CN110911496B - Thin film transistor, preparation method of thin film transistor and display panel - Google Patents
Thin film transistor, preparation method of thin film transistor and display panel Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 107
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 107
- 239000010703 silicon Substances 0.000 claims abstract description 107
- 229910052751 metal Inorganic materials 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 80
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 71
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 238000011065 in-situ storage Methods 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000009413 insulation Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 3
- 230000007613 environmental effect Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 89
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 28
- 239000001257 hydrogen Substances 0.000 abstract description 28
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 28
- 239000007769 metal material Substances 0.000 abstract description 12
- 238000005516 engineering process Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 361
- 239000007789 gas Substances 0.000 description 27
- 238000010586 diagram Methods 0.000 description 13
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
- 238000002161 passivation Methods 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 6
- 229910052733 gallium Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 239000012044 organic layer Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005234 chemical deposition Methods 0.000 description 5
- 239000011787 zinc oxide Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- ZPZCREMGFMRIRR-UHFFFAOYSA-N molybdenum titanium Chemical compound [Ti].[Mo] ZPZCREMGFMRIRR-UHFFFAOYSA-N 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000002207 thermal evaporation Methods 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/44—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/38 - H01L21/428
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
In the thin film transistor, the method for manufacturing the thin film transistor, and the display panel provided by the present application, a first silicon oxide layer is formed on the conductive channel pattern and the substrate, and plasma in-situ processing is performed on the first silicon oxide layer to form a first silicon oxynitride layer; the technical means of forming the grid metal layer on the first silicon oxynitride layer and etching the grid metal layer and the first silicon oxynitride layer to form the grid pattern and the grid insulation layer pattern is that the silicon oxide material is converted into the silicon oxynitride material by adopting a plasma in-situ treatment technology, so that the upper interface and the lower interface of the grid insulation layer which are in contact with the conductive channel layer and the grid metal layer are both the silicon oxynitride material with low hydrogen content, and the technical problem of improving the dielectric constant of the insulating medium layer and the interface characteristic of the insulating medium layer and the metal material on the premise that the insulating medium layer has low hydrogen element content is solved.
Description
Technical Field
The application relates to the field of display, in particular to a thin film transistor, a preparation method of the thin film transistor and a display panel.
Background
Currently, indium gallium zinc oxide materials are widely used in the preparation of array substrates in the field of large-size, high-performance active matrix organic light emitting diode display technology due to their excellent properties. However, the characteristics of the indium gallium zinc oxide material mainly depend on the hydrogen content in the adjacent dielectric layer, and the characteristics of the indium gallium zinc oxide material directly affect the parameters of the thin film transistor, such as threshold voltage, mobility and reliability, so the SiO with low hydrogen content is generally adopted in the prior art 2 The material serves as an insulating dielectric layer material.
In recent years, siO has been used as a material for the formation of films 2 The material is widely applied and SiO is found 2 The dielectric constant of the material is low, the improvement of the performance of the thin film transistor and the reduction of the capacitance area are limited to a certain extent, and SiO 2 Poor interfacial properties between the material and the metal material may lead to process structureDestruction and failure.
Therefore, it is difficult for panel manufacturers to try to overcome the above-mentioned problems, such as the dielectric constant of the insulating dielectric layer material and the interface characteristics between the insulating dielectric layer material and the metal material, while the insulating dielectric layer material has a low hydrogen content.
Disclosure of Invention
The application provides a thin film transistor, a preparation method of the thin film transistor and a display panel, which can solve the technical problems that the dielectric constant of an insulating dielectric layer material and the interface characteristic of the insulating dielectric layer material and an indium gallium zinc oxide material are improved on the premise that the insulating dielectric layer material of the existing display panel has low hydrogen element content.
The application provides a preparation method of a thin film transistor, which comprises the following steps:
providing a substrate, and sequentially forming a buffer layer and a conductive channel pattern on the substrate;
forming a first silicon oxide layer on the conductive channel pattern and the substrate, and carrying out plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer;
forming a gate metal layer on the first silicon oxynitride layer, and etching the gate metal layer and the first silicon oxynitride layer to form a gate pattern and a gate insulation layer pattern;
forming an insulating layer on the gate pattern, the gate insulating layer pattern, the conductive channel pattern, and the substrate, and forming a first via hole and a second via hole on the insulating layer;
and forming a source electrode pattern and a drain electrode pattern on the insulating layer, wherein the source electrode pattern is connected with the conductive channel pattern through the first via hole, and the drain electrode pattern is connected with the conductive channel pattern through the second via hole.
In the method for manufacturing a thin film transistor provided in the present application, after the steps of forming a first silicon oxide layer on the conductive channel pattern and the substrate and performing plasma in-situ processing on the first silicon oxide layer to form a first silicon oxynitride layer, the method further includes:
forming a second silicon dioxide layer on the first silicon oxynitride layer, and carrying out plasma in-situ treatment on the second silicon dioxide layer so as to sequentially form a silicon oxide layer and a second silicon oxynitride layer on the first silicon oxynitride layer;
the method comprises the steps of forming a grid metal layer on the first silicon oxynitride layer, etching the grid metal layer and the first silicon oxynitride layer to form a grid pattern and a grid insulation layer pattern, and specifically comprises the following steps: and forming a grid metal layer on the second silicon oxynitride layer, and etching the grid metal layer, the second silicon oxynitride layer, the silicon oxide layer and the first silicon oxynitride layer to form a grid pattern and a grid insulation layer pattern with a three-layer structure, wherein the first silicon oxynitride layer and the second silicon oxynitride layer are both low-hydrogen-content film layers.
In the method for manufacturing a thin film transistor provided by the present application, the step of performing plasma in-situ processing on the second silicon oxide layer to sequentially form a silicon oxide layer and a second silicon oxynitride layer on the first silicon oxynitride layer includes: adjusting the environmental temperature, the impact force degree of plasma gas and the gas flow;
adopting the plasma gas to impact the surface of the second silicon dioxide layer;
and after keeping for a preset time, sequentially forming a silicon oxide layer and a second silicon oxynitride layer with a preset thickness on the first silicon oxynitride layer.
In the method for manufacturing a thin film transistor provided by the present application, the first silicon oxynitride layer covers the conductive channel pattern, and the thickness of the first silicon oxynitride layer is 50 to 100 angstroms.
In the method for manufacturing a thin film transistor provided by the present application, the step of performing plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer includes:
adjusting the impact force and the gas flow of the plasma gas;
and adopting the plasma gas to impact the surface of the first silicon oxide layer, so that the surface of the first silicon oxide layer close to one side of the conductive channel pattern and the surface of the first silicon oxide layer close to one side of the gate metal pattern are both nitrided to form a first silicon oxynitride layer.
In the preparation method of the thin film transistor provided by the application, the plasma gas comprises N 2 O and N 2 At least one of (1).
In the method for manufacturing a thin film transistor provided by the present application, the first silicon oxynitride layer covers the conductive channel pattern, and the thickness of the first silicon oxynitride layer is 50 to 100 angstroms.
In the method for manufacturing a thin film transistor provided by the present application, the step of forming a gate metal layer on the first silicon oxynitride layer, and etching the gate metal layer and the first silicon oxynitride layer to form a gate pattern and a gate insulating layer pattern includes:
forming a grid metal layer on the first silicon oxynitride layer, and carrying out a wet etching process on the grid metal layer by taking a photomask as a mask to form a grid metal layer pattern;
and carrying out dry etching process on the gate insulating layer by taking the gate metal layer pattern as a mask and the photomask as a mask to form the gate insulating layer pattern.
The present application also provides a thin film transistor, including:
a substrate;
a buffer layer disposed on the substrate;
a conductive channel pattern on the buffer layer;
a gate insulating layer pattern disposed on the conductive channel pattern, the gate insulating layer pattern including a first silicon oxynitride layer pattern, the first silicon oxynitride layer pattern being a low hydrogen content film;
a gate metal layer pattern disposed on the gate insulating layer pattern;
an insulating layer disposed on the gate metal layer pattern, the insulating layer covering the gate metal layer pattern, the gate insulating layer pattern, and the conductive channel pattern;
a source/drain pattern disposed on the insulating layer, the source pattern being connected to the conductive channel pattern through a first via hole, and the drain pattern being connected to the conductive channel pattern through a second via hole.
In the thin film transistor that this application provided, the gate insulation layer pattern is the three layer construction pattern, the gate insulation layer pattern is including the first silicon oxynitride layer pattern, silicon oxide layer pattern and the second silicon oxynitride layer pattern that stack gradually and arrange, first silicon oxynitride layer pattern and second silicon oxynitride layer pattern are the rete of low hydrogen content.
In the thin film transistor provided by the present application, the thickness of the silicon oxide layer is 0 to 1450 angstroms, the thickness of the first silicon oxynitride layer pattern is 50 to 100 angstroms, and the thickness of the second silicon oxynitride layer pattern is 50 to 100 angstroms.
The application also provides a display panel, which comprises the thin film transistor.
In the thin film transistor, the preparation method of the thin film transistor and the display panel provided by the application, the silicon oxide material is converted into the silicon oxynitride material by adopting the plasma in-situ treatment technology, so that the upper and lower interfaces of the gate insulating layer in contact with the conductive channel layer and the gate metal layer are both the silicon oxynitride material with low hydrogen content, and the technical problems of improving the dielectric constant of the insulating dielectric layer material and the interface characteristic of the insulating dielectric layer material and the metal material on the premise of meeting the requirement that the insulating dielectric layer material has low hydrogen content are solved.
Drawings
In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic view of a first sub-flow of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 3 is a second sub-flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 4 is another schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 5 is a third sub-flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a thin film transistor provided in the present embodiment when a gate insulating layer pattern and a gate metal layer pattern are formed;
fig. 7 is a schematic structural diagram of a thin film transistor provided in an embodiment of the present application;
fig. 8 is another schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application;
fig. 10 is another schematic structural diagram of a display panel according to an embodiment of the present application.
Detailed Description
The technical solution in the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It should be apparent that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application, are within the scope of protection of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 1, a method for manufacturing a thin film transistor provided in an embodiment of the present application includes the following steps: 101. providing a substrate, and sequentially forming a buffer layer and a conductive channel pattern on the substrate; 102. forming a first silicon oxide layer on the conductive channel pattern and the substrate, and carrying out plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer; 103. forming a gate metal layer on the first silicon oxynitride layer, and etching the gate metal layer and the first silicon oxynitride layer to form a gate pattern and a gate insulation layer pattern; 104. forming an insulating layer on the gate pattern, the gate insulating layer pattern, the conductive channel pattern, and the substrate, and forming a first via hole and a second via hole on the insulating layer; 105. and forming a source electrode pattern and a drain electrode pattern on the insulating layer, wherein the source electrode pattern is connected with the conductive channel pattern through the first through hole, and the drain electrode pattern is connected with the conductive channel pattern through the second through hole.
It can be understood that, the gate electrode is generally made of a metal material, wherein, the copper metal material is used most, the adhesion property between the insulating layer and the gate electrode is mainly reflected in the contact property between the insulating layer material and the gate electrode material, and because the insulating layer material and the gate electrode material generate a stress mismatch problem during the thermal deposition process, if the difference between the adhesion forces between the insulating layer material and the gate electrode material is large, the gate electrode material with a large area will fall off, thereby causing the damage and failure of the process structure; the upper and lower interfaces of the gate insulating layer pattern are made of SiON material, the gate insulating layer is in contact with the gate electrode, and the SiON material is in contact with the currently used SiO 2 Compared with the material, the adhesion property between the SiON material and the metal material is higher than that of SiO 2 Adhesion properties between materials and metal materials.
It is understood that the conductive channel layer serves as a core of the thin film transistor device, and the interface characteristics between the material of the conductive channel layer and the material of the insulating layer may affect the carrier transport during the carrier transport process, because the carrier transport channel is formed at the interface where the conductive channel layer contacts the gate insulating layer, which is formed of SiON material at the interface where the gate insulating layer contacts the conductive channel layer, and SiO during the forward bias application process 2 SiON materials have higher dielectric constants than materials, and therefore, the gate insulating layer is in contact with the conductive channel layerThe interface has lower interface state concentration, namely lower defect concentration, and the high defect concentration can generate defect scattering in the carrier transmission process to reduce the mobility, and in addition, the high defect density can reduce the subthreshold swing of the thin film transistor device and influence the switching characteristic of the thin film transistor device.
It can be understood that hydrogen content in the adjacent dielectric layer of the conductive channel layer also affects parameters such as threshold voltage, mobility and reliability of the thin film transistor, so that a chemical deposition method which is basically adopted for forming a SiNO material in the prior art and has low hydrogen content is required to be selected, the SiNO material is formed by plasma in-situ treatment, and the specific method is to firstly form a SiO material by adopting the chemical deposition method 2 Film of material, then treating the SiO with a plasma gas containing nitrogen 2 Film of material, thereby making SiO 2 The material is converted to a SiNO material. SiH is generally used when chemical deposition is used to form SiNO material 4 +NH 3 The reaction gas of (1); formation of SiO by chemical deposition 2 As the material, siH is generally used 4 +N 2 A reactant gas of O; in-situ processing of SiO by plasma 2 In the process of converting the material into the SiNO material, plasma gas containing nitrogen element is adopted, and the plasma gas is generally N 2 O and N 2 At least one of (1). Therefore, compared with the SiNO material prepared by a chemical deposition method, the SiNO material prepared by the method has the advantages that the incorporation amount of hydrogen elements is not high, and the premise that the insulating dielectric layer material has low hydrogen elements can be met.
Specifically, please refer to fig. 1 and fig. 2, wherein fig. 2 is a first sub-flow diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 1 and fig. 2, step 102 specifically includes: 1021. forming a first silicon oxide layer on the conductive channel pattern and the substrate; 1022. adjusting the impact force and the gas flow of the plasma gas; 1023. and adopting plasma gas to impact the surface of the first silicon oxide layer, so that the surface of the first silicon oxide layer close to one side of the conductive channel pattern and the surface of the first silicon oxide layer close to one side of the gate metal pattern are both nitrided to form a first silicon oxynitride layer.
Wherein the plasma gas comprises N 2 O and N 2 Of course using another gas such as NH 3 Can also make SiO 2 Conversion of material to SiNO but using N 2 O and N 2 By contrast, with NH 3 The SiNO material produced as a plasma gas has a high hydrogen content. So this application is to use N 2 O and N 2 By using SiO as plasma gas 2 The material is converted into the SiNO material, and in the processing process, factors influencing the content of hydrogen elements in the SiNO material further comprise the impact strength, the gas flow and the impact time of plasma gas, so that the impact strength, the gas flow and the impact time of the plasma gas are accurately controlled, and the hydrogen content in the formed SiNO material is enabled to be the lowest.
In one embodiment, the first silicon oxynitride layer has a thickness of 50 to 100 angstroms and covers the conductive channel layer.
Specifically, please refer to fig. 1 and fig. 3, and fig. 3 is a second sub-flow diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 1 and fig. 3, step 103 specifically includes: 1031. forming a grid metal layer on the first silicon oxynitride layer; 1032. and performing a wet etching process on the gate metal layer by using a photomask as a mask to form the gate metal layer pattern 1033, and performing a dry etching process on the gate insulating layer by using the photomask as a mask to form the gate insulating layer pattern.
As can be understood, because the gate insulating layer pattern and the gate metal layer pattern are formed by using the same photomask, wherein the photomask comprises a light-transmitting region and light-shielding regions located at two sides of the light-transmitting region, an orthographic projection of the light-transmitting region on the substrate coincides with an orthographic projection of the gate insulating layer pattern on the substrate, and an orthographic projection of the light-transmitting region on the substrate coincides with an orthographic projection of the gate metal layer pattern on the substrate.
Further, referring to fig. 4, fig. 4 is another schematic flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure, and as shown in fig. 5, the method for manufacturing a thin film transistor according to an embodiment of the present disclosure includes the following steps: 201. providing a substrate, and sequentially forming a buffer layer and a conductive channel pattern on the substrate; 202. forming a first silicon oxide layer on the conductive channel pattern and the substrate, and carrying out plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer; 203. forming a second silicon dioxide layer on the first silicon oxynitride layer, and carrying out plasma in-situ treatment on the second silicon dioxide layer so as to sequentially form a silicon oxide layer and a second silicon oxynitride layer on the first silicon oxynitride layer; 204. forming a grid metal layer on the second silicon oxynitride layer, and etching the grid metal layer, the second silicon oxynitride layer, the silicon oxide layer and the first silicon oxynitride layer to form a grid pattern and a grid insulation layer pattern with a three-layer structure; 205. forming an insulating layer on the gate pattern, the gate insulating layer pattern, the conductive channel pattern, and the substrate, and forming a first via hole and a second via hole on the insulating layer; 206. and forming a source electrode pattern and a drain electrode pattern on the insulating layer, wherein the source electrode pattern is connected with the conductive channel pattern through the first through hole, and the drain electrode pattern is connected with the conductive channel pattern through the second through hole.
Specifically, please refer to fig. 1 and 5, wherein fig. 5 is a third sub-flow diagram of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 1 and fig. 3, step 203 specifically includes: 2031. forming a second silicon oxide layer on the first silicon oxynitride layer; 2032. adjusting the environmental temperature, the impact force degree of the plasma gas and the gas flow; 2033. adopting plasma gas to impact the surface of the second silicon dioxide layer; 2034. and after keeping the preset time, sequentially forming a silicon oxide layer and a second silicon oxynitride layer with a preset thickness on the first silicon oxynitride layer.
Wherein, the thickness of the first silicon oxynitride layer is 50-100 angstroms, the thickness of the silicon oxide layer is 0-1450 angstroms, and the thickness of the second silicon oxynitride layer is 50-100 angstroms. It is understood that the thickness of the second silicon oxynitride layer formed can be controlled by the process parameters of the ambient temperature, the impact force of the plasma gas, and the impact time.
Further, referring to fig. 6, fig. 6 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure when a gate insulating layer pattern and a gate metal layer pattern are formed. As shown in fig. 6, the thin film transistor according to the embodiment of the present invention includes a substrate 301, a buffer layer 302, a conductive channel pattern 303, a gate insulating layer pattern 304, and a gate metal layer pattern 305.
The buffer layer 302 is disposed on the substrate 301, the conductive channel pattern 303 is disposed on the buffer layer 302, the gate insulating layer pattern 304 is disposed on the conductive channel pattern 303, the gate metal layer pattern 304 is a three-layer stacked structure, the gate metal layer pattern 304 includes a first silicon oxynitride layer pattern 3041, a silicon oxide layer pattern 3042, and a second silicon oxynitride layer pattern 3043, which are sequentially stacked, and the gate metal layer pattern 305 is disposed on the gate insulating layer pattern 304.
Here, it can be understood that there is a difference between the actually formed gate metal layer pattern 305 and the gate insulating layer pattern 304, and the gate metal layer pattern 305 is smaller than the gate insulating layer pattern 304. Although the gate metal layer pattern 305 and the gate insulating layer pattern 304 are formed under the same photoresist mask condition using the same mask, different processing methods are used, the method for forming the gate metal layer pattern 305 is wet etching, and the method for forming the gate insulating layer pattern 304 is dry plasma etching, because the lateral etching rate of the wet etching is not much different from the lateral etching rate under the same photoresist mask condition, the wet etching results in a larger pattern size loss due to its isotropic property compared with the dry plasma etching, so that the finally formed gate metal layer pattern 305 is smaller than the gate insulating layer pattern 304.
In one embodiment, after the gate metal layer pattern 305 is formed, the conductive channel pattern 303, which is not protected by the gate insulating layer pattern 304, may be further processed to form N + conductor regions for connection with the source and drain electrodes; the N + conductor region is formed by plasma bombardment, and more particularly, by physically bombarding the conductive channel pattern 303, which is not protected by the gate insulating layer pattern 304, with an inert gas, which is generally helium, as a process gas. The conductive channel pattern 303 protected by the gate insulating layer pattern 304 is not processed as a thin film transistor channel.
In the preparation method of the thin film transistor, the silicon oxide material is converted into the silicon oxynitride material by adopting the plasma in-situ treatment technology, so that the upper and lower interfaces of the gate insulating layer in contact with the conductive channel layer and the gate metal layer are both the silicon oxynitride material with low hydrogen content, and the technical problem of improving the dielectric constant of the insulating dielectric layer material and the interface characteristic of the insulating dielectric layer material and the metal material on the premise of meeting the requirement that the insulating dielectric layer material has low hydrogen content is solved.
Referring to fig. 7, fig. 7 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 7, the thin film transistor provided in the embodiment of the present application includes a substrate 401, a buffer layer 402, a conductive channel pattern 403, a gate insulating layer pattern 404, a gate metal layer pattern 405, an insulating layer 406, a source pattern 407, and a drain pattern 408.
Wherein the buffer layer 402 is disposed on the substrate 401, the conductive channel pattern 03 is disposed on the buffer layer 402, the gate insulating layer pattern 404 is disposed on the conductive channel pattern 403, and the gate metal layer pattern 404 is a three-layer stacked structure, the gate metal layer pattern 404 includes a first silicon oxynitride layer pattern 4041, a silicon oxide layer pattern 4042, and a second silicon oxynitride layer pattern 4043, which are sequentially stacked, the gate metal layer pattern 405 is disposed on the gate insulating layer pattern 04, the insulating layer 406 is disposed on the gate metal layer pattern 405, and the insulating layer 406 covers the gate metal layer pattern 405, the gate insulating layer pattern 04, and the conductive channel pattern 403, the source pattern 407 and the drain pattern 408 are both disposed on the insulating layer 406, and the source pattern 407 is connected with the conductive channel pattern 403 through a first via 4071, and the drain pattern 408 is connected with the conductive channel pattern 403 through a second via 4081.
It is understood that the material constituting the first and second silicon oxynitride layer patterns 4041 and 4043 has a low hydrogen content, so that a negative bias phenomenon of a threshold voltage due to the high hydrogen content can be prevented, and mobility and reliability of the thin film transistor can be improved.
In one embodiment, the gate insulating layer pattern 404 has a thickness of 100 to 1500 angstroms, the first silicon oxynitride layer pattern 4041 has a thickness of 50 to 100 angstroms, and the second silicon oxynitride layer pattern 3043 has a thickness of 50 to 100 angstroms.
Wherein, in one embodiment, the material of the buffer layer 402 comprises Si 3 N 4 、SiO 2 And SiON; the buffer layer 402 may be a single layer film or a double layer film; the thickness of the buffer layer is 1000-5000 angstroms; the specific definition of the buffer layer 402 may be determined by the process requirements.
In one embodiment, the material of the conductive channel pattern 403 includes one of indium gallium zinc oxide, indium tin zinc oxide, and indium gallium zinc tin oxide, although other materials may be selected, and the specific selection of which material to form the conductive channel pattern 403 is determined by specific process requirements; the conductive channel pattern 403 has a thickness of 100 to 1000 angstroms.
Among them, in one embodiment, a material constituting the gate metal layer pattern 405 is one of molybdenum and copper, titanium and copper, or molybdenum-titanium alloy and copper; the thickness of the gate metal layer pattern 405 is 2000 to 10000 angstroms.
Wherein, in one embodiment, the insulating layer 406 has a thickness of 3000 to 10000 angstroms.
In one embodiment, the source electrode pattern 407 and the drain electrode pattern 408 have a double-layer metal structure, and the source electrode pattern 407 and the drain electrode pattern 408 are made of molybdenum and copper, titanium and copper, or molybdenum-titanium alloy and copper; the thickness of the source pattern 407 is 2000 to 8500 angstroms, and the thickness of the drain pattern 407 is 2000 to 8500 angstroms.
Referring to fig. 8, fig. 8 is another schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure. As shown in fig. 8, the thin film transistor provided in the embodiment of the present application includes a substrate 501, a buffer layer 502, a conductive channel pattern 503, a gate insulating layer pattern 504, a gate metal layer pattern 505, an insulating layer 506, a source pattern 507, and a drain pattern 508.
Wherein the buffer layer 502 is disposed on the substrate 501, the conductive channel pattern 503 is on the buffer layer 502, the gate insulating layer pattern 504 is disposed on the conductive channel pattern 503, and the gate insulating layer pattern 504 is a low hydrogen content silicon oxynitride film, the gate metal layer pattern 505 is disposed on the gate insulating layer pattern 504, the insulating layer 506 is disposed on the gate metal layer pattern 505, and the insulating layer 506 covers the gate metal layer pattern 505, the gate insulating layer pattern 504, and the conductive channel pattern 503, the source pattern 507 and the drain pattern 508 are both disposed on the insulating layer 506, and the source pattern 507 is connected to the conductive channel pattern 503 through the first via 5071, and the drain pattern 508 is connected to the conductive channel pattern 503 through the second via 5081.
It is to be understood that the thin film transistor shown in fig. 8 is different from the thin film transistor shown in fig. 7 in that the gate insulating layer pattern 504 is formed of only one layer of a silicon oxynitride material having a low hydrogen content, and the gate metal layer pattern 404 has a three-layer stacked structure including a first silicon oxynitride layer pattern 4041, a silicon oxide layer pattern 4042, and a second silicon oxynitride layer pattern 4043 which are sequentially stacked. Compared with the thin film transistor shown in fig. 7, the thin film transistor shown in fig. 8 can better solve the technical problem of improving the dielectric constant of the insulating dielectric layer material and the interface characteristic between the insulating dielectric layer material and the metal material on the premise that the insulating dielectric layer material has low hydrogen content, and can also achieve better technical effect, but the plasma is limited by N atoms in SiO 2 The diffusion depth in the film layer can not form an SiON layer with enough thickness in a single treatment process, and if the thickness of the grid insulation layer is too low, the grid breakdown voltage of the thin film transistor in the working process can be greatly limited, so that the thin film transistor is easy to lose efficacy, even if the mode of multiple plasma in-situ treatment is adopted to carry out the cumulative SiONThe SiON material with a certain thickness can be used as the gate insulation layer, but the adoption of the method has the disadvantages of increased processing time and complex processing flow.
In the thin film transistor formed in the embodiment of the application, the silicon oxide material is converted into the silicon oxynitride material by adopting the plasma in-situ treatment technology, so that the upper and lower interfaces of the gate insulating layer in contact with the conductive channel layer and the gate metal layer are both made of the silicon oxynitride material with low hydrogen content, and the technical problems of improving the dielectric constant of the insulating dielectric layer material and the interface characteristic of the insulating dielectric layer material and the metal material on the premise of meeting the requirement that the insulating dielectric layer material has low hydrogen content are solved.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 9, the display panel provided by the embodiment of the present application includes a substrate 601, a buffer layer 602, a conductive channel pattern 603, a gate insulating layer pattern 604, a gate metal layer pattern 605, an insulating layer 606, a source pattern 607, a drain pattern 608, a passivation layer 609, a planarization layer 610, an anode pattern 611, an organic layer 612, and a light emitting layer pattern 613.
Wherein the buffer layer 602 is disposed on the substrate 601, the conductive channel pattern 603 is on the buffer layer 602, the gate insulating layer pattern 604 is disposed on the conductive channel pattern 603, the gate metal layer pattern 605 is disposed on the gate insulating layer pattern 604, the insulating layer 606 is disposed on the gate metal layer pattern 605, and the insulating layer 606 covers the gate metal layer pattern 605, the gate insulating layer pattern 604, and the conductive channel pattern 603, the source pattern 607 and the drain pattern 608 are both disposed on the insulating layer 606, and the source pattern 607 is connected with the conductive channel pattern 603 through a first via 6071, the drain pattern 608 is connected with the conductive channel pattern 603 through a second via 6081, the passivation layer 609 is disposed on the source pattern 607 and the drain pattern 608, and covers the source pattern 607 and the drain pattern 608, the planarization layer 610 is disposed on the passivation layer 609, the anode pattern 611 is disposed on the planarization layer 610, and the anode pattern 611 is connected with the drain pattern 608 through a third via 6111, the organic layer 612 is disposed on the anode pattern 611, the organic layer 612 is disposed with the through via 6121, the through via groove 609, and the light emitting layer 611 is connected with the anode pattern 61613.
Wherein, in one embodiment, the material comprising the passivation layer 609 is SiO 2 A film; the passivation layer 609 has a thickness of 1000 to 5000 angstroms.
In one embodiment, the planarization layer 610 may be a photoresist layer with the same composition or a photoresist layer with different compositions, and the thickness of the planarization layer 610 is 10000-20000 angstroms.
In one embodiment, the material of the anode pattern 611 may be indium tin oxide, and the thickness of the anode pattern 611 is 500 to 1000 angstroms.
In one embodiment, the organic layer 612 may be a photoresist layer with the same composition or a photoresist layer with different compositions, and the thickness of the organic layer 612 is 10000 to 20000 angstroms.
Referring to fig. 10, fig. 10 is another schematic structural diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 10, the display panel provided in the embodiment of the present application includes a substrate 701, a buffer layer 702, a conductive channel pattern 703, a gate insulating layer pattern 704, a gate metal layer pattern 705, an insulating layer 706, a source electrode pattern 707, a drain electrode pattern 708, a passivation layer 709, a planarization layer 710, an anode pattern 711, an organic layer 712, and a light emitting layer pattern 713.
Wherein the buffer layer 702 is disposed on the substrate 701, the conductive channel pattern 703 is on the buffer layer 702, the gate insulating layer pattern 704 is disposed on the conductive channel pattern 703, the gate metal layer pattern 504 is a three-layer stacked structure, the gate metal layer pattern 704 includes a first silicon oxynitride layer pattern 7041, a silicon oxide layer pattern 7042, and a second silicon oxynitride layer pattern 7043, which are sequentially stacked, the gate metal layer pattern 705 is disposed on the gate insulating layer pattern 704, the insulating layer 706 is disposed on the gate metal layer pattern 705, and the insulating layer 706 covers the gate metal layer pattern 705, the gate insulating layer pattern 704, and the conductive channel pattern 703, the source pattern 707 and the drain pattern 708 are both disposed on the insulating layer 707, and the source pattern 707 is connected to the conductive channel pattern 703 through a first via 7071, the drain pattern 708 is connected to the conductive channel pattern 703 through a second via 7081, the passivation layer 709 is disposed on the source pattern 707 and the drain pattern 708, and covers the source pattern 707 and the drain pattern 708, the planarization layer 710 is disposed on the passivation layer 709, the anode pattern 711 is disposed on the passivation layer 71711, and the anode 71711, and the organic light emitting layer 7121 is disposed on the anode 71711, and the organic light emitting layer 71711.
In the display panel formed in the embodiment of the application, the silicon oxide material is converted into the silicon oxynitride material by adopting the plasma in-situ treatment technology, so that the upper and lower interfaces of the gate insulating layer in contact with the conductive channel layer and the gate metal layer are both the silicon oxynitride material with low hydrogen content, and the technical problem of improving the dielectric constant of the insulating dielectric layer material and the interface characteristic of the insulating dielectric layer material and the metal material on the premise of meeting the requirement that the insulating dielectric layer material has low hydrogen content is solved.
The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A preparation method of a thin film transistor is characterized by comprising the following steps:
providing a substrate, and sequentially forming a buffer layer and a conductive channel pattern on the substrate;
forming a first silicon oxide layer on the conductive channel pattern and the substrate, and carrying out plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer;
forming a second silicon dioxide layer on the first silicon oxynitride layer, and carrying out plasma in-situ treatment on the second silicon dioxide layer so as to sequentially form a silicon oxide layer and a second silicon oxynitride layer on the first silicon oxynitride layer; forming a gate metal layer on the second silicon oxynitride layer, and etching the gate metal layer, the second silicon oxynitride layer, the silicon oxide layer and the first silicon oxynitride layer to form a gate pattern and a gate insulation layer pattern of a three-layer structure, wherein the first silicon oxynitride layer and the second silicon oxynitride layer are both low-hydrogen-content film layers;
forming an insulating layer on the gate pattern, the gate insulating layer pattern, the conductive channel pattern, and the substrate, and forming a first via hole and a second via hole on the insulating layer;
and forming a source electrode pattern and a drain electrode pattern on the insulating layer, wherein the source electrode pattern is connected with the conductive channel pattern through the first via hole, and the drain electrode pattern is connected with the conductive channel pattern through the second via hole.
2. The method according to claim 1, wherein the step of performing plasma in-situ treatment on the second silicon oxide layer to sequentially form a silicon oxide layer and a second silicon oxynitride layer on the first silicon oxynitride layer comprises:
adjusting the environmental temperature, the impact force degree of the plasma gas and the gas flow;
adopting the plasma gas to impact the surface of the second silicon dioxide layer;
and after keeping the preset time, sequentially forming a silicon oxide layer and a second silicon oxynitride layer with preset thickness on the first silicon oxynitride layer.
3. The method according to claim 1, wherein the second silicon oxynitride layer has a thickness of 50 to 100 angstroms, and the second silicon oxide layer has a thickness of 100 to 1500 angstroms.
4. The method according to claim 1, wherein the step of performing plasma in-situ treatment on the first silicon oxide layer to form a first silicon oxynitride layer comprises:
adjusting the impact force and the gas flow of the plasma gas;
and adopting the plasma gas to impact the surface of the first silicon oxide layer, so that the surface of the first silicon oxide layer close to one side of the conductive channel pattern and the surface of the first silicon oxide layer close to one side of the gate pattern are both nitrided to form a first silicon oxynitride layer.
5. The method for manufacturing a thin film transistor according to claim 2 or 4, wherein the plasma gas includes at least one of N2O and N2.
6. The method of manufacturing a thin film transistor according to claim 1, wherein the first silicon oxynitride layer covers the conductive channel pattern, and a thickness of the first silicon oxynitride layer is 50 to 100 angstroms.
7. The method according to claim 1, wherein the step of forming a gate metal layer on the first silicon oxynitride layer and etching the gate metal layer and the first silicon oxynitride layer to form a gate pattern and a gate insulating layer pattern comprises:
forming a gate metal layer on the first silicon oxynitride layer;
carrying out a wet etching process on the grid metal layer by taking a photomask as a mask to form a grid metal layer pattern;
and carrying out dry etching process on the gate insulating layer by taking the gate metal layer pattern as a mask and the photomask as a mask to form the gate insulating layer pattern.
8. A thin film transistor, comprising:
a substrate;
a buffer layer disposed on the substrate
A conductive channel pattern on the buffer layer;
the grid insulation layer pattern is arranged on the conductive channel pattern, the grid insulation layer pattern is a three-layer structure pattern, the grid insulation layer pattern comprises a first silicon oxynitride layer pattern, a silicon oxide layer pattern and a second silicon oxynitride layer pattern which are sequentially arranged in a stacked mode, and the first silicon oxynitride layer pattern and the second silicon oxynitride layer pattern are both low-hydrogen-content film layers;
a gate metal layer pattern disposed on the gate insulating layer pattern;
an insulating layer disposed on the gate metal layer pattern, the insulating layer covering the gate metal layer pattern, the gate insulating layer pattern, and the conductive channel pattern;
a source/drain pattern disposed on the insulating layer, the source pattern being connected to the conductive channel pattern through a first via hole, and the drain pattern being connected to the conductive channel pattern through a second via hole.
9. The thin film transistor of claim 8, wherein the silicon oxide layer has a thickness of 0 to 1450 angstroms, the first silicon oxynitride layer pattern has a thickness of 50 to 100 angstroms, and the second silicon oxynitride layer pattern has a thickness of 50 to 100 angstroms.
10. A display panel comprising the thin film transistor according to any one of claims 8 to 9.
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