CN110908199A - Array substrate and liquid crystal display panel - Google Patents
Array substrate and liquid crystal display panel Download PDFInfo
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- CN110908199A CN110908199A CN201911119350.9A CN201911119350A CN110908199A CN 110908199 A CN110908199 A CN 110908199A CN 201911119350 A CN201911119350 A CN 201911119350A CN 110908199 A CN110908199 A CN 110908199A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Abstract
The invention provides an array substrate and a liquid crystal display panel, wherein a part of data lines and a grid electrode are arranged in the same layer, the other part of data lines and a source/drain electrode layer are arranged in the same layer, the data lines are arranged between the grid electrode layer and the source/drain electrode layer in an alternative wiring mode and are electrically connected through via holes, the thickness of an insulating layer between the data lines and a common electrode layer is increased, the data lines arranged in different layers form induction capacitors, parasitic capacitors between the data lines and the common electrode layer are reduced, and the normal display capability of certain special pictures in the liquid crystal display panel is improved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate and a liquid crystal display panel with the array substrate.
Background
The liquid crystal display can be classified into an active matrix type and a passive matrix type depending on the driving method. The active matrix liquid crystal display uses a thin film transistor as a driving switch. The thin film transistor is divided into an amorphous silicon thin film transistor and a low temperature polysilicon thin film transistor according to the material of the active layer.
Compared with amorphous silicon thin film transistors, LTPS TFTs have many advantages, such as high aperture ratio, high resolution, and high display quality, and can integrate driving circuits on glass substrates. Compared with five photo-mask processes for fabricating the amorphous silicon thin film transistor, the low temperature polysilicon thin film transistor has high process technology complexity and requires more photo-mask process steps, which may require eight or nine photo-masks, thereby consuming a large amount of manufacturing cost. In order to reduce the number of photomasks, the flat layer is omitted, but the flat layer brings a series of risks of display effects, when the flat layer is absent, the distance between the wiring for transmitting the data signal to the pixel and the common electrode layer is short, so that the parasitic capacitance between the data signal and the common electrode layer is increased, and the liquid crystal display panel has a risk of abnormal display in some special pictures.
In summary, an array substrate and a liquid crystal display panel having the same are needed to solve the technical problem that the TFT device in the prior art omits a planarization layer, and the parasitic capacitance between the routing line for transmitting data signals to the pixels and the common signal is large, which affects the normal display of some special pictures in the liquid crystal display panel.
Disclosure of Invention
The invention provides an array substrate and a liquid crystal display panel with the same, which can solve the technical problems that in the prior art, a flat layer is omitted in a TFT (thin film transistor) device, parasitic capacitance between a wiring for transmitting a data signal to a pixel and a common signal is large, and normal display of some special pictures in the liquid crystal display panel is influenced.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides an array substrate, wherein a sub-pixel is formed on the array substrate, and the sub-pixel comprises a substrate, a shading layer arranged on the substrate, a buffer layer arranged on the substrate and covering the shading layer, a polycrystalline silicon layer arranged on the buffer layer and corresponding to the shading layer, a first insulating layer arranged on the polycrystalline silicon layer, a first metal layer arranged on the first insulating layer, a second insulating layer arranged on the first insulating layer and covering the first metal layer, a second metal layer arranged on the second insulating layer, a third insulating layer arranged on the second insulating layer and covering the second metal layer, a common electrode arranged on the third insulating layer, a passivation layer arranged on the common electrode, and a pixel electrode arranged on the passivation layer.
The first metal layer comprises a grid electrode, a scanning line and a first data line, the second metal layer comprises a source electrode, a drain electrode and a second data line, and the first data line is electrically connected with the second data line through a through hole.
According to a preferred embodiment of the present invention, the second insulating layer and the third insulating layer are both inorganic thin films, and the material of the inorganic thin films is one or more of silicon dioxide, silicon nitride, and silicon oxynitride.
According to a preferred embodiment of the present invention, the via hole is located in the second insulating layer, one end of the via hole is conducted with the source or the drain, and the other end is conducted with the first metal layer.
According to a preferred embodiment of the present invention, the second data line is electrically connected to the drain, and the second data line is insulated from the source; or, the second data line is electrically connected with the source electrode, and the second data and the drain electrode are arranged in an insulating mode.
According to a preferred embodiment of the present invention, the polysilicon layer includes a semiconductor layer and a doped layer located on a surface of the semiconductor layer.
According to a preferred embodiment of the present invention, a touch signal line is further disposed on a surface of the second insulating layer, and the touch signal line is electrically connected to the common electrode.
According to a preferred embodiment of the present invention, the materials of the first metal layer and the second metal layer are each a combination material of one or more of aluminum, molybdenum, copper, chromium, tungsten, tantalum, and titanium.
According to a preferred embodiment of the present invention, one ends of the plurality of first data lines are connected together to integrally form a sensing electrode, one ends of the plurality of second data lines are connected together to integrally form a driving electrode, and the sensing electrode and the driving electrode are arranged in parallel to form a sensing capacitor.
According to a preferred embodiment of the present invention, the first data line and the second data line are vertically disposed, and an inductive capacitor is formed at an overlapping position.
According to an object of the present invention, a liquid crystal display panel is provided, which includes the array substrate, a color film substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.
The invention has the beneficial effects that: the invention provides an array substrate and a liquid crystal display panel, wherein one part of data lines and a grid electrode are arranged in the same layer, the other part of data lines and a source/drain electrode layer are arranged in the same layer, the data lines are arranged between the grid electrode layer and the source/drain electrode layer in an alternative wiring mode and are electrically connected through via holes, the thickness of an insulating layer between the data lines and a common electrode layer is increased, the data lines arranged in different layers form induction capacitors, parasitic capacitors between the data lines and the common electrode layer are reduced, the normal display capability of certain special pictures in the liquid crystal display panel is improved, in addition, the insulating layer between the data lines and the common electrode is arranged into an inorganic film, no extra photomask manufacturing process is needed, and the preparation cost of the liquid crystal display panel is reduced.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic view illustrating an array substrate according to an embodiment of the present disclosure;
fig. 2 is a schematic top view of an array substrate according to an embodiment of the present disclosure;
fig. 3 is another schematic distribution diagram of data lines in an array substrate according to an embodiment of the present disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals, and broken lines in the drawings indicate that the elements do not exist in the structures, and only the shapes and positions of the structures are explained.
The invention can solve the technical problem that the parasitic capacitance between the wiring for transmitting data signals to the pixels and the common signal is large and the normal display of some special pictures in the liquid crystal display panel is influenced because a flat layer is omitted in the TFT device in the prior art.
As shown in fig. 1, the present application provides an array substrate 100, wherein a sub-pixel is formed on the array substrate 100, the sub-pixel includes a substrate 101, a light shielding layer 102 disposed on the substrate 101, a buffer layer 103 disposed on the substrate 101 and covering the light shielding layer 102, a polysilicon layer 104 disposed on the buffer layer 103 and corresponding to the top of the light shielding layer 102, a first insulating layer 105 disposed on the polysilicon layer 104, a first metal layer 106 disposed on the first insulating layer 105, a second insulating layer 107 disposed on the first insulating layer 105 and covering the first metal layer 106, a second metal layer 108 disposed on the second insulating layer 107, a third insulating layer 109 disposed on the second insulating layer 107 and covering the second metal layer 108, a common electrode 201 disposed on the third insulating layer 109, a passivation layer 202 disposed on the common electrode 201, and a pixel electrode 203 disposed on the passivation layer 202, wherein the first metal layer 106 includes a gate 1061, a drain, a source, a drain, the second metal layer 108 includes a source 1081, a drain 1082, and a second data line 1083, the first data line 1062 and the second data line 1083 are electrically connected through the via 1063, in this embodiment, a via 1063 is disposed inside the second insulating layer 107, one end of the via 1063 is connected to the drain 1082, and the other end is connected to the first metal layer 106, in the other case, one end of the via 1063 is electrically connected to the source 1081, and the other end is connected to the first metal layer 106, that is, the second data line 1083 is electrically connected to the drain 1082, and the second data line 1083 is electrically connected to the source 1081; alternatively, the second data line 1083 is electrically connected to the source 1081, and the second data line 1083 and the drain 1082 are disposed in an insulated manner.
Specifically, the substrate 101 is usually a glass substrate, but may be a substrate made of other materials, and is not limited herein; forming a light-shielding layer 102 on a substrate 101, wherein the material of the light-shielding layer 102 is a metal, preferably an alloy of one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti); preparing a buffer layer 103 covering the light-shielding layer 102 on the substrate 101, wherein the buffer layer 103 is a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a composite film formed by alternately laminating a silicon oxide film and a silicon nitride film; preparing a polysilicon layer 104 on the buffer layer 103 by a chemical vapor deposition method, wherein the polysilicon layer 104 comprises a semiconductor layer 1041 and a doping layer 1042 positioned on the surface of the semiconductor layer 1041, the semiconductor layer 1041 is deposited on the buffer layer 103 by a magnetron sputtering method, a metal organic chemical vapor deposition method or a pulse laser evaporation method, annealing treatment is performed for about 0.5 hour in a dry air atmosphere at 400 ℃, the semiconductor layer 1041 is etched by a wet etching process or a dry etching process using oxalic acid as an etching solution after the annealing treatment is completed, the whole metal oxide film is patterned to form an island-shaped metal oxide layer after the etching process, and the semiconductor layer 1041 plays a switching role; after the semiconductor layer 1041 is prepared, the doping layer 1042 is formed on the semiconductor layer 1041 by a chemical vapor deposition method, a source doping region and a drain doping region and a channel region located between the source doping region and the drain doping region are arranged at two ends of the doping layer 1042, the doping layer 1042 is doped with nitrogen ions, phosphorus ions and boron ions, electrical characteristics of a channel between a source and a drain are increased, potential barrier and power consumption are reduced, and on-state current of the thin film transistor is improved.
The first insulating layer 105 is formed on the surface of the polysilicon layer 104, the first insulating layer 105 is an inorganic thin film, the material of the inorganic layer is one or more of silicon dioxide, silicon nitride and silicon oxynitride, and the inorganic thin film is relatively thin, so that a separate photomask process is not required, and the cost of the array substrate 100 can be reduced. A first metal layer 106 is deposited on the surface of the first insulating layer 105, the first metal layer 106 is preferably a combination material of one or more of aluminum, molybdenum, copper, chromium, tungsten, tantalum and titanium, and after the first metal layer 106 is patterned, a gate 1061, a scan line 1064 in the same region as the gate, and a first data line 1062 are formed.
Preparing a second insulating layer 107 on the surface of the first insulating layer 105, covering the first metal layer 106 with the second insulating layer 107, then preparing a second metal layer 108 on the second insulating layer 107, and preparing a third insulating layer 109 on the surface of the second insulating layer 107, wherein the preparation method and the selected material of the second insulating layer 107 and the third insulating layer 109 are the same as those of the first insulating layer 105, and according to the same chemical properties of the same material, the third insulating layer 109 can be etched by corrosive liquid, and the second insulating layer 107 can also be etched, so that corresponding via holes 107 can be prepared on the second insulating layer 107, and the first metal layer 106 is conducted with the second metal layer 108, so that the number of photomasks is not increased, and simultaneously, the contact relation can be satisfied. The design changes the thickness of the insulating layer between the first data line 1062 and the common electrode 201 from the third insulating layer 109 to the total thickness of the second insulating layer 105 and the third insulating layer 109, so that the parasitic capacitance effect between two layers of materials is reduced, and the abnormal display risk of special pictures can be reduced or eliminated.
The second metal layer 108 and the first metal layer 106 are prepared by similar methods and materials. The second metal layer 108 includes a source 1081, a drain 1082, and a second data line 1083 in the same area as the drain 1082; the source electrode 1081 is electrically connected to the source doped region through the source contact hole, the drain electrode 1082 is electrically connected to the drain doped region through the drain contact hole, and the pixel electrode 203 is electrically connected to the drain electrode 1082 through the pixel via 2031. The surface of the second insulating layer 107 is further provided with a touch signal line 1084, and the touch signal line 1084 is electrically connected to the common electrode 2011 through the signal via 1091.
In the present application, the first data line 1062 and the second data line 1083 are disposed in two layers, and the first data line 1062 originally close to the common electrode is disposed on the first metal layer 106, and the two are electrically connected to each other through the via 1063, so as to form a double-layer wiring structure, and the thickness of the insulating layer between the first data line 1062 and the common electrode 201 is increased, thereby reducing the parasitic capacitance between the first data line 1062 and the common electrode 201, and improving the display quality of the array substrate.
As shown in fig. 2, in the embodiment of the present application, a schematic top view structure of the array substrate 100 is provided, wherein one ends of a plurality of second data lines 1083 are connected together to form a driving electrode 1085 (shown by a dotted line in the figure), a first data line 1062 is located right below the second data line 1083 (not in the position relationship in fig. 2, fig. 2 only shows the electrical connection relationship between the first data line 1062 and the second data line 1083), one ends of a plurality of first data lines 1062 are connected together to form a sensing electrode (not shown), the shape of the sensing electrode is similar to the shape of the driving electrode 1085, and the sensing electrode is electrically connected to the driving electrode 1085 through a via 1063. In the present embodiment, the sensing electrode and the driving electrode 1085 are disposed in parallel to form a sensing capacitor, wherein the driving electrode 1085 is electrically connected to the drain 1082, the scanning line 1064 is disposed on the front side of the driving electrode 1085, the touch signal line 1084 is disposed on the right side of the driving electrode 1085, and the common electrode 201 (indicated by a dotted line in the figure) is further disposed on the periphery of the scanning line 1064.
As shown in fig. 3, an embodiment of the present application provides another distribution diagram of data lines in an array substrate, where a first data line 1062 includes a first sub data line 10621, a second sub data line 10622, a third sub data line 10623, a fourth sub data line 10624, and a fifth sub data line 10625; the second data line 1083 includes a sixth sub-data line 10831, a seventh sub-data line 10832, an eighth sub-data line 10833, a ninth sub-data line 10834, a tenth sub-data line 10835, and an eleventh sub-data line 10836. Two adjacent sub data lines in the first data line 1062 are electrically connected to each other to form an induction electrode, and two adjacent sub data lines in the second data line 1083 are also electrically connected to each other to form a driving electrode, wherein the sub data lines in the first data line 1062 are electrically connected to the sub data lines in the second data line 1083 through via holes, that is, the induction electrode is electrically connected to the driving electrode. In the present embodiment, the sensing electrode is disposed perpendicular to the driving electrode, and does not actually contact the driving electrode at the overlapping position, and the sensing capacitor is formed at the overlapping position.
According to an object of the present invention, a liquid crystal display panel is further provided, which includes the array substrate, a color film substrate disposed opposite to the array substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate.
The invention has the beneficial effects that: according to the array substrate, one part of data lines and the grid electrode are arranged on the same layer, the other part of data lines and the source/drain electrode layer are arranged on the same layer, the data lines are arranged between the grid electrode layer and the source/drain electrode layer in an alternative wiring mode, the thickness of an insulating layer between the data lines and a common electrode layer is increased through the electric connection of the through holes, the data lines arranged on different layers form induction capacitors, the parasitic capacitance between the data lines and the common electrode layer is reduced, the normal display capability of certain special pictures in the liquid crystal display panel is improved, in addition, the insulating layer between the data lines and the common electrode is arranged into an inorganic film, no extra photomask manufacturing process is needed, and the preparation cost of the liquid crystal display panel is reduced.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. An array substrate is characterized in that a sub-pixel is formed on the array substrate, and the sub-pixel comprises a substrate, a shading layer arranged on the substrate, a buffer layer arranged on the substrate and covering the shading layer, a polycrystalline silicon layer arranged on the buffer layer and corresponding to the shading layer, a first insulating layer arranged on the polycrystalline silicon layer, a first metal layer arranged on the first insulating layer, a second insulating layer arranged on the first insulating layer and covering the first metal layer, a second metal layer arranged on the second insulating layer, a third insulating layer arranged on the second insulating layer and covering the second metal layer, a common electrode arranged on the third insulating layer, a passivation layer arranged on the common electrode, and a pixel electrode arranged on the passivation layer;
the first metal layer comprises a grid electrode, a scanning line and a first data line, the second metal layer comprises a source electrode, a drain electrode and a second data line, and the first data line is electrically connected with the second data line through a through hole.
2. The array substrate of claim 1, wherein the second insulating layer and the third insulating layer are both inorganic films, and the material of the inorganic films is one or more of silicon dioxide, silicon nitride, and silicon oxynitride.
3. The array substrate of claim 2, wherein the via is located in the second insulating layer, and one end of the via is in communication with the source or the drain, and the other end of the via is in communication with the first metal layer.
4. The array substrate of claim 1, wherein the second data line is electrically connected to the drain electrode, and the second data line is insulated from the source electrode; or, the second data line is electrically connected with the source electrode, and the second data and the drain electrode are arranged in an insulating mode.
5. The array substrate of claim 1, wherein the polysilicon layer comprises a semiconductor layer and a doped layer on the surface of the semiconductor layer.
6. The array substrate of claim 1, wherein a touch signal line is further disposed on a surface of the second insulating layer, and the touch signal line is electrically connected to the common electrode.
7. The array substrate of claim 1, wherein the first metal layer and the second metal layer are made of one or more of aluminum, molybdenum, copper, chromium, tungsten, tantalum, and titanium.
8. The array substrate of claim 1, wherein one end of the first data lines is connected to form a sensing electrode, one end of the second data lines is connected to form a driving electrode, and the sensing electrode and the driving electrode are arranged in parallel to form a sensing capacitor.
9. The array substrate of claim 1, wherein the first data line and the second data line are vertically disposed, and an induced capacitor is formed at an overlapping position.
10. A liquid crystal display panel, characterized in that the liquid crystal display panel comprises the array substrate of any one of claims 1 to 9, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color film substrate.
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| CN201911119350.9A CN110908199A (en) | 2019-11-15 | 2019-11-15 | Array substrate and liquid crystal display panel |
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Cited By (5)
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| CN111969029A (en) * | 2020-08-31 | 2020-11-20 | 江苏仕邦柔性电子研究院有限公司 | TFT device structure for OLED display panel |
| CN112068368A (en) * | 2020-09-01 | 2020-12-11 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN114360384A (en) * | 2022-01-13 | 2022-04-15 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN114779543A (en) * | 2022-04-02 | 2022-07-22 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
| WO2023164979A1 (en) * | 2022-03-02 | 2023-09-07 | 武汉华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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