CN110907747A - Power distribution network traveling wave fault sampling processing system - Google Patents
Power distribution network traveling wave fault sampling processing system Download PDFInfo
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- CN110907747A CN110907747A CN201911000605.XA CN201911000605A CN110907747A CN 110907747 A CN110907747 A CN 110907747A CN 201911000605 A CN201911000605 A CN 201911000605A CN 110907747 A CN110907747 A CN 110907747A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
- G01R31/086—Locating faults in cables, transmission lines, or networks according to type of conductors in power transmission or distribution networks, i.e. with interconnected conductors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/088—Aspects of digital computing
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Abstract
The invention discloses a power distribution network traveling wave fault sampling processing system which comprises a voltage transformer, an ADC (analog-to-digital converter) data acquisition module, a time service module and an FPGA (field programmable gate array) sampling processing unit, wherein the voltage transformer is used for monitoring voltage signals of a power distribution line; the FPGA sampling processing unit controls the ADC data acquisition module to sample data, performs low-pass filtering processing on the sampled data, performs power frequency quantity calculation on the low-pass filtered data, and inputs the time signal into ADC sampled value data. The sampling time synchronization control scheme adopted by the sampling processing system is high in synchronization precision, and filtering and power frequency quantity calculation are performed on the sampled data in advance by utilizing the high operation speed of the FPGA, so that the efficiency and the accuracy of subsequent fault analysis processing are greatly improved.
Description
Technical Field
The invention relates to a traveling wave fault analysis technology of a power distribution network power supply line, in particular to a system for sampling and processing a traveling wave fault of a power distribution network.
Background
When traveling wave fault analysis is performed on a power distribution network, a large number of voltage data signals are generally required to be sampled in real time, and sampling processing of data has important influence on accuracy and processing efficiency of subsequent fault data analysis. An FPGA (programmable array device) is a suitable data processing device with a large computation amount, but a relatively simple computation structure. At present, an FPGA is applied to traveling wave fault collection of a power distribution network, however, at present, the FPGA is used more often to simply remove dryness of collected signals, and then, other processors (such as a DSP) are needed to perform complicated calculation, that is, the current FPGA processing does not play a role in simplifying subsequent traveling wave fault analysis processing.
In addition, the currently adopted double-end traveling wave ranging needs synchronous sampling of a plurality of devices to accurately measure the time difference of the traveling wave signal reaching the measuring point of the devices, so that the synchronous control precision of the sampling time of the traveling wave signal is higher, and the current synchronous sampling scheme for the traveling wave fault of the power distribution network has larger promotion space.
Disclosure of Invention
The invention aims to solve the problems and provides a system capable of efficiently sampling traveling wave signals of a power distribution network, so that the effectiveness of sampling data and the processing efficiency of the sampling data are improved.
In order to realize the aim of the invention, the invention provides a power distribution network traveling wave fault sampling processing system which comprises a voltage transformer, an ADC data acquisition module, a time service module and an FPGA sampling processing unit;
the voltage transformer is used for monitoring three-phase voltage signals on a distribution line;
the ADC data acquisition module is used for acquiring voltage signals output by the voltage transformer;
the time service module is used for outputting a time signal;
the ADC data acquisition module and the time service module are electrically connected with the FPGA sampling processing unit, the FPGA sampling processing unit controls the ADC data acquisition module to sample data, the FPGA sampling processing unit performs low-pass filtering processing on the sampled data, performs power frequency quantity calculation on the low-pass filtered data, and injects the time signal into ADC sampled data.
Preferably, the FPGA sampling processing unit includes:
the synchronous sampling module is used for controlling the ADC to perform synchronous sampling;
the time decoding module is used for decoding the time information output by the time service module to obtain time information; the absolute time scale is added into ADC sampling value data;
the FIR low-pass filtering module is used for carrying out low-pass filtering processing on the sampling data;
the Fourier transform module calculates power frequency quantity by using the data subjected to the FIR low-pass filtering;
the data formatting module is used for storing the sampling data, the data after FIR low-pass filtering, the power frequency quantity data and the time data into an FIFO (first in first out) of the uPP controller according to a certain format;
uPP controller, which implements uPP interface protocol, transfers data in FIFO to external processing device through uPP interface.
Preferably, the ADC data acquisition module includes 3 ADC analog-to-digital converters, and is configured to perform synchronous data acquisition on the three-phase voltage signals monitored by the voltage transformer.
Preferably, the data formatting module writes the data into FIFOs, each data structure is fixed in length and comprises 500 sampling points and FIR low-pass filtered data, the fourier filtered computation result, the absolute time scale comprises the time decoding result and the internal time counter value, and each sampled data packet comprises the absolute time scale of the first sampling point in the data packet.
Further, a dual clock FIFO is used to connect the data formatting module and the uPP interface, the data formatting module serves as a write end of the FIFO, the uPP interface serves as a read end of the FIFO, and the data formatting module and the uPP interface can be independently controlled by using different clocks.
Preferably, the ADC data acquisition module is configured to use an OPA2604 chip as a front-end operational amplifier to receive the voltage signal output by the voltage transformer, and is connected to a signal output terminal of the OPA2604 chip through a THS1408 chip of TI corporation, and a signal output terminal of the THS1408 chip is connected to the FPGA sampling processing unit.
Preferably, the time service module is configured as a GPS/beidou satellite time service module, and the absolute time scale is obtained through a 1PPS second pulse output by a satellite receiving module of the GPS/beidou satellite time service module and a NMEA-0183 standard protocol.
Preferably, the time decoding module is configured to run a decoding program to perform decoding using the NIOS II soft core.
Preferably, the cut-off frequency set by the FIR low-pass filtering module is 500 Hz.
Preferably, the sampling processing system adopts a PT power supply winding to supply power, and is also provided with a standby power supply, so that after a fault occurs, the sampling processing system is switched to the standby power supply to supply power.
Compared with the existing traveling wave fault sampling scheme, the invention has the beneficial effects that: the FPGA is used as a multi-path sampling controller, a GPS time scale controller, a data cache and a digital filtering processor, so that higher operation speed and lower resource consumption can be realized, and the high-efficiency processing of the sampled data is realized. Furthermore, the adopted sampling time synchronization control scheme has higher synchronization precision. The high operation speed of the FPGA is utilized to carry out filtering and power frequency quantity calculation on the sampled data in advance, so that the efficiency and the accuracy of subsequent fault analysis and processing are greatly improved.
Drawings
Fig. 1 is a block diagram of a power distribution network traveling wave fault sampling processing system according to an embodiment of the present invention.
Detailed Description
The following describes a traveling wave fault collection and processing system of a power distribution network in detail with reference to the accompanying drawings and specific embodiments, and it should be noted that the embodiments of the present invention are not limited to the specific embodiments below.
The system comprises a voltage transformer, an ADC data acquisition module, a time service module and an FPGA sampling processing unit;
the voltage transformer is used for monitoring three-phase voltage signals on a distribution line;
the ADC data acquisition module is used for acquiring voltage signals output by the voltage transformer;
the time service module is used for outputting a time signal;
the ADC data acquisition module and the time service module are electrically connected with the FPGA sampling processing unit, the FPGA sampling processing unit controls the ADC data acquisition module to sample data, the FPGA sampling processing unit performs low-pass filtering processing on the sampled data, performs power frequency quantity calculation on the low-pass filtered data, and injects the time signal into ADC sampled data.
It should be noted that the above sampling processing system provided may provide a front-end signal acquisition process for fault location analysis of the power distribution network by a traveling wave method. By the scheme, synchronous sampling of three-phase voltage signals of the distribution line can be achieved, low-pass filtering processing is carried out on the sampled data through the FPGA sampling processing unit, power frequency quantity calculation is carried out on the low-pass filtered data, and whether fault happens or not is judged efficiently and quickly through the power frequency quantity data during subsequent fault location analysis, so that follow-up judgment on whether fault happens or not is not required to carry out large-scale calculation, and the processing capacity of the sampled data is improved (under normal conditions, when traveling wave fault analysis is carried out on the power distribution network, the collected data which need to be monitored in real time is large in data calculation quantity), and the fault detection sensitivity is improved. As an optional application, the power distribution network traveling wave fault sampling processing system of this embodiment may be used in cooperation with a DSP processor, and send sampling data processed by the FPGA sampling processing unit of this sampling processing system to the DSP processor for subsequent fault location analysis processing.
As an alternative embodiment, the ADC data acquisition module includes 3 ADC analog-to-digital converters for performing synchronous data acquisition on the three-phase voltage signals monitored by the voltage transformer.
Specifically, the distance between the poles of the 10kV distribution line is generally about 60 meters, and the transmission speed of the traveling wave in the line is 0.3 m/ns at most, so that the hardware sampling interval can be set to be not less than 200ns, namely the sampling rate is not less than 5 MSPS. In view of this, in this embodiment, the ADC data acquisition module is configured to use the OPA2604 chip as a front-end operational amplifier to receive the voltage signal output by the voltage transformer, and is connected to the signal output terminal of the OPA2604 chip through the THS1408 chip of the TI company, and the signal output terminal of the THS1408 chip is connected to the FPGA sampling processing unit. THS1408 has 14-bit resolution, the highest sampling rate of 8MSPS, meets the design requirement of more than or equal to 5MSPS of system design requirement, the 14-bit resolution can better identify weak voltage traveling wave signals, a CMOS (complementary metal oxide semiconductor) process is adopted, a single 3.3V power supply is used, an external reference power supply is not needed, the power supply can be directly accessed to an I/O (input/output) port of an FPGA (field programmable gate array) sampling processing unit, two analog input modes of single-ended and differential are supported, and an OPA2604 operational amplifier chip is used at the front end and can be matched with different voltage transformer output voltage signals.
As a preferred embodiment, the FPGA sampling processing unit includes:
the synchronous sampling module is used for controlling the ADC to perform synchronous sampling;
the time decoding module is used for decoding the time information output by the time service module to obtain time information; the absolute time scale is added into ADC sampling value data;
the FIR low-pass filtering module is used for carrying out low-pass filtering processing on the sampling data;
the Fourier transform module calculates power frequency quantity by using the data subjected to the FIR low-pass filtering;
the data formatting module is used for storing the sampling data, the data after FIR low-pass filtering, the power frequency quantity data and the time data into an FIFO (first in first out) of the uPP controller according to a certain format;
uPP controller, which implements uPP interface protocol, transfers data in FIFO to external processing device through uPP interface.
In the above scheme, after the sampling values are formatted, the ADC sampling data, the FIR low-pass filtering result, the fourier transform result, and the time data are formatted into a sampling data packet and stored in the FIFO of the uPP controller. As the sampling data packet has the fundamental wave effective value calculated by FIR filtering and Fourier transform, the calculation is not needed to be carried out again in the follow-up process, and whether the fault event happens can be judged by directly using the calculation result provided by the FPGA sampling processing unit. The sampling data comprises original full-frequency voltage signals, and playback and reanalysis of fault signals are facilitated.
In general, in some traveling wave ranging methods (such as the double-ended traveling wave ranging method), synchronous sampling is usually required for multiple devices to accurately measure the time difference of the traveling wave signal reaching the measurement point of the devices. The time service module in the sampling processing system is configured as a GPS/Beidou satellite time service module, and the absolute time scale is obtained through the 1PPS second pulse output by the satellite receiving module of the GPS/Beidou satellite time service module and the NMEA-0183 standard protocol.
Preferably, the data formatting module writes data into an FIFO, each data structure has a fixed length and comprises 500 sampling points and FIR low-pass filtering data, the Fourier filtering calculation result and the absolute time scale comprise a time decoding result of a GPS/Beidou satellite time service module and an internal time counter value, the internal time counter is provided with a clock source by a constant temperature crystal oscillator and used for counting time below seconds, the counter is cleared by a 1PPS signal and can provide time precision of up to 10ns, and each sampling data packet comprises the absolute time scale of the first sampling point in the data packet.
Preferably, a dual clock FIFO is used to connect the data formatting module and the uPP interface, the data formatting module serves as the write side of the FIFO, the uPP interface serves as the read side of the FIFO, and the data formatting module and the uPP interface can be independently controlled using different clocks.
Preferably, since the message of the NMEA-0183 protocol is a variable-length message, it is not beneficial to use hardware for direct decoding. And setting the time decoding module to use an NIOS II soft core and run a decoding program for decoding.
Preferably, the FIR low-pass filtering module sets a cut-off frequency of 500Hz, which is helpful for removing interference signals such as noise.
Preferably, the sampling processing system adopts a PT power supply winding to supply power, and is also provided with a standby power supply, so that after a fault occurs, the sampling processing system is switched to the standby power supply to supply power.
Claims (10)
1. A power distribution network traveling wave fault sampling processing system is characterized by comprising a voltage transformer, an ADC data acquisition module, a time service module and an FPGA sampling processing unit;
the voltage transformer is used for monitoring three-phase voltage signals on a distribution line;
the ADC data acquisition module is used for acquiring voltage signals output by the voltage transformer;
the time service module is used for outputting a time signal;
the ADC data acquisition module and the time service module are electrically connected with the FPGA sampling processing unit, the FPGA sampling processing unit controls the ADC data acquisition module to sample data, the FPGA sampling processing unit performs low-pass filtering processing on the sampled data, performs power frequency quantity calculation on the low-pass filtered data, and injects the time signal into ADC sampled data.
2. The system for sampling and processing traveling wave faults of the power distribution network according to claim 1, wherein the FPGA sampling and processing unit comprises:
the synchronous sampling module is used for controlling the ADC to perform synchronous sampling;
the time decoding module is used for decoding the time information output by the time service module to obtain time information; the absolute time scale is added into ADC sampling value data;
the FIR low-pass filtering module is used for carrying out low-pass filtering processing on the sampling data;
the Fourier transform module calculates power frequency quantity by using the data subjected to the FIR low-pass filtering;
the data formatting module is used for storing the sampling data, the data after FIR low-pass filtering, the power frequency quantity data and the time data into an FIFO (first in first out) of the uPP controller according to a certain format;
uPP controller, which implements uPP interface protocol, transfers data in FIFO to external processing device through uPP interface.
3. The traveling wave fault sampling processing system for power distribution network of claim 1, wherein the ADC data acquisition module comprises 3 ADC analog-to-digital converters for performing synchronous data acquisition on the three-phase voltage signals monitored by the voltage transformer.
4. The system of claim 2, wherein the data formatting module writes data into FIFOs, each data structure is of a fixed length and comprises 500 sampling points and FIR low-pass filtered data, the fourier filtered computation results, the absolute time scale comprise the time decoding results and the internal time counter values, and each sampled data packet comprises the absolute time scale of the first sampling point in the data packet.
5. The system for sampling and processing traveling wave faults of the power distribution network according to claim 2 or 4, wherein a double-clock FIFO is used for connecting the data formatting module and the uPP interface, the data formatting module is used as a write end of the FIFO, the uPP interface is used as a read end of the FIFO, and the data formatting module and the uPP interface can be independently controlled by using different clocks.
6. The system for sampling and processing the traveling wave fault of the power distribution network according to claim 2, wherein the ADC data acquisition module is configured to receive the voltage signal output by the voltage transformer by using an OPA2604 chip as a front-end operational amplifier, and is connected to a signal output end of the OPA2604 chip through a THS1408 chip, and a signal output end of the THS1408 chip is connected to the FPGA sampling and processing unit.
7. The system for sampling and processing the traveling wave fault of the power distribution network according to claim 1, wherein the time service module is configured as a GPS/Beidou satellite time service module, and an absolute time scale is obtained through a 1PPS (pulse per second) pulse output by a satellite receiving module of the GPS/Beidou satellite time service module and a NMEA-0183 standard protocol.
8. The system for sampling and processing traveling wave faults of the power distribution network according to claim 7, wherein the time decoding module is configured to run a decoding program for decoding by using a NIOSII soft core.
9. The system for sampling and processing traveling wave faults of the power distribution network according to claim 2, wherein the cut-off frequency set by the FIR low-pass filtering module is 500 Hz.
10. The system for sampling and processing the traveling wave fault of the power distribution network according to claim 1, wherein the sampling and processing system is powered by a PT power supply winding and is also provided with a standby power supply, and after the fault occurs, the sampling and processing system is switched to the standby power supply to supply power.
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Application publication date: 20200324 |