CN113917277A - High-speed sampling circuit suitable for transmission line fault early warning diagnosis terminal - Google Patents

High-speed sampling circuit suitable for transmission line fault early warning diagnosis terminal Download PDF

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Publication number
CN113917277A
CN113917277A CN202110995137.5A CN202110995137A CN113917277A CN 113917277 A CN113917277 A CN 113917277A CN 202110995137 A CN202110995137 A CN 202110995137A CN 113917277 A CN113917277 A CN 113917277A
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China
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current
sampling
differential
hidden danger
traveling wave
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Inventor
邓庆
周华良
夏雨
马凡凡
丁玮
姚吉文
王海全
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Nari Technology Co Ltd
NARI Nanjing Control System Co Ltd
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Nari Technology Co Ltd
NARI Nanjing Control System Co Ltd
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Priority to CN202110995137.5A priority Critical patent/CN113917277A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/081—Locating faults in cables, transmission lines, or networks according to type of conductors
    • G01R31/086—Locating faults in cables, transmission lines, or networks according to type of conductors in power transmission or distribution networks, i.e. with interconnected conductors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/18—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
    • G01R15/181—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers using coils without a magnetic core, e.g. Rogowski coils
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/08—Locating faults in cables, transmission lines, or networks
    • G01R31/088—Aspects of digital computing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults

Abstract

The invention discloses a high-speed sampling circuit suitable for a power transmission line fault early warning diagnosis terminal, wherein two sets of Rogowski coils are provided with independent post-stage signal processing and collecting circuits, one circuit is a current sampling unit for realizing milliampere to ten ampere levels for a hidden danger current sampling unit, and the sampling unit comprises a hidden danger current Rogowski coil, a hidden danger current integrating circuit and a hidden danger current differential sampling circuit; one path is a traveling wave current sampling unit to realize ten-ampere-level to kilo-ampere-level current sampling, and the sampling unit comprises a traveling wave current Rogowski coil, a traveling wave current integrating circuit and a traveling wave current differential sampling circuit. The two sampling units of the invention realize the measurement of high-precision and hundred-megawatt sampling rate of the current covering a wide amplitude range from milliampere level to kiloampere level and a wide frequency band range from ten hertz level to megahertz level.

Description

High-speed sampling circuit suitable for transmission line fault early warning diagnosis terminal
Technical Field
The invention belongs to the technical field of measurement and control of an electric power system, particularly belongs to the field of monitoring of the state of primary equipment of the electric power system, and particularly relates to a high-speed sampling circuit suitable for a fault early warning diagnosis terminal of an electric transmission line.
Background
Transient currents in the grid contain a large amount of fault current information covering an extremely wide range of amplitudes and frequency bands. For example, in the field of state monitoring of high-voltage transmission lines, when breakdown faults do not occur due to hidden trouble of a line, such as bird droppings, barrier flashover and the like, high-frequency small-signal hidden trouble discharge current of dozens of milliamperes and megahertz exists on the line. At the moment, the workers need to position the hidden danger, so that further great damage to the power transmission line is avoided; when a breakdown short circuit fault occurs in a line, for example, a foreign matter is lapped on the line, and wind deflection short circuit occurs in an interphase line, the amplitude range of the fault current is as large as thousands of amperes, and the frequency band range covers dozens of hertz to thousands of hertz. At the moment, the working personnel need to position the fault point and quickly remove the fault to recover power supply. The two special application scenes put high requirements on performance indexes of the monitoring equipment, such as the measurement amplitude range, the frequency bandwidth, the sampling rate, the measurement accuracy and the like; the wide-band high-speed high-precision detection device has a proper amplitude measurement range from milliampere to kiloampere, can cover a wide-band high-speed high-precision detection device of a high-frequency signal from ten hertz to megahertz, can reproduce hidden dangers and fault current waveforms completely, can reproduce a current change process in fault development, and has important significance for hidden danger prevention and fault diagnosis of a power transmission line. The method is not only beneficial to timely repairing of the fault line, but also can greatly save manpower and material resources for line inspection, ensure the safe and stable operation of the whole power grid, and have great social and economic benefits.
A plurality of terminal devices are installed on a wire of the power transmission line along the line, and potential hazard current and fault current signals are collected and detected by using a biro coil, a double integral conditioning circuit, a double hundred million differential sampling circuit and an SoC chip with an FPGA core.
A conventional electromagnetic CT is generally used as a current sensor for sampling current in some application fields such as measurement and control of a power system. However, the conventional electromagnetic CT has a problem of large current saturation, and is not favorable for detecting high-frequency wide-width current due to poor frequency characteristics.
In the field of monitoring of the state of a transmission line conductor, a Rogowski coil is used for detecting a large-current short-circuit fault signal in part of products, but an effective method for detecting milliampere-level high-frequency hidden danger current is not available.
In addition, the traditional power system measurement control device mostly adopts an ADC with a low sampling rate and a low cut-off frequency as a core analog-to-digital conversion device of the acquisition system, and the sampling method cannot acquire and restore high-frequency hidden dangers and fault current signals in real time and at high precision, and cannot provide powerful support for subsequent fault type identification, diagnosis and positioning.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a high-speed sampling circuit suitable for a power transmission line fault early warning diagnosis terminal, and solves the problem that the current signals with wide amplitude and wide frequency band in a power transmission line cannot be acquired, measured and recorded at high speed.
In order to solve the technical problems, the invention provides a high-speed sampling circuit suitable for a power transmission line fault early warning diagnosis terminal, which comprises a hidden danger current sampling unit, a traveling wave current sampling unit and a control unit;
the hidden danger current sampling unit comprises a hidden danger current Rogowski coil, a hidden danger current integrating circuit and a hidden danger current differential sampling circuit; the hidden danger current Rogowski coil acquires a hidden danger current signal, converts the hidden danger current signal into a voltage signal, and inputs the voltage signal into a hidden danger current integrating circuit, the hidden danger current integrating circuit integrates, filters and amplifies the voltage signal and inputs the voltage signal into a hidden danger current differential sampling circuit, and the hidden danger current differential sampling circuit converts the input signal into a hidden danger current differential signal and outputs the hidden danger current differential signal;
the traveling wave current sampling unit comprises a traveling wave current Rogowski coil, a traveling wave current integrating circuit and a traveling wave current differential sampling circuit; the traveling wave current Rogowski coil acquires a traveling wave current signal, converts the traveling wave current signal into a voltage signal, and then inputs the voltage signal into the traveling wave current integrating circuit, the traveling wave current integrating circuit performs integration, filtering and amplification on the voltage signal, and then inputs the voltage signal into the hidden danger current differential sampling circuit, and the traveling wave current differential sampling circuit converts the input signal into a traveling wave current differential signal and outputs the traveling wave current differential signal;
the control unit respectively collects the hidden danger current differential signals and the traveling wave current differential signals output by the hidden danger current sampling unit and the traveling wave current sampling unit to obtain the hidden danger current and the traveling wave current sampling values; and when the sampling values of the hidden trouble current and the traveling wave current exceed the respective current waveform recording threshold values, the current waveform storage and recording are triggered.
Optionally, the hidden danger current integral conditioning circuit and the traveling wave current integral conditioning circuit have the same structure.
Optionally, the hidden danger current integrating and conditioning circuit comprises an integrating circuit, a filter circuit and an amplifying circuit;
the integrating circuit comprises a first high-bandwidth operational amplifier and an external sampling resistor RsDamping resistance R1First capacitor C1Feedback resistance RFA first balance resistor RP1(ii) a External sampling resistor RsThe positive and negative output ends of the Rogowski coil are connected in parallel, and the negative output end of the Rogowski coil is grounded; the positive input end of the first high-bandwidth operational amplifier is connected with a damping resistor R1The positive output end of the Rogowski coil is connected with the rear end of the first high-bandwidth operational amplifier, and the reverse input end of the first high-bandwidth operational amplifier is connected with a first balance resistor RP1Then grounding; a first capacitor C1And a feedback resistor RFThe output end and the positive input end of the first high-bandwidth operational amplifier are connected in parallel; the output end of the first high-bandwidth operational amplifier is connected with the filter circuit；
The filter circuit comprises a second resistor R2And a second capacitor C2(ii) a The output end of the first high-bandwidth operational amplifier is connected with a second capacitor C2And a second resistor R2Back ground, second capacitor C2And a second resistor R2The electric connection point is used as the output end of the filter circuit and is connected with the amplifying circuit;
the amplifying circuit comprises a second high-bandwidth operational amplifier and a second balance resistor RP2And a third resistor R3(ii) a The output end of the filter circuit is connected with the forward input end of the second high-bandwidth operational amplifier, and the reverse input end of the second high-bandwidth operational amplifier is connected with the second balance resistor RP2The rear end is grounded, and the output end of the first high-bandwidth operational amplifier is connected with a third resistor R3And the output end of the first high-bandwidth operational amplifier outputs voltage as the output of the integral conditioning circuit.
Optionally, the hidden danger current differential sampling circuit includes: an adjustable gain amplifier U1, a first differential amplifier U2 and a first high-speed ADC chip U3;
the output Vo1 of the hidden danger current integral conditioning circuit is connected with the positive input end of the adjustable gain amplifier U1, and the negative input end of the adjustable gain amplifier U1 is grounded; the output end of the adjustable gain amplifier U1 is connected with the positive input end of a first differential amplifier U2, and the negative input end of the first differential amplifier U2 is grounded; the first differential amplifier U2 outputs a differential voltage signal Vo3 connected to the analog differential signal input port of the first high speed ADC chip U3; the first high-speed ADC chip U3 converts the Vo3 differential voltage signal into a differential digital signal, and sends the differential digital signal to the control unit;
the control unit is connected with an adjustable gain amplifier U1 to control the amplification gain of the adjustable gain amplifier U1.
Optionally, the traveling wave current differential sampling circuit includes: a second differential amplifier U4, a second high speed ADC chip U5;
the output Vo1 of the traveling wave current integral conditioning circuit is connected with the positive input end of a second differential amplifier U4, and the negative input end of the second differential amplifier U4 is grounded; the second differential amplifier U4 outputs a differential voltage signal Vo2 connected to the analog differential signal input port of the second high-speed ADC chip U5; the second high-speed ADC chip U5 converts the differential voltage signal Vo2 into a differential digital signal, which is sent to the control unit.
Optionally, the frequency of analog-to-digital conversion of the first high-speed ADC chip U3 and the second high-speed ADC chip U5 is greater than 2 times the highest frequency of the differential voltage signal.
Optionally, the control unit controls the first high-speed ADC chip U3 and the second high-speed ADC chip U5 to sample synchronously.
Optionally, the control unit includes two independent hidden danger current ring buffers and a traveling wave current buffer, the hidden danger current ring buffers are used for storing hidden danger current sampling values and hidden danger current recording data, and the traveling wave current ring buffers are used for storing traveling wave current sampling values and traveling wave current recording data.
Optionally, the operation of the control unit on the ring buffer area is divided into a sampling function module and a wave recording function module;
when the transmission line runs without faults, the sampling function module works, and the sampling function module stores the sampling data in the annular buffer area;
when the transmission line runs with a fault, the wave recording function module is started, and records the current waveform and stores the current waveform in the annular buffer area.
Optionally, the control unit acquires the current time as the starting time of the recording waveform when the current records the wave, and records the time of the fault point in a 'fault timestamp' register;
according to the set time period T = Ta + Tb before and after the fault time, T is the wave recording time length, Ta is the time length after starting, Tb is the time length before starting, a data pointer at Tb before the starting wave recording point is stored in a fault data reading pointer register, and a trigger signal is output after the Ta time is delayed;
after receiving the trigger signal, reading out the sampling data from the dual-port RAM according to the address pointed in the fault data reading pointer for fault current recording.
Compared with the prior art, the invention has the following beneficial effects:
1) the flexible double Rogowski coil is used for measuring currents in different amplitude ranges, and has the advantages of wide measurement amplitude range, wide response frequency band, good linearity, no magnetic saturation phenomenon, small influence of the position of a measured conductor on sampling precision and the like;
2) a double-integral signal conditioning circuit is used for conditioning and amplifying signals collected by Rogowski coils of monitoring objects with different current amplitudes, and the sampling resolution and precision of a rear-stage ADC in a full measurement range are guaranteed. The hidden danger current sampling unit realizes current sampling from milliampere level to ten ampere level, and the traveling wave current sampling unit realizes current sampling from ten ampere level to kiloampere level;
3) by using double-hundred-million differential high-speed ADC sampling, high-frequency current small signals sent by a preceding stage integral conditioning circuit can be respectively collected in real time, high-frequency hidden danger current and fault current signals are restored at high precision, and powerful support is provided for subsequent fault type identification, diagnosis and positioning;
4) the FPGA technology is used for concurrent calculation, the processing performance is high, the fault-tolerant function and the anti-interference performance are achieved, the double sets of sampling units are controlled, and the acquisition and storage of the whole system on the input current signal with wide amplitude, wide frequency band, high precision and high speed are achieved.
Drawings
FIG. 1 is a block diagram of a high-speed sampling circuit according to the present invention;
FIG. 2 is a Rogowski coil integral conditioning circuit;
FIG. 3 is a differential sampling circuit for potential current signals;
FIG. 4 is a traveling wave current signal differential sampling circuit;
fig. 5 is a schematic diagram of the sampling and start-up control (single channel).
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Because the current variation range in the fields of power system measurement and control and the like is large, the frequency band is wide, and for accurately acquiring the current amplitude, a sensor with high frequency transmission capability and transient response speed is adopted, so that the distortion of a current signal is avoided. The differential characteristic of the Rogowski coil has excellent response capability to the high-frequency sudden current of the power transmission line, so the Rogowski coil is adopted as the current sensor. And Rogowski coils with different amplitude-frequency characteristics are selected according to the amplitude-frequency characteristics of different monitored objects, and the two sets of Rogowski coils are provided with independent post-stage signal processing and acquisition circuits.
The invention relates to a high-speed sampling circuit suitable for a power transmission line fault early warning diagnosis terminal, which comprises a biro coil, a double integral conditioning circuit, a double differential sampling circuit and an FPGA (field programmable gate array) core (control unit) in an SoC (system on chip), as shown in figure 1.
The double Rogowski coil pointer adopts flexible non-magnetic framework Rogowski coils with different sensitivities for different monitored objects, and comprises an external metal shielding shell and a Rogowski coil. The Rogowski coil is embedded in a metal shielding shell, a non-magnetic framework is adopted, and an annular opening is formed in the shielding shell close to the lead. The structure is light and small, the installation is convenient, the conductor of the power transmission line is not damaged, the direct electric connection with a tested loop is not realized, the influence on primary side current signals is small, the ferromagnetic material is not contained, the saturation phenomenon cannot occur, and the linearity is good. Because the amplitude ranges of the measured objects are different, the flexible Rogowski coil is divided into a hidden danger current Rogowski coil and a traveling wave current Rogowski coil. The hidden danger current Rogowski coil mainly collects a milliampere-level to ten-ampere-level small current signal, and the traveling wave current Rogowski coil mainly collects an ampere-level to kiloampere-level large current signal. The sampling double-flexible Rogowski coil realizes the signal sensing function in a wide amplitude range from milliampere to kiloampere and a wide frequency band range from ten hertz to megahertz.
The double-integral conditioning circuit comprises a hidden danger current integral conditioning circuit and a traveling wave current integral conditioning circuit. The hidden danger current integral conditioning circuit and the traveling wave current integral conditioning circuit have the same structure, and each integral conditioning circuit comprises an integral circuit, a filter circuit and an amplifying circuit.
The double-differential sampling circuit comprises a hidden danger current differential sampling circuit and a fault traveling wave current differential sampling circuit. The hidden danger current differential sampling circuit comprises an adjustable gain amplifier, a differential amplifier and a hundred-million sampling high-speed ADC. The traveling wave current differential sampling circuit comprises a differential amplifier and a hundred-million sampling high-speed ADC.
The FPGA core control unit comprises gain amplification logic of an adjustable gain amplifier in a potential current differential sampling circuit and logic of a potential current and a function of triggering current waveform storage and recording when a traveling wave current sampling value exceeds a respective current waveform recording threshold value, wherein the logic is realized by an FPGA core in an SoC.
That is to say, as shown in fig. 1, one path of the high-speed sampling circuit is a hidden danger current sampling unit to realize a current sampling unit of milliampere level to ten ampere level, and the sampling unit comprises a hidden danger current rogowski coil, a hidden danger current integrating circuit and a hidden danger current differential sampling circuit which are connected in sequence; one path is a traveling wave current sampling unit to realize ten-ampere-level to kilo-ampere-level current sampling, and the sampling unit comprises a traveling wave current Rogowski coil, a traveling wave current integrating circuit and a traveling wave current differential sampling circuit which are sequentially connected.
The working principle of the high-speed sampling circuit is as follows:
the biro coil realizes the function of converting the hidden danger current and the traveling wave current into a secondary voltage small signal after differentiating the primary current signal; the voltage small signals respectively complete the functions of integral reduction, filtering and primary amplification of the signals through respective integral conditioning circuits; in order to facilitate the high-precision acquisition of signals, the signals subjected to integral conditioning are processed by the differential sampling circuit again to complete the secondary amplification of the signals and the conversion of single-ended signals into differential signals, and the high-speed ADC is used for realizing the analog-to-digital conversion; finally, the FPGA checks the data after the analog-to-digital conversion, and the data are distinguished and stored.
Aiming at different primary lead measuring current amplitude ranges, the invention respectively adopts hidden danger current Rogowski coils to detect current signals from milliampere level to ten ampere level, and converts the primary current signals in the amplitude range into secondary voltage small signals; and detecting a current signal from ten amperes to kiloamperes by adopting a traveling wave current Rogowski coil, and converting a primary current signal in the amplitude range into a secondary voltage small signal. Compared with a traveling wave current Rogowski coil, the hidden danger current Rogowski coil has the advantages that the amplitude range of the measured current is narrower, and the sensitivity and the resolution are higher, so that the number of winding turns of the hidden danger current Rogowski coil is more than that of the traveling wave current Rogowski coil.
Aiming at signals acquired by different Rogowski coils at the front stage, the hidden danger current integral conditioning circuit and the traveling wave current integral conditioning circuit respectively complete the integral reduction, filtering and primary amplification functions of the signals. The method comprises the steps of firstly integrating a small differential signal from a Rogowski coil through an integrating circuit, restoring original phase-frequency characteristics of a waveform, secondly eliminating a low-frequency signal in the integrated signal through a rear-stage high-pass filtering circuit, and finally primarily amplifying the filtered signal through a primary amplifying circuit. The integrating circuit is shown in figure 2: the hidden danger current integral conditioning circuit and the traveling wave current integral conditioning circuit are the same and comprise an integral circuit, a filter circuit and an amplifying circuit;
the integrating circuit comprises a first high-bandwidth operational amplifier and an external sampling resistor RsDamping resistance R1First capacitor C1Feedback resistance RFA first balance resistor RP1(ii) a External sampling resistor RsThe positive and negative output ends of the Rogowski coil are connected in parallel, and the negative output end of the Rogowski coil is grounded; the positive input end of the first high-bandwidth operational amplifier is connected with a damping resistor R1The positive output end of the Rogowski coil is connected with the rear end of the first high-bandwidth operational amplifier, and the reverse input end of the first high-bandwidth operational amplifier is connected with a first balance resistor RP1Then grounding; a first capacitor C1And a feedback resistor RFThe output end and the positive input end of the first high-bandwidth operational amplifier are connected in parallel; the output end of the first high-bandwidth operational amplifier is connected with the filter circuit;
the filter circuit comprises a second resistor R2And a second capacitor C2(ii) a A second resistor R2And a second capacitor C2Forming a first-order high-pass filter circuit. The output end of the first high-bandwidth operational amplifier is connected with a second capacitor C2And a second resistor R2Back ground, second capacitor C2And a second resistor R2The electric connection point is used as the output end of the filter circuit and is connected with the amplifying circuit;
the amplifying circuit comprises a second high-bandwidth operational amplifier and a second balance resistor RP2And a third resistor R3(ii) a FilteringThe output end of the circuit is connected with the positive input end of the second high-bandwidth operational amplifier, and the negative input end of the second high-bandwidth operational amplifier is connected with the second balance resistor RP2The rear end is grounded, and the output end of the first high-bandwidth operational amplifier is connected with a third resistor R3And the output end of the first high-bandwidth operational amplifier outputs voltage as the output of the integral conditioning circuit.
In the integral conditioning circuit, RsExternal sampling resistor, R, for Rogowski coil1Is a damping resistance, C1Is an integrating circuit capacitor, a feedback resistor RFThe slope output eliminating circuit is used for eliminating non-ideal factors such as offset current, bias current and temperature drift of the operational amplifier, and the slope output superimposed on a useful signal is generated at the output end through continuous accumulation of the integrating capacitor, and the signal-to-noise ratio of the output signal of the Rogowski coil is effectively improved. To eliminate the effect of the DC offset of the operational amplifier, the resistor RP is balanced1Value is RP1=R1||RF. After the integration element, an additional R2And C2The formed first-order high-pass filter circuit with the cut-off frequency of 10Hz reduces the gain of low-frequency signals and can effectively reduce the interference of power frequency quantity of a power system. An in-phase amplifying circuit is designed behind the filter circuit, and a high-bandwidth operational amplifier is adopted to amplify the signals.
Meanwhile, theories and experiments prove that the change range of the amplitude values of the hidden danger current and the fault current on the power transmission line is very large, from dozens of milliamperes to thousands of amperes, so that a conditioning circuit at the front end of the ADC is required to have a large input dynamic range. Therefore, in order to improve sampling accuracy and anti-interference capability, signals from the rogowski coil integrating circuit need to be accessed to a high-speed ADC chip after being conditioned by differential signals. After the hidden danger current integrating circuit and the fault traveling wave current integrating circuit restore the original waveform, the input signal is conditioned through respective independent differential sampling circuits, and the processing functions of signal filtering, secondary amplification, single-end differential conversion and the like are realized. The differential signal sampling circuit is divided into a hidden danger current differential sampling circuit (shown in figure 3) and a fault traveling wave current differential sampling circuit (shown in figure 4).
As shown in fig. 3, the hidden danger current differential sampling circuit includes an adjustable gain amplifier U1, a first differential amplifier U2, and a first high-speed ADC chip U3; the output Vo1 of the hidden danger current integral conditioning circuit is connected with the positive input end of the adjustable gain amplifier U1, and the negative input end of the adjustable gain amplifier U1 is grounded; the output end of the adjustable gain amplifier U1 is connected with the positive input end of a first differential amplifier U2, and the negative input end of the first differential amplifier U2 is grounded; the first differential amplifier U2 outputs a differential voltage signal Vo3 connected to the analog differential signal input port of the first high speed ADC chip U3; the first high-speed ADC chip U3 realizes analog-to-digital conversion, converts the Vo3 differential voltage signal into a differential digital signal, and sends the differential digital signal to an FPGA core of the SoC chip for processing.
Because the amplitude range of the hidden danger current is generally dozens of milliamperes to several amperes, after the hidden danger current is differentiated by the Rogowski coil, the input signal is several millivolts, and the input signal needs to be amplified and conditioned by high magnification. Therefore, in the hidden danger current differential sampling circuit shown in fig. 3, the integrated hidden danger current signal needs to be amplified by the U1 operational amplifier. The U1 operational amplifier is a high-bandwidth operational amplifier with digital interface adjustable gain, and is controlled by a later-stage FPGA core, so that 100-time amplification of signals can be realized. The signal is amplified and then driven by a U2 differential operational amplifier driving chip, the sampled signal is converted into a differential signal from a single-ended signal, and then the differential signal is sent to a high-speed ADC conversion chip U3, so that the analog-digital conversion function is realized.
Travelling wave current differential sampling circuit as shown in fig. 4, the travelling wave current differential sampling circuit includes a second differential amplifier U4, a second high-speed ADC chip U5; the output Vo1 of the traveling wave current integral conditioning circuit is connected with the positive input end of a second differential amplifier U4, and the negative input end of the second differential amplifier U4 is grounded; the second differential amplifier U4 outputs a differential voltage signal Vo2 connected to the analog differential signal input port of the second high-speed ADC chip U5; the second high-speed ADC chip U5 realizes analog-to-digital conversion, converts the differential voltage signal Vo2 into a differential digital signal, and sends the differential digital signal to an FPGA core of the SoC chip for processing.
The amplitude range of the traveling wave current is generally dozens of amperes to thousands of amperes, after the traveling wave current is differentiated by the Rogowski coil, the input signal is hundreds of millivolts, and the amplitude range of the signal can be directly captured by the ADC. Therefore, signals of the traveling wave current conditioned by the integrating circuit do not need to be amplified again, and can be directly driven by the U4 differential operational amplifier driving chip, the sampled signals are converted into differential signals from single-ended signals, and then the differential signals are sent to the U5 high-speed ADC conversion chip, and the analog-to-digital conversion function is realized.
Because the frequency range of the hidden danger current frequency and the fault current frequency on the power transmission line is between dozens of hertz and dozens of megahertz, the frequency of ADC conversion must be more than 2 times of the highest frequency of a signal according to the sampling theorem. In order to better maintain the signal waveform, the invention adopts an integrated sampling chip which adopts ADC conversion chips of U3 and U5 to have 14-bit sampling precision, the sampling frequency bandwidth is 220MHz, and the highest sampling rate is 250 MSPS. The input end is a differential sampling holding amplifying circuit, and the output end is a multi-stage differential pipeline structure and is provided with error correction logic. The ADC realizes the function of analog-to-digital conversion, and ensures the accuracy and the real-time performance of data during sampling.
Aiming at the digital signals after the conversion of the preceding stage differential sampling circuit is completed, the FPGA core in the SoC starts different current waveform recording functions in different current amplitude ranges, and finally, the system acquires and stores the input current signals with wide amplitude, wide frequency band, high precision and high speed. The invention selects the SoC chip with the FPGA core and the ARM core as the main control device of the system, the FPGA core controls 2 ADCs to sample synchronously at high speed, the sampled data is cached in an on-chip memory, namely a ring buffer area in real time, the cyclic coverage is realized, and the size of the buffer area is set to be more than 2 times of the data to be recorded. Two independent annular buffer areas of hidden danger current and traveling wave current and a data transmission channel are designed, comprehensive and complete fault waveforms are ensured, and post analysis is facilitated.
The operation of the FPGA for checking the data annular buffer area is divided into a sampling function module and a wave recording function module. When the transmission line runs without faults, the current load of the conducting wire changes relatively slowly, and the instantaneous values of the current are the same in two adjacent cycles, and the change rates of the corresponding phase currents are also the same. At the moment, a sampling function module of the FPGA core works, the sampling function module stores sampling data in an annular buffer area, the data in the buffer area adopts a circular covering mode, a writing pointer points to the beginning of the buffer area every time, and the current time is recorded in a ring-head timestamp register.
When the transmission line runs in a fault, the current load of the wire is suddenly changed, and the amplitude or the first derivative of the current of the wire is suddenly changed. Therefore, the current change rate of the corresponding phase of the previous cycle of the current is multiplied by a certain coefficient to be used as a set threshold value of the recording record of the fault current waveform at the current moment, so that the dynamic tracking of the set threshold value to the input current signal is realized. When the current change of the measured wire exceeds a set value, the FPGA core starts the current recording function module to complete the acquisition and recording of the transient fault current waveform of the sudden change.
The hidden danger current waveform and the traveling wave current fault waveform are recorded by adopting different criteria and starting thresholds. When the current is recorded, the FPGA core acquires the current time from a time-tick and time-keeping module of an ARM core in the SoC as the starting time of a wave recording waveform, records the time of a fault point in a 'fault time stamp' register, and stores a data pointer at Tb before the starting and wave recording point in a 'fault data reading pointer' register according to the set time period T = Ta + Tb before and after the fault time (T is the wave recording time length, Ta is the time length after the starting, and Tb is the time length before the starting) according to a current wave recording function module, and outputs a trigger signal to the ARM core after the Ta time is delayed. After receiving the starting signal, the ARM core can read out sampling data from the dual-port RAM according to the address pointed by the fault data reading pointer for fault current wave recording, so that the digital recording and storage functions of the fault current wave are realized.
Fig. 5 is a FPGA cache sampled data buffer module architecture. The internal memory of the module is set to be in a simple double-port mode, and high-speed sampling data is stored in an annular circulation covering mode. When the circular loop storage is carried out, if the write port pointer is detected to be a data buffer area ring head pointer, the module stores the current system time as a ring head time stamp. When the fault wave recording function module generates a starting signal, the module stores a current write port pointer as a fault DATA end pointer (DATA C); calculating to obtain a failure timestamp according to the starting delay and the current system time; and finally, calculating a failure moment write port pointer (DATA B) by the set number of pre-failure wave recording DATA points, the start delay and the failure moment write port pointer (DATA B) to obtain a failure DATA initial storage pointer. This pointer acts as a failure DATA start read pointer (DATA A). And the subsequent data interface module transmits data between the fault timestamp and the fault data starting pointer to a DDR designated buffer area in a DMA mode.
The invention has the following effects:
1) the flexible double Rogowski coil is used for measuring currents in different amplitude ranges, and has the advantages of wide measurement amplitude range, wide response frequency band, good linearity, no magnetic saturation phenomenon, small influence of the position of a measured conductor on sampling precision and the like;
2) a double-integral signal conditioning circuit is used for conditioning and amplifying signals collected by Rogowski coils of monitoring objects with different current amplitudes, and the sampling resolution and precision of a rear-stage ADC in a full measurement range are guaranteed. The hidden danger current sampling unit realizes current sampling from milliampere level to ten ampere level, and the traveling wave current sampling unit realizes current sampling from ten ampere level to kiloampere level;
3) by using double-difference high-speed ADC sampling, high-frequency current small signals sent by a preceding stage integral conditioning circuit can be respectively collected in real time, high-frequency hidden danger current and fault current signals are restored at high precision, and powerful support is provided for subsequent fault type identification, diagnosis and positioning;
4) the FPGA technology is used for concurrent calculation, the processing performance is high, the fault-tolerant function and the anti-interference performance are achieved, the double sets of sampling units are controlled, and the acquisition and storage of the whole system on the input current signal with wide amplitude, wide frequency band, high precision and high speed are achieved.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (10)

1. A high-speed sampling circuit suitable for a power transmission line fault early warning diagnosis terminal is characterized by comprising a hidden danger current sampling unit, a traveling wave current sampling unit and a control unit;
the hidden danger current sampling unit comprises a hidden danger current Rogowski coil, a hidden danger current integrating circuit and a hidden danger current differential sampling circuit; the hidden danger current Rogowski coil acquires a hidden danger current signal, converts the hidden danger current signal into a voltage signal, and inputs the voltage signal into a hidden danger current integrating circuit, the hidden danger current integrating circuit integrates, filters and amplifies the voltage signal and inputs the voltage signal into a hidden danger current differential sampling circuit, and the hidden danger current differential sampling circuit converts the input signal into a hidden danger current differential signal and outputs the hidden danger current differential signal;
the traveling wave current sampling unit comprises a traveling wave current Rogowski coil, a traveling wave current integrating circuit and a traveling wave current differential sampling circuit; the traveling wave current Rogowski coil acquires a traveling wave current signal, converts the traveling wave current signal into a voltage signal, and then inputs the voltage signal into the traveling wave current integrating circuit, the traveling wave current integrating circuit performs integration, filtering and amplification on the voltage signal, and then inputs the voltage signal into the hidden danger current differential sampling circuit, and the traveling wave current differential sampling circuit converts the input signal into a traveling wave current differential signal and outputs the traveling wave current differential signal;
the control unit respectively collects the hidden danger current differential signals and the traveling wave current differential signals output by the hidden danger current sampling unit and the traveling wave current sampling unit to obtain the hidden danger current and the traveling wave current sampling values; and when the sampling values of the hidden trouble current and the traveling wave current exceed the respective current waveform recording threshold values, the current waveform storage and recording are triggered.
2. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal according to claim 1, wherein the hidden danger current integral conditioning circuit and the traveling wave current integral conditioning circuit have the same structure.
3. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal as claimed in claim 1 or 2, wherein the hidden danger current integrating and conditioning circuit comprises an integrating circuit, a filtering circuit and an amplifying circuit;
said productThe sub-circuit comprises a first high-bandwidth operational amplifier and an external sampling resistor RsDamping resistance R1First capacitor C1Feedback resistance RFA first balance resistor RP1(ii) a External sampling resistor RsThe positive and negative output ends of the Rogowski coil are connected in parallel, and the negative output end of the Rogowski coil is grounded; the positive input end of the first high-bandwidth operational amplifier is connected with a damping resistor R1The positive output end of the Rogowski coil is connected with the rear end of the first high-bandwidth operational amplifier, and the reverse input end of the first high-bandwidth operational amplifier is connected with a first balance resistor RP1Then grounding; a first capacitor C1And a feedback resistor RFThe output end and the positive input end of the first high-bandwidth operational amplifier are connected in parallel; the output end of the first high-bandwidth operational amplifier is connected with the filter circuit;
the filter circuit comprises a second resistor R2And a second capacitor C2(ii) a The output end of the first high-bandwidth operational amplifier is connected with a second capacitor C2And a second resistor R2Back ground, second capacitor C2And a second resistor R2The electric connection point is used as the output end of the filter circuit and is connected with the amplifying circuit;
the amplifying circuit comprises a second high-bandwidth operational amplifier and a second balance resistor RP2And a third resistor R3(ii) a The output end of the filter circuit is connected with the forward input end of the second high-bandwidth operational amplifier, and the reverse input end of the second high-bandwidth operational amplifier is connected with the second balance resistor RP2The rear end is grounded, and the output end of the first high-bandwidth operational amplifier is connected with a third resistor R3And the output end of the first high-bandwidth operational amplifier outputs voltage as the output of the integral conditioning circuit.
4. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal according to claim 1, wherein the hidden danger current differential sampling circuit comprises: an adjustable gain amplifier U1, a first differential amplifier U2 and a first high-speed ADC chip U3;
the output Vo1 of the hidden danger current integral conditioning circuit is connected with the positive input end of the adjustable gain amplifier U1, and the negative input end of the adjustable gain amplifier U1 is grounded; the output end of the adjustable gain amplifier U1 is connected with the positive input end of a first differential amplifier U2, and the negative input end of the first differential amplifier U2 is grounded; the first differential amplifier U2 outputs a differential voltage signal Vo3 connected to the analog differential signal input port of the first high speed ADC chip U3; the first high-speed ADC chip U3 converts the Vo3 differential voltage signal into a differential digital signal, and sends the differential digital signal to the control unit;
the control unit is connected with an adjustable gain amplifier U1 to control the amplification gain of the adjustable gain amplifier U1.
5. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal according to claim 4, wherein the traveling wave current differential sampling circuit comprises: a second differential amplifier U4, a second high speed ADC chip U5;
the output Vo1 of the traveling wave current integral conditioning circuit is connected with the positive input end of a second differential amplifier U4, and the negative input end of the second differential amplifier U4 is grounded; the second differential amplifier U4 outputs a differential voltage signal Vo2 connected to the analog differential signal input port of the second high-speed ADC chip U5; the second high-speed ADC chip U5 converts the differential voltage signal Vo2 into a differential digital signal, which is sent to the control unit.
6. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal of claim 5, wherein the frequency of analog-to-digital conversion of the first high-speed ADC chip U3 and the second high-speed ADC chip U5 is more than 2 times of the highest frequency of the differential voltage signal.
7. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal as claimed in claim 5, wherein the control unit controls the first high-speed ADC chip U3 and the second high-speed ADC chip U5 to sample synchronously.
8. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal as claimed in claim 1, wherein the control unit comprises two independent hidden danger current ring buffers and a traveling wave current buffer, the hidden danger current ring buffers are used for storing hidden danger current sampling values and hidden danger current recording data, and the traveling wave current ring buffers are used for storing traveling wave current sampling values and traveling wave current recording data.
9. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal according to claim 8, wherein the control unit divides the operation of the annular buffer area into a sampling function module and a wave recording function module;
when the transmission line runs without faults, the sampling function module works, and the sampling function module stores the sampling data in the annular buffer area;
when the transmission line runs with a fault, the wave recording function module is started, and records the current waveform and stores the current waveform in the annular buffer area.
10. The high-speed sampling circuit applicable to the power transmission line fault early warning diagnosis terminal as recited in claim 1, wherein the control unit acquires the current time as the start time of a recording waveform when recording the current, and records the time of a fault point in a 'fault timestamp' register;
according to the set time period T = Ta + Tb before and after the fault time, T is the wave recording time length, Ta is the time length after starting, Tb is the time length before starting, a data pointer at Tb before the starting wave recording point is stored in a fault data reading pointer register, and a trigger signal is output after the Ta time is delayed;
after receiving the trigger signal, reading out the sampling data from the dual-port RAM according to the address pointed in the fault data reading pointer for fault current recording.
CN202110995137.5A 2021-08-27 2021-08-27 High-speed sampling circuit suitable for transmission line fault early warning diagnosis terminal Pending CN113917277A (en)

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Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220170965A1 (en) * 2020-12-02 2022-06-02 Hyundai Mobis Co., Ltd. Apparatus and method for compensating for offset in switching current sensing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220170965A1 (en) * 2020-12-02 2022-06-02 Hyundai Mobis Co., Ltd. Apparatus and method for compensating for offset in switching current sensing
US11940473B2 (en) * 2020-12-02 2024-03-26 Hyundai Mobis Co., Ltd. Apparatus and method for compensating for offset in switching current sensing

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