CN110875194A - 芯片封装结构的形成方法 - Google Patents

芯片封装结构的形成方法 Download PDF

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Publication number
CN110875194A
CN110875194A CN201910585617.7A CN201910585617A CN110875194A CN 110875194 A CN110875194 A CN 110875194A CN 201910585617 A CN201910585617 A CN 201910585617A CN 110875194 A CN110875194 A CN 110875194A
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layer
conductive
substrate
forming
chip
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CN201910585617.7A
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蔡柏豪
洪士庭
郑心圃
翁得期
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本公开实施例提供一种芯片封装结构的形成方法，包含：形成导电结构于基板之上；基板包含介电层和位于介电层中的布线层，且导电结构电性连接至布线层；形成第一模制层于基板之上并围绕导电结构；形成重分布结构于第一模制层和导电结构之上；以及将芯片结构接合至重分布结构。

Description

芯片封装结构的形成方法
技术领域
本公开实施例涉及芯片封装结构及其形成方法，且特别涉及芯片封装结构中的导电结构及其形成方法。
背景技术
半导体装置已运用在各种电子应用上，例如个人电脑、手机、数码相机以及其他的电子设备。半导体装置的制造通常会按序将绝缘层或介电层、导电层及半导体层沉积在半导体基板之上，并且利用光刻工艺和蚀刻工艺将各材料层图案化以形成电路元件及其上的元件。
随着半导体技术的发展，半导体芯片/晶粒变得越来越小。此时，需要将更多功能整合到半导体晶粒中。结果，半导体晶粒的封装变得更困难。
发明内容
根据本公开的一实施例，提供一种芯片封装结构的形成方法，包含：形成导电结构于基板之上，其中基板包含介电层和位于介电层中的布线层，且导电结构电性连接至布线层；形成第一模制层于基板之上并围绕导电结构和基板；形成重分布结构于第一模制层和导电结构之上；以及将芯片结构接合至重分布结构。
根据本公开的另一实施例，提供一种芯片封装结构的形成方法，包含：形成导电结构于基板之上，其中基板包含介电层和位于介电层中的布线层，且导电结构电性连接至布线层；形成第一模制层于基板之上以围绕导电结构；移除导电结构之上的第一模制层；形成重分布结构于第一模制层和导电结构之上，其中重分布结构直接接触导电结构；以及将芯片结构接合至重分布结构。
又根据本公开的另一实施例，提供一种芯片封装结构，包含：基板，包含介电层和位于介电层中的布线层，其中基板具有第一表面和侧壁，且侧壁邻接第一表面；导电结构，位于第一表面之上并电性连接至布线层；第一模制层，位于第一表面和侧壁之上以围绕导电结构和基板；重分布结构，位于第一模制层和导电结构之上；以及芯片结构，位于重分布结构之上。
附图说明
通过以下的详细描述配合说明书附图，可以更加理解本公开实施例的内容。需强调的是，根据产业上的标准惯例，许多部件(feature)并未按照比例绘制。事实上，为了能清楚地讨论，各种部件的尺寸可能被任意地增加或减少。
图1A至图1I根据一些实施例示出形成芯片封装结构的工艺的各个阶段的剖面示意图。
附图标记说明：
100～芯片封装结构
110～载体基板
120～粘着层
130、172a、174a～基板
130a、131a、131b、156～表面
131c、154、169、214～侧壁
132、161、163、165、DI1、DI2～介电层
132a、144a、161a、163a、165a～开口
134、162、164～布线层
136～导孔
138、139、166、P1、P2～导电垫
142～种子层
144～遮罩层
146～导电层
147～导电结构
147a、152、167、174d、212～顶表面
150、176d、210～模制层
160、176a～重分布结构
168、B1、B2～底表面
170～芯片结构
172、174、176b～芯片
172b、174b～装置层
172c、174c～内连线层
176～芯片封装
176c、182、184、186、220～导电凸块
190～底部充填层
D1～距离
T1、T2、T3、T4、T5～厚度
V1～方向
W1、W2、W3、W4、W5～宽度
具体实施方式
以下内容提供了许多不同的实施例或范例，用于实施所提供的标的的不同部件。组件和配置的具体范例描述如下，以简化本公开实施例。当然，这些仅仅是范例，并非用以限定本公开实施例。举例来说，叙述中若提及第一部件形成于第二部件上方，可能包含形成第一和第二部件直接接触的实施例，也可能包含额外的部件形成于第一和第二部件之间，使得第一和第二部件不直接接触的实施例。此外，本公开实施例在不同范例中可重复使用参考数字及/或字母，此重复是为了简化和清楚的目的，并非代表所讨论的不同实施例及/或组态之间有特定的关系。
此外，其中可能用到与空间相对用语，例如“在……之下”、“在……下方”、“下方的”、“在……上方”、“上方的”及类似的用词，这些空间相对用语为了便于描述如图所示的一个(些)元件或部件与另一个(些)元件或部件之间的关系。这些空间相对用语包含使用中或步骤中的装置的不同方位，以及附图中所描述的方位。当装置被转向不同方位时(旋转90度或其他方位)，则其中所使用的空间相对形容词也将依转向后的方位来解释。应理解的是，可在此方法之前、期间及之后提供额外的步骤，且在此方法的其他实施例中，可置换或删除所述的一些操作。
图1A至图1I根据一些实施例示出形成芯片封装结构的工艺的各个阶段的剖面图。根据一些实施例，如图1A所示，提供载体基板110。根据一些实施例，载体基板110被配置以在后续工艺步骤期间提供暂时性的机械和结构支撑。根据一些实施例，载体基板110包含玻璃、硅、氧化硅、氧化铝、金属、前述的组合及/或类似的材料。根据一些实施例，载体基板110包含金属框架。
根据一些实施例，如图1A所示，形成粘着层120于载体基板110之上。根据一些实施例，粘着层120直接接触载体基板110。根据一些实施例，粘着层120顺应性地(conformally)形成于载体基板110上。根据一些实施例，粘着层120是由例如聚合物材料的绝缘材料所组成。利用涂布工艺或其他合适的工艺来形成粘着层120。
根据一些实施例，如图1A所示，基板130设置在粘着层120之上。根据一些实施例，基板130具有表面131a和131b以及侧壁131c。根据一些实施例，表面131a背向载体基板110。根据一些实施例，表面131a相反于表面131b。根据一些实施例，侧壁131c位于表面131a和131b之间。根据一些实施例，侧壁131c邻接表面131a和131b。
根据一些实施例，基板130包含介电层132、布线层(wiring layers)134、导孔(conductive vias)136以及导电垫138和139。根据一些实施例，布线层134、导孔136以及导电垫138和139位于介电层132中。根据一些实施例，一些导孔136在布线层134之间电性连接。根据一些实施例，其他导孔136在布线层134和导电垫138之间电性连接。
根据一些实施例，布线层134、导孔136以及导电垫138和139彼此电性连接。介电层132是由聚合物材料或其他合适的材料所组成。举例而言，介电层132包含例如玻璃纤维材料的纤维材料、例如聚合物材料的预浸材料(prepreg material)、Ajinomoto积层膜(ABF；Ajinomoto Build-up Film)、阻焊材料或前述的组合。根据一些实施例，布线层134、导孔136以及导电垫138和139是由例如铜、铝或钨的导电材料所组成。
根据一些实施例，如图1A所示，形成种子层142于基板130之上。根据一些实施例，种子层142形成于导电垫138和介电层132之上。根据一些实施例，种子层142直接接触导电垫138及介电层132。根据一些实施例，种子层142是由钛、铜及/或其他合适的导电材料所组成。根据一些实施例，利用例如物理气相沉积工艺的沉积工艺来形成种子层142。
根据一些实施例，如图1A所示，遮罩层144形成于种子层142之上。根据一些实施例，遮罩层144具有开口144a。根据一些实施例，开口144a露出种子层142的一部分。根据一些实施例，遮罩层144是由例如光刻胶材料的聚合物材料所组成。根据一些实施例，利用涂布工艺和光刻工艺来形成遮罩层144。
根据一些实施例，如图1A所示，形成导电层146于开口144a中。根据一些实施例，导电层146是由例如铜、铝或钨的导电材料所组成。根据一些实施例，利用电镀工艺(platingprocess)或其他合适的工艺来形成导电层146，所述电镀工艺例如为电镀工艺(electro-plating process)或无电电镀工艺(electroless plating process)。
根据一些实施例，如图1B所示，移除遮罩层144。根据一些实施例，如图1B所示，移除原本位于遮罩层144之下的种子层142。根据一些实施例，如图1B所示，导电层146和位于导电层146之下的种子层142一起形成导电结构147。在一些其他实施例中，在将基板130设置于粘着层120之上之前，形成导电结构147于基板130之上。
根据一些实施例，导电结构147包含导电柱及/或导电迹线(traces)(或导线)。根据一些实施例，每一个导电结构147电性连接至其下的导电垫138。根据一些实施例，每一个导电结构147直接接触其下的导电垫138。在一些实施例中，导电结构147是导电迹线，并且导电迹线与随后形成的布线层的布线(routing)匹配。
根据一些实施例，如图1B所示，形成模制层(molding layer)150于载体基板110之上以覆盖基板130和导电结构147。根据一些实施例，模制层150覆盖基板130的表面131a和侧壁131c。根据一些实施例，模制层150直接接触基板130及导电结构147。根据一些实施例，模制层150包含聚合物材料。根据一些实施例，利用模制工艺来形成模制层150。
根据一些实施例，模制层150包含聚合物材料。根据一些实施例，用语“聚合物”可代表热固性聚合物、热塑性聚合物或前述的任何混合物。举例而言，聚合物材料可包含塑胶材料、环氧树脂，聚酰亚胺(polyimide)、聚对苯二甲酸乙二酯(polyethyleneterephthalate；PET)、聚氯乙烯(polyvinyl chloride；PVC)、聚甲基丙烯酸甲酯(polymethylmethacrylate；PMMA)、掺杂有特定填料(fillers)的聚合物成分，填料包含纤维、粘土、陶瓷、无机粒子或前述的任何组合。在其他实施例中，根据一些实施例，模制层150可由例如环氧甲酚酚醛清漆(epoxy cresol novolac；ECN)、联苯环氧树脂(biphenylepoxy resin)、多功能液态环氧树脂或前述的任何组合的环氧树脂所组成。又在其他实施例中，模制层150可由可选择性地(optionally)包含一或多种填料的环氧树脂所组成，以提供组合物任何各种所需的性质。根据一些实施例，填料的例子可为铝、二氧化钛、碳黑、碳酸钙、二氧化硅或前述的任何组合。
根据一些实施例，如图1C所示，移除模制层150的上部以露出导电结构147。根据一些实施例，移除工艺包含平坦化工艺，例如化学机械研磨工艺(chemical mechanicalpolishing process；CMP工艺)。因此，在移除工艺之后，每一个导电结构147的顶表面147a与模制层150的顶表面152共平面。
根据一些实施例，模制层150连续地围绕导电结构147和整个基板130。根据一些实施例，导电结构147在基板130之上穿过模制层150。在一些实施例中，导电结构147的厚度T1介于约2μm至约50μm的范围。在一些实施例中，导电结构147的厚度T1介于约20μm至约50μm的范围。在一些实施例中，模制层150在基板130之上的厚度T2介于约2μm至约50μm的范围。在一些实施例中，模制层150在基板130之上的厚度T2介于约20μm至约50μm的范围。
根据一些实施例，导电结构147的厚度T1大致上等于模制层150在基板130之上的厚度T2。根据一些实施例，本公开中的用语“大致上等于”意味着“在10％以内”。举例而言，根据一些实施例，用语“大致上等于”意味着厚度T1和T2之间的差异在导电结构147和位于基板130之上的模制层150之间的平均厚度的10％之内。此差异可能是由于生产工艺所导致。在一些实施例中，导电结构147的宽度W1介于约5μm至约200μm的范围。在一些实施例中，导电结构147的宽度W1介于约15μm至约30μm的范围。在一些实施例中，导电结构147之间的距离D1介于约10μm至约400μm的范围。在一些实施例中，导电结构147之间的距离D1介于约10μm至约20μm的范围。
根据一些实施例，如图1D所示，形成重分布结构(redistribution structure)160于模制层150和导电结构147之上。根据一些实施例，重分布结构160直接接触导电结构147及模制层150。
重分布结构160的形成包含：形成介电层161于模制层150和导电结构147之上，其中介电层161具有分别露出其下方的导电结构147的开口161a；形成布线层162于介电层161之上和开口161a中，以电性连接至导电结构147；形成介电层163于介电层161和布线层162之上，其中介电层163具有部分地露出布线层162的开口163a；形成布线层164于介电层163之上和开口163a中，以电性连接至布线层162；形成介电层165于介电层163和布线层164之上，其中介电层165具有部分地露出布线层164的开口165a；形成导电垫166于开口165a中。
根据一些实施例，每一个介电层161、163和165的形成包含沉积工艺(例如化学气相沉积工艺或物理气相沉积工艺)、光刻工艺和蚀刻工艺。根据一些实施例，每一个布线层162和164以及导电垫166的形成包含光刻工艺、电镀工艺和蚀刻工艺。
根据一些实施例，介电层161顺应性地形成于模制层150和导电结构147上。在一些实施例中，导电垫166的宽度W2沿着方向V1缩小，其中方向V1从重分布结构160的顶表面167到重分布结构160的底表面168。根据一些实施例，导电垫166的宽度W2小于开口163a的宽度。根据一些实施例，开口163a的宽度小于开口161a的宽度。
根据一些实施例，介电层161、163和165是由例如聚合物材料(例如聚苯并恶唑、聚酰亚胺或光敏材料)、氮化物(例如氮化硅)、氧化物(例如氧化硅)、氮氧化硅或类似的材料的绝缘材料所组成。根据一些实施例，布线层162和164以及导电垫166是由例如金属(例如铜、铝或钨)的导电材料所组成。
根据一些实施例，如图1E所示，芯片结构170通过导电凸块182、184和186接合至重分布结构160。根据一些实施例，芯片结构170包含芯片172和174以及芯片封装176。
根据一些实施例，芯片172和174以及芯片封装176通过导电凸块182、184和186电性连接至重分布结构160的导电垫166。根据一些实施例，芯片172和174以及芯片封装176通过重分布结构160和导电结构147电性连接至基板130。
芯片172和174包含芯片上系统(system-on-chip；SoC)、存储器芯片(例如动态随机存取存储器芯片)、射频(radio frequency；RF)芯片或其他合适的芯片。芯片172和174以及芯片封装176可具有相同或不同的宽度。芯片172和174以及芯片封装176可具有相同或不同的高度。
根据一些实施例，芯片172具有基板172a、装置层172b和内连线层(interconnectlayer)172c。在一些实施例中，基板172a是由包含单晶、多晶或非晶结构的硅或锗的元素半导体材料所组成。在一些其他实施例中，基板172a是由例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、合金半导体(例如SiGe或GaAsP)或前述的组合的化合物半导体所组成。
基板172a也可包含多层半导体、绝缘体上覆半导体(semiconductor oninsulator；SOI)(例如绝缘体上覆硅或绝缘体上覆锗)或前述的组合。根据一些实施例，基板172a具有面向重分布结构160的底表面B1。
根据一些实施例，装置层172b位于底表面B1之上。根据一些实施例，装置层172b包含电子元件(未示出)、介电层DI1和导电垫P1。
在一些实施例中，电子元件形成于基板172a上或基板172a中。根据一些实施例，电子元件包含主动元件(例如晶体管、二极管或类似的元件)及/或无源元件(例如电阻器、电容器、电感器或类似的元件)。根据一些实施例，介电层DI1形成于底表面B1之上并覆盖电子元件。
根据一些实施例，导电垫P1内埋于(embedded)介电层DI1中并且电性连接至电子元件。根据一些实施例，导电垫P1是由例如金属(例如铜、铝、镍或前述的组合)的导电材料所组成。
根据一些实施例，内连线层172c形成于装置层172b之上。根据一些实施例，内连线层172c包含内连线结构(未示出)和介电层(未示出)。根据一些实施例，内连线结构位于介电层中并且电性连接至导电垫P1。
根据一些实施例，导电凸块182位于导电垫166和内连线层172c之间，以通过内连线层172c的内连线结构将导电垫166电性连接至导电垫P1。
根据一些实施例，芯片174具有基板174a、装置层174b和内连线层174c。在一些实施例中，基板174a是由包含单晶、多晶或非晶结构的硅或锗的元素半导体材料所组成。在一些其他实施例中，基板174a是由例如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、合金半导体(例如SiGe或GaAsP)或前述的组合的化合物半导体所组成。
基板174a也可包含多层半导体、绝缘体上覆半导体(例如绝缘体上覆硅或绝缘体上覆锗)或前述的组合。根据一些实施例，基板174a具有面向重分布结构160的底表面B2。根据一些实施例，装置层174b位于底表面B2之上。根据一些实施例，装置层174b包含电子元件(未示出)、介电层DI2和导电垫P2。
在一些实施例中，电子元件形成于基板174a上或基板174a中。根据一些实施例，电子元件包含主动元件(例如晶体管、二极管或类似的元件)及/或无源元件(例如电阻器、电容器、电感器或类似的元件)。根据一些实施例，介电层DI2形成于底表面B2之上并覆盖电子元件。
根据一些实施例，导电垫P2内埋于介电层DI2中并且电性连接至电子元件。根据一些实施例，导电垫P2是由例如金属(例如铜、铝、镍或前述的组合)的导电材料所组成。
根据一些实施例，内连线层174c形成于装置层174b之上。根据一些实施例，内连线层174c包含内连线结构(未示出)和介电层(未示出)。根据一些实施例，内连线结构位于介电层中并且电性连接至导电垫P2。
根据一些实施例，导电凸块184位于导电垫166和内连线层174c之间，以通过内连线层174c的内连线结构将导电垫166电性连接至导电垫P2。
在一些实施例中，根据一些实施例，芯片封装176包含重分布结构(或基板)176a、芯片176b、导电凸块176c和模制层176d。根据一些实施例，重分布结构176a包含介电层(未示出)和布线层(未示出)。根据一些实施例，布线层位于介电层中。
根据一些实施例，芯片176b通过导电凸块176c接合至重分布结构176a。芯片176b包含动态随机存取存储器(dynamic random access memory；DRAM)芯片、高带宽存储器(high bandwidth memory；HBM)芯片或其他合适的芯片。
根据一些实施例，导电凸块176c将芯片176b电性连接至重分布结构176a的布线层。根据一些实施例，导电凸块176c是由例如锡和银或其他合适的导电材料(例如金)的焊料材料所组成。
根据一些实施例，模制层176d形成于重分布结构176a之上以围绕芯片176b和导电凸块176c。模制层176d是由聚合物材料或其他合适的绝缘材料所组成。
根据一些实施例，导电凸块186位于导电垫166和重分布结构176a之间，以通过重分布结构176a的布线层和导电凸块176c将导电垫166电性连接至芯片176b。
根据一些实施例，导电凸块186比导电凸块182或184宽。根据一些实施例，导电凸块182或184也称为微凸块。根据一些实施例，导电凸块186也称为C4凸块。
在一些实施例中，导电凸块182的宽度W3介于约10μm至约150μm的范围。在一些实施例中，导电凸块182的宽度W3介于约40μm至约50μm的范围。在一些实施例中，导电凸块184的宽度W4介于约10μm至约150μm的范围。在一些实施例中，导电凸块184的宽度W4介于约40μm至约50μm的范围。在一些实施例中，导电凸块186的宽度W5介于约50μm至约250μm的范围。在一些实施例中，导电凸块186的宽度W5介于约100μm至约150μm的范围。
根据一些实施例，导电凸块182、184和186是由例如锡和银或其他合适的导电材料(例如金)的焊料材料所组成。根据一些实施例，导电凸块182、184和186是焊球。
根据一些实施例，如图1E所示，形成底部充填层190于芯片172和174、芯片封装176和重分布结构160之间。根据一些实施例，底部充填层190围绕芯片172和174、芯片封装176以及导电凸块182、184和186。根据一些实施例，底部充填层190是由绝缘材料所组成，所述绝缘材料例如为聚合物材料或由环氧树脂和充填材料组成的模制化合物材料。
根据一些实施例，在基板130的热膨胀系数(coefficient of thermalexpansion；CTE)、模制层150的热膨胀系数和载体基板110的热膨胀系数之间实现了热膨胀系数平衡。因此，根据一些实施例，降低了基板130的翘曲(warpage)。从而，改善了随后形成于表面131b之上的导电凸块的共面性(coplanarity)。
由于导电结构147、模制层150和重分布结构160以良好的共面性按序形成于基板130之上，导电结构147、模制层150和重分布结构160具有良好的共面性，这改善了导电凸块182、184和186与重分布结构160之间的粘结性(bondability)。
根据一些实施例，如图1F所示，形成模制层210于重分布结构160、底部充填层190、芯片172和174以及芯片封装176之上。根据一些实施例，模制层210包含聚合物材料。根据一些实施例，利用模制工艺来形成模制层210。
根据一些实施例，如图1G所示，移除模制层210的上部以露出芯片174的顶表面174d。因此，根据一些实施例，芯片174的散热效率得到改善。
根据一些实施例，移除工艺包含平坦化工艺，例如化学机械研磨工艺(化学机械研磨工艺)。因此，根据一些实施例，在移除工艺之后，顶表面174d与模制层210的顶表面212共平面。在一些其他实施例(未示出)中，顶表面174d和212以及芯片172和芯片封装176的顶表面与彼此共平面。
根据一些实施例，模制层210围绕芯片172和174以及芯片封装176、导电凸块182、184和186以及底部充填层190。根据一些实施例，模制层210直接接触芯片172和174以及芯片封装176和底部充填层190。
根据一些实施例，如图1H所示，将基板130上下翻转。根据一些实施例，如图1H所示，移除载体基板110。根据一些实施例，如图1H所示，移除粘着层120。
根据一些实施例，如图1I所示，移除介电层132的一部分以于介电层132中形成开口132a。根据一些实施例，开口132a露出其下的导电垫139。
根据一些实施例，如图1I所示，导电凸块220分别形成于由开口132a露出的导电垫139之上。根据一些实施例，导电凸块220是由例如锡和银或其他合适的导电材料的焊料材料所组成。
根据一些实施例，如图1I所示，在模制层150、重分布结构160和模制层210上进行切割工艺(或锯切(sawing)工艺)以切穿模制层150和210以及重分布结构160，以形成芯片封装结构100。为了简单起见，根据一些实施例，图1I仅示出其中一个芯片封装结构100。
在一些实施例中，在切割工艺之后，模制层150的侧壁154、重分布结构160的侧壁169和模制层210的侧壁214与彼此共平面。在一些实施例中，基板130的表面130a与模制层150的表面156共平面。根据一些实施例，导电结构147的厚度T1小于重分布结构160的厚度T3、基板130的厚度T4和芯片172的厚度T5中的任一个。
根据一些实施例，由于重分布结构160通过导电结构147(其由电镀工艺形成)电性连接至基板130而非焊球，因此不需要进行退火工艺来将焊球接合至基板130。因此，根据一些实施例，降低了基板130的翘曲。
此外，导电结构147是通过电镀工艺形成于基板130之上，因此导电结构147的形成不会受到基板130翘曲的影响。因此，根据一些实施例，导电结构147和基板130之间的粘结性得到改善。
由于导电结构147是通过在遮罩层144的开口144a中形成导电层146而形成，因此可利用光刻工艺来调整遮罩层144的开口144a(如图1A和图1B所示)以调节导电结构147的尺寸和两个相邻导电结构147之间的距离。因此，导电结构147的尺寸和两个相邻导电结构147之间的距离可小于焊球的尺寸/焊球之间的距离及/或比焊球的尺寸/焊球之间的距离更为均匀。结果，改善了导电结构147的密度。
根据一些实施例，提供芯片封装结构及其形成方法。此方法(用于形成芯片封装结构)包含利用电镀工艺形成导电结构于基板和重分布结构之间。因此，导电结构和基板之间的粘结性不会受到基板翘曲的影响。结果，基板和重分布结构之间的电性连接性质得到改善。
根据一些实施例，提供一种芯片封装结构的形成方法。所述方法包含形成导电结构于基板之上。基板包含介电层和位于介电层中的布线层，且导电结构电性连接至布线层。所述方法包含形成第一模制层于基板之上并围绕导电结构。所述方法包含形成重分布结构于第一模制层和导电结构之上。所述方法包含将芯片结构接合至重分布结构。
在一些实施例中，第一模制层连续地覆盖基板的表面和侧壁，所述表面面向重分布结构，且所述侧壁邻接并围绕所述表面。在一些实施例中，所述芯片封装结构的形成方法还包含：在将芯片结构接合至重分布结构之后，形成导电凸块于基板之上，其中基板位于导电凸块和重分布结构之间。在一些实施例中，所述芯片封装结构的形成方法还包含：在形成导电凸块于基板之上之后，切穿第一模制层和重分布结构。在一些实施例中，在切穿第一模制层和重分布结构之后，第一模制层的第一侧壁与重分布结构的第二侧壁共平面。在一些实施例中，导电结构穿过第一模制层。在一些实施例中，重分布结构直接接触导电结构及第一模制层。在一些实施例中，芯片结构通过重分布结构和导电结构电性连接至基板。在一些实施例中，所述芯片封装结构的形成方法还包含：形成第二模制层于重分布结构之上并围绕芯片结构。在一些实施例中，所述芯片封装结构的形成方法还包含：在形成第二模制层于重分布结构之上之前，形成底部充填层于芯片结构和重分布结构之间，其中第二模制层更围绕底部充填层。
根据一些实施例，提供一种芯片封装结构的形成方法。所述方法包含形成导电结构于基板之上。基板包含介电层和位于介电层中的布线层，且导电结构电性连接至布线层。所述方法包含形成第一模制层于基板之上以围绕导电结构。所述方法包含移除导电结构之上的第一模制层。所述方法包含形成重分布结构于第一模制层和导电结构之上。重分布结构直接接触导电结构。所述方法包含将芯片结构接合至重分布结构。
在一些实施例中，导电结构的形成包含：形成种子层于基板之上；形成遮罩层于种子层之上，其中遮罩层具有开口，所述开口部分地露出种子层；形成导电层于开口中；以及移除遮罩层和位于遮罩层之下的种子层，其中导电层和位于导电层之下的种子层一起形成导电结构。在一些实施例中，导电层的形成包含电镀工艺或无电电镀工艺。在一些实施例中，在移除导电结构之上的第一模制层之后，第一模制层的第一顶表面与导电结构的第二顶表面共平面。在一些实施例中，形成重分布结构于第一模制层和导电结构之上包含：形成介电层于第一模制层和导电结构之上，其中介电层具有开口，所述开口露出导电结构；以及形成布线层于介电层之上和开口中以连接至导电结构，其中芯片结构电性连接至布线层。
根据一些实施例，提供一种芯片封装结构。所述芯片封装结构包含基板，其包含介电层和位于介电层中的布线层。基板具有第一表面和侧壁，且所述侧壁邻接所述第一表面。所述芯片封装结构包含导电结构，其位于第一表面之上并电性连接至布线层。所述芯片封装结构包含第一模制层，其位于第一表面和侧壁之上以围绕导电结构和基板。所述芯片封装结构包含重分布结构，其位于第一模制层和导电结构之上。所述芯片封装结构包含芯片结构，其位于重分布结构之上。
在一些实施例中，第一模制层的第一侧壁与重分布结构的第二侧壁共平面。在一些实施例中，所述芯片封装结构还包含第二模制层，其位于重分布结构之上并围绕芯片结构，其中第二模制层的第三侧壁与第一模制层的第一侧壁及重分布结构的第二侧壁共平面。在一些实施例中，第一模制层的第一顶表面与导电结构的第二顶表面共平面。在一些实施例中，基板具有相对于第一表面的第二表面，且第二表面与第一模制层的第三表面共平面。
前述内文概述了许多实施例的部件，以使本技术领域中技术人员可以从各个方面更加了解本公开实施例。本技术领域中技术人员应可理解，且可轻易地以本公开实施例为基础来设计或修饰其他工艺及结构，并以此达到相同的目的及/或达到与在此介绍的实施例等相同的优点。本技术领域中技术人员也应了解这些相等的结构并未背离本公开的构思与范围。在不背离本公开的构思与范围的前提下，可对本公开实施例进行各种改变、置换或修改。

Claims (1)

1.一种芯片封装结构的形成方法，包括：
形成一导电结构于一基板之上，其中该基板包含一介电层和位于该介电层中的一布线层，且该导电结构电性连接至该布线层；
形成一第一模制层于该基板之上并围绕该导电结构和该基板；
形成一重分布结构于该第一模制层和该导电结构之上；以及
将一芯片结构接合至该重分布结构。
CN201910585617.7A 2018-08-30 2019-07-01 芯片封装结构的形成方法 Pending CN110875194A (zh)

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