CN110873831A - Frequency fault injector for medium-low frequency sinusoidal signals - Google Patents
Frequency fault injector for medium-low frequency sinusoidal signals Download PDFInfo
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- CN110873831A CN110873831A CN201911222054.1A CN201911222054A CN110873831A CN 110873831 A CN110873831 A CN 110873831A CN 201911222054 A CN201911222054 A CN 201911222054A CN 110873831 A CN110873831 A CN 110873831A
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Abstract
The invention provides a frequency fault injector facing a medium-low frequency sinusoidal signal, which comprises a fault injection controller and a fault injection upper computer; the fault injection upper computer is used for sending a fault injection instruction and controlling the fault injection controller to generate a fault sine signal; the fault injection controller generates a simulated fault sinusoidal signal based on a fault instruction sent by the upper computer. The injector adopts a frequency spectrum separation-fault reconstruction technology to collect, process and analyze input signals and reconstruct fault signals on the basis, so that the frequency parameters of the input signals are adjusted on the premise of not changing the amplitude and the offset of the input signals, the adjustment range is 2 Hz-600 KHz, and the amplitude and the offset of output signals can be automatically identified and kept to be the same as those of the input signals in the adjustment process.
Description
Technical Field
The invention relates to the technical field of fault testing, in particular to a frequency fault injector facing a medium-low frequency sinusoidal signal.
Background
The testability is a design characteristic that equipment can timely and accurately determine the working state of the equipment and effectively isolate internal faults of the equipment. The fault injection is used as a test method for checking the fault tolerance of system equipment, and is an important means for ensuring the reliability of equipment in a verification stage. The testability verification work of the avionics system mainly comprises the step of injecting different types of faults into developed equipment so as to verify the self-protection capability and the recovery capability of the system under the complex and severe working environment.
The sinusoidal signal is taken as a common typical signal in an avionic system, has complex carried content, can indicate important working parameters, and is inevitable in the fault injection work of a testability test. However, at present, the testability fault injection technology is mainly divided into plug-in type, probe type, external bus type, adapter plate type and software type fault injection. The 5-class fault injection method mainly realizes fault injection of common digital signals and analog signals in a physical layer, an electrical layer and a protocol layer, and the mechanism is realized by changing the level. For a sinusoidal signal, the fault forms of the sinusoidal signal include three types of 'amplitude abnormity', 'bias abnormity' and 'frequency abnormity', fault injection facing to the amplitude and the bias can be realized by an amplifier, but fault facing to the frequency cannot be realized by the amplifier due to non-linear change. Currently, the signal generator can realize the control of the frequency of the sinusoidal signal, however, this way changes the amplitude and the offset while changing the frequency, and cannot realize accurate injection, so that currently, a sinusoidal signal injection means which is solely oriented to the frequency parameter is lacked in the technical field.
Disclosure of Invention
The invention aims to solve the technical problem of simulating a fault frequency form to realize accurate injection of a sine frequency fault signal on the premise of not damaging an avionic system.
The invention provides a frequency fault injector facing a medium-low frequency sinusoidal signal, which comprises a fault injection controller and a fault injection upper computer; the fault injection upper computer is used for sending a fault injection instruction and controlling the fault injection controller to generate a fault sine signal; the fault injection controller comprises a case, a fault injection main board and a cross-linked cable inside the case; the chassis comprises a front panel and a rear panel, wherein the front panel comprises a power switch, a BNC input channel interface and a BNC output interface; the rear panel comprises a power interface and an RS232 communication interface; the fault injection main board comprises a frequency spectrum separation unit, a fault reconstruction unit and a main control unit; the frequency spectrum separation unit is used for automatically collecting the frequency, amplitude and bias parameters of the sinusoidal signals and realizing the identification of the characteristics and parameters of the input sinusoidal signals; the spectrum separation unit consists of a sampling isolation circuit, a low-pass filter LFP circuit and a peakThe device comprises a value detection circuit, a pulse shaping circuit, a channel control circuit and an ADC circuit; input signal uiForming a DC signal u by a low-pass filterLTo obtain the offset V of the input signald(ii) a At the same time, the input signal uiAnd the direct current signal uLPerforming subtraction operation to form a standard sinusoidal signal uHSaid standard sinusoidal signal uHThe peak value V of the signal is obtained after passing through the peak detection circuitpSaid peak value VpAnd an offset VdThe channel control circuit selects the channel and outputs the channel to the ADC circuit to obtain a digital result; furthermore, the input signal uiThe sine wave is transformed into a pulse signal f through the pulse shaping circuit, and the pulse signal f enters a timer of the main control unit for counting to obtain the input signal uiThe frequency of (d); the fault reconstruction unit generates a simulated fault sinusoidal signal based on a fault instruction sent by the fault injection upper computer; the fault reconstruction unit comprises a DDS circuit, an amplitude conversion circuit, a gain adjustment circuit, a bus control circuit and a DAC circuit; the DDS circuit generates a standard sinusoidal signal, forms a bipolar signal after amplitude conversion, and further recovers the input signal u through the gain adjusting circuitiPeak value of (V)pWhile the DAC produces an offset VdThe bipolar signal and the direct current signal are subjected to addition operation through the summing circuit to form a fault signal; the frequency of the fault signal is determined by the main control unit in combination with the pulse signal f and parameters in the fault injection instruction; the main control unit is used for receiving the instruction of the fault injection upper computer, adjusting the working parameters of the frequency spectrum separation unit and the fault reconstruction unit, and sending the current working state and working parameters of the fault injection controller to the fault injection upper computer;
preferably, the input signal uiThe sinusoidal signal obtained from the tested system when the tested system works normally.
Preferably, the main control unit comprises an MCU.
Preferably, the MCU comprises a timer unit for measuring the frequency of the input signal.
Preferably, the MCU includes a UART unit for performing RS232 communication with the fault injection upper computer.
Preferably, the MCU includes an SPI1 unit, an SPI2 unit, an SPI3 unit, a watchdog unit and an I/O port;
the SPI1 unit controls the ADC circuit to collect the input signal uiAmplitude and bias parameters of; the SPI2 unit controls the DDS circuit to form a fault sine signal; the SPI3 unit controls the DAC and performs gain adjustment simultaneously; the watchdog unit monitors the running state of system software to prevent a program from running away; the I/O port is used for indicating the system running state.
Preferably, the SPI3 unit comprises a bus driver.
Preferably, the communication protocol of the RS232 communication is as follows:
a transmission interface: RS 232;
and (3) transmission protocol: 115200bps, 8, N, 1;
wrapping heads: the 1 st and 2 nd bytes of each packet data are fixed as 0x55 and 0 xAA; the header 1, 2 bytes of the response packet are fixed to 0xAA, 0x 55;
command word: the instruction word of each packet data processing, which represents the instruction to be processed by the packet, is located in the 3 rd byte;
length word: the 4 th and 5 th bytes of each packet data are length words, only the length of the data bytes, if the current packet has no data word, the length word is 0x0000, the length word adopts a small-end byte order, the low byte is in front, and the high byte is in back;
a data word: the 6 th byte of each packet data starts to the previous byte of the check word;
checking words: the last byte of each packet data is the XOR result from the start to the end of the data word;
instruction description: the command is divided into a control command and a response command, and the packet format structures of a control command packet and a response command packet are the same. The control command is even, the response command is odd, and the value is the corresponding control command plus 1;
and returning data is successful: when a command which can be correctly analyzed is received, a response command is returned, and the command word of the response command is the control command word plus 1;
failure to return data: return when an error or unrecognizable command is received: 0xAA, 0x55, 0x0F, 0x00, 0x00, 0xX 0R;
command parsing: the content of the first 2 bytes in each data packet is fixed and is 0x55, 0xAA when being sent; in response, 0xAA, 0x 55.
Compared with the prior art, the invention has the following effects:
the frequency fault injector for the medium-low frequency sinusoidal signals adopts a frequency spectrum separation-fault reconstruction technology, the frequency spectrum separation unit is used for automatically collecting the frequency, amplitude and offset parameters of the sinusoidal signals and realizing the identification of the characteristics and parameters of the input sinusoidal signals, on the basis, the fault reconstruction unit generates simulated fault sinusoidal signals based on fault instructions sent by the fault injection upper computer, the frequency parameters of the input signals are adjusted on the premise of not changing the amplitude and offset of the input signals, the adjustment range is 2 Hz-600 KHz, and the amplitude and offset of the output signals can be automatically identified and kept the same as those of the input signals in the adjustment process.
Drawings
FIG. 1 is a schematic diagram of a frequency fault injector practical use scenario in an embodiment of the present invention; and
fig. 2 is a schematic diagram of the functional principle of the frequency fault injection main board in the embodiment of the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
As shown in fig. 1, the frequency fault injector for medium and low frequency sinusoidal signals provided in this embodiment includes a fault injection controller and a fault injection upper computer, and can perform frequency adjustment on sinusoidal signals within 2Hz to 600KHz without changing amplitude and bias.
And the fault injection upper computer is used for sending a fault injection instruction and controlling the fault injection controller to generate a fault sine signal.
The fault injection controller includes a fault injector chassis, a fault injection motherboard, and a cross-linked cable inside the chassis.
The fault injection chassis comprises a front panel and a rear panel, wherein the front panel comprises 1 power switch, 4 BNC input channel interfaces (IN 1-IN 4) and 4 BNC output interfaces (OUT 1-OUT 4).
The rear panel comprises 1 220V power interface and 1 DB9 packaged RS232 communication interface.
As shown in fig. 2, the fault injection main board includes a spectrum separation unit, a fault reconstruction unit, and a main control unit;
the frequency spectrum separation unit is used for automatically collecting the frequency, amplitude and bias parameters of the sinusoidal signals and realizing the identification of the characteristics and parameters of the input sinusoidal signals; the frequency spectrum separation unit consists of a sampling isolation circuit, a low-pass filter LFP circuit, a peak detection circuit, a pulse shaping circuit, a channel control circuit and an ADC circuit; taking sinusoidal signal obtained from normal operation of tested system as input signal uiInput signal uiForming a DC signal u by a low-pass filterLTo obtain the offset V of the input signald(ii) a At the same time, the input signal uiAnd a direct current signal uLPerforming subtraction operation to form a standard sinusoidal signal uHStandard sinusoidal signal uHThe peak value V of the signal is obtained after passing through the peak detection circuitpPeak value VpAnd an offset VdThe channel control circuit selects the channel and outputs the channel to the ADC circuit to obtain a digital result; in addition, the input signal uiThe sine wave is transformed into a pulse signal f through a pulse shaping circuit, and the pulse signal f enters a timer in an MCU processor of the main control unit for counting to obtain an input signal uiThe model of the MCU processor in this embodiment is STM32F 4.
The fault reconstruction unit generates a simulated fault sinusoidal signal based on a fault instruction sent by the fault injection upper computer; the fault reconstruction unit comprises a DDS circuit, an amplitude conversion circuit, a gain adjustment circuit, a bus control circuit and a DAC circuit;the DDS circuit generates a standard sinusoidal signal, forms a bipolar signal after amplitude conversion, and further recovers to an input signal u through a gain adjusting circuitiPeak value of (V)pWhile the DAC produces a signal corresponding to said offset VdThe same direct current signal, the bipolar signal and the direct current signal are added through a summing circuit to form a fault signal; and the frequency of the fault signal is determined by combining the pulse signal f and the parameters in the fault injection instruction through the MCU of the main control unit.
The main control unit is used for receiving the instruction of the fault injection upper computer, adjusting the working parameters of the frequency spectrum separation unit and the fault reconstruction unit, and sending the current working state and the working parameters of the fault injection controller to the fault injection upper computer.
The MCU in the embodiment also comprises an SPI1 unit, an SPI2 unit, an SPI3 unit, a watchdog unit and an I/O port; the SPI1 unit controls an ADC circuit to collect the input signal uiAmplitude and bias parameters of; the SPI2 unit controls the DDS circuit to form a fault sine signal; the SPI3 unit simultaneously controls a DAC and performs gain adjustment, and a bus driver is added to the SPI3 unit for increasing the driving capability; the watchdog unit monitors the running state of system software to prevent the program from running away; the I/O port is used for indicating the running state of the system.
MCU still includes the UART unit that is used for carrying out RS232 communication with the fault injection host computer, and communication chip adopts MAX232 chip in this embodiment, and the communication protocol of RS232 communication is as follows:
a transmission interface: RS 232;
and (3) transmission protocol: 115200bps, 8, N, 1;
wrapping heads: the 1 st and 2 nd bytes of each packet data are fixed as 0x55 and 0 xAA; the header 1, 2 bytes of the response packet are fixed to 0xAA, 0x 55;
command word: the instruction word of each packet data processing, which represents the instruction to be processed by the packet, is located in the 3 rd byte;
length word: the 4 th and 5 th bytes of each packet data are length words, only the length of the data bytes, if the current packet has no data word, the length word is 0x0000, the length word adopts a small-end byte order, the low byte is in front, and the high byte is in back;
a data word: the 6 th byte of each packet data starts to the previous byte of the check word;
checking words: the last byte of each packet data is the XOR result from the start to the end of the data word;
instruction description: the command is divided into a control command and a response command, and the packet format structures of a control command packet and a response command packet are the same. The control command is even, the response command is odd, and the value is the corresponding control command plus 1;
and returning data is successful: when a command which can be correctly analyzed is received, a response command is returned, and the command word of the response command is the control command word plus 1;
failure to return data: return when an error or unrecognizable command is received: 0xAA, 0x55, 0x0F, 0x00, 0x00, 0xX 0R;
command parsing: the content of the first 2 bytes in each data packet is fixed and is 0x55, 0xAA when being sent; in response, 0xAA, 0x 55.
And the main control unit receives the fault injection upper computer instruction by adopting an RS232 interface, generates a fault signal and returns a fault operation state and working parameters. The communication protocol is as follows:
a transmission interface: RS 232;
and (3) transmission protocol: 115200bps, 8, N, 1;
wrapping heads: the 1 st and 2 nd bytes of each packet data are fixed as 0x55 and 0 xAA; the header 1, 2 bytes of the response packet are fixed to 0xAA, 0x 55;
command word: the instruction word of each packet data processing, which represents the instruction to be processed by the packet, is located in the 3 rd byte;
length word: the 4 th and 5 th bytes of each packet data are length words, except the length of the data bytes, and if there is no data word in the current packet, the length word is 0x 0000. The length word adopts a small-end byte order, the low byte is in front, and the high byte is in back;
a data word: the 6 th byte of each packet data starts to the previous byte of the check word;
checking words: the last byte of each packet data is the XOR result from the start to the end of the data word;
instruction description: the command is divided into a control command and a response command, and the packet format structures of a control command packet and a response command packet are the same. The control command is even, the response command is odd, and the value is the corresponding control command plus 1;
and returning data is successful: when a command that can be correctly parsed is received, a response command is returned. The command word in response to the command adds 1 to the control command word.
Failure to return data: return when an error or unrecognizable command is received: 0xAA, 0x55, 0x0F, 0x00, 0x00, 0xX 0R.
Command parsing: the content of the first 2 bytes in each data packet is fixed and is 0x55, 0xAA when being sent; in response, 0xAA, 0x 55.
The control command design of the frequency fault injector for the medium and low frequency sinusoidal signals of the embodiment is shown in tables 1 and 2:
TABLE 1 Peak, mean, frequency measurement Command
TABLE 2 Fault frequency sinusoidal Signal Generation Command
The frequency fault injector facing the medium-low frequency sinusoidal signals in the embodiment comprises three working modes of continuous fault injection, interval fault injection and scanning fault injection;
continuous fault injection: continuously injecting a fault until the fault injection upper computer sends a command to stop fault injection;
interval fault injection: injecting a fault with fixed parameters according to the specified interval time and duration, and stopping the fault after the injection times are completed;
step fault injection: and fault injection is carried out according to the specified starting, ending, stepping amount and interval time, and the last injection state is kept after the injection is finished until the upper computer sends a command to stop the fault injection.
In this embodiment, a sinusoidal signal between one LRU1 and one LRU2 is selected for fault injection, as shown in fig. 1, the sinusoidal signal Vpp is 1.5V, the frequency is 10kHz, the dc offset is 1V, and the detailed operation process when a fault is performed by using the frequency fault injector channel 4 is as follows:
step 1: disconnecting the original connection between the LRU1 and the LRU2 (a → B → C → D), and connecting the frequency fault injection controller IN series into the fault injection path using the fault injection cables 1, 2 to form a new connection loop (a → B → IN4 → OUT4 → D);
step 2: operating upper computer software, and establishing communication connection between the fault injection controller and the upper computer;
and step 3: the fault injection type is selected, fault injection parameters are configured, and the detailed configuration parameters required under different fault injection types are shown in table 3.
TABLE 3 parameter configuration
And 4, step 4: and sending a fault injection instruction and executing fault injection.
And 5: the fault injection is stopped.
The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and do not limit the scope of the present invention, and various modifications and improvements made to the technical solution of the present invention by those skilled in the art without departing from the spirit of the present invention shall fall within the protection scope defined by the claims of the present invention.
Claims (7)
1. A frequency fault injector facing to medium and low frequency sinusoidal signals comprises a fault injection controller and a fault injection upper computer; the fault injection upper computer is used for sending a fault injection instruction and controlling the fault injection controller to generate a fault sine signal; the fault injection controller comprises a case, a fault injection main board and a cross-linked cable inside the case; the chassis comprises a front panel and a rear panel, wherein the front panel comprises a power switch, a BNC input channel interface and a BNC output interface; the rear panel comprises a power interface and an RS232 communication interface; it is characterized in that the preparation method is characterized in that,
the fault injection main board comprises a frequency spectrum separation unit, a fault reconstruction unit and a main control unit;
the frequency spectrum separation unit is used for identifying the characteristics and parameters of an input sinusoidal signal and automatically acquiring the frequency, amplitude and bias parameters of the sinusoidal signal; the frequency spectrum separation unit comprises a sampling isolation circuit, a low-pass filter circuit, a peak detection circuit, a pulse shaping circuit, a channel control circuit and an ADC circuit; input signal uiForming a DC signal u by a low-pass filterLObtaining an offset V of the input signald(ii) a At the same time, the input signal uiAnd the direct current signal uLPerforming subtraction operation to form a standard sinusoidal signal uHSaid standard sinusoidal signal uHThe peak value V of the signal is obtained after passing through the peak detection circuitpSaid peak value VpAnd an offset VdThe channel control circuit selects the channel and outputs the channel to the ADC circuit to obtain a digital result; the input signal uiThe sine wave is transformed into a pulse signal f through the pulse shaping circuit, and the pulse signal f enters the main control unit for counting to obtain the input signal uiThe frequency of (d);
the fault reconstruction unit generates a simulated fault sinusoidal signal based on a fault instruction sent by the fault injection upper computer; the fault reconstruction unit comprises a DDS circuit, an amplitude conversion circuit, a gain adjustment circuit, a bus control circuit and a DAC circuit; the DDS circuit generates a standard sinusoidal signal, the standard sinusoidal signal forms a bipolar signal after passing through the amplitude conversion circuit, and the bipolar signal is further recovered to the input signal through the gain adjustment circuitNumber uiPeak value of (V)pWhile the DAC produces an offset VdThe bipolar signal and the direct current signal are added through a summing circuit to form a fault signal; the frequency of the fault signal is determined by the main control unit in combination with the pulse signal f and parameters in the fault injection instruction; and
the main control unit is used for receiving the instruction of the fault injection upper computer, adjusting the working parameters of the frequency spectrum separation unit and the fault reconstruction unit, and sending the current working state and working parameters of the fault injection controller to the fault injection upper computer.
2. The medium-low frequency sinusoidal signal oriented frequency fault injector of claim 1, wherein the input signal uiThe sinusoidal signal obtained from the tested system when the tested system works normally.
3. The medium and low frequency sinusoidal signal oriented frequency fault injector of claim 1, wherein the master control unit includes an MCU.
4. The medium and low frequency sinusoidal signal oriented frequency fault injector of claim 3, wherein the MCU includes a timer unit for measuring input signal frequency.
5. The medium and low frequency sinusoidal signal oriented frequency fault injector of claim 1, wherein the MCU includes a UART unit for RS232 communication with the fault injection upper computer.
6. The mid-low frequency sinusoidal signal oriented frequency fault injector of claim 1, wherein the MCU includes an SPI1 unit, an SPI2 unit, an SPI3 unit, a watchdog unit and I/O ports;
the SPI1 unit controls the ADC circuit to collect the input signal uiAmplitude and bias parameters of; the above-mentionedThe SPI2 unit controls the DDS circuit to form a fault sine signal; the SPI3 unit controls the DAC and performs gain adjustment simultaneously; the watchdog unit monitors the running state of system software; the I/O port is used for indicating the system running state.
7. The medium and low frequency sinusoidal signal facing frequency fault injector of claim 6, wherein said SPI3 unit comprises a bus driver.
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| CN201911222054.1A CN110873831B (en) | 2019-12-03 | 2019-12-03 | Frequency fault injector for medium-low frequency sinusoidal signals |
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