CN109388529B - Relay protection CPU (Central processing Unit) mainboard performance detection method and system - Google Patents
Relay protection CPU (Central processing Unit) mainboard performance detection method and system Download PDFInfo
- Publication number
- CN109388529B CN109388529B CN201710672439.2A CN201710672439A CN109388529B CN 109388529 B CN109388529 B CN 109388529B CN 201710672439 A CN201710672439 A CN 201710672439A CN 109388529 B CN109388529 B CN 109388529B
- Authority
- CN
- China
- Prior art keywords
- test
- main board
- management device
- tested
- cpu main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention provides a method and a system for detecting the performance of a relay protection CPU main board, wherein the detecting system comprises an upper computer, a test management device and an auxiliary test device, the upper computer is connected with the test management device, the test management device is used for being connected with the CPU main board to be detected, and the FPGA auxiliary module is used for being connected with the CPU main board to be detected through a backboard bus; the upper computer is used for sending a CPU main board performance test command; the test management device is used for receiving the test instruction sent by the upper computer, forwarding the test instruction to the CPU main board to be tested, receiving the test result of the CPU main board and forwarding the test result to the upper computer. The invention realizes the automatic test of the hardware functional module of the CPU board card, improves the detection efficiency and the accuracy of the detection result, saves the cost of manpower and material resources, reduces the artificial error in the test process, and greatly shortens the production and debugging period of the product.
Description
Technical Field
The invention belongs to the technical field of relay protection and control automation of a power system, and particularly relates to a relay protection CPU (central processing unit) mainboard performance detection method and system.
Background
In recent years, the development of an electric power system has higher and higher requirements on the reliability of a hardware system of a microcomputer relay protection device, how to ensure the quality of the hardware system is an urgent problem to be solved, the relay protection device is a main component of the electric power system, whether the relay protection device can normally operate directly influences the reliability and the safety of the operation of the electric power system, a CPU board is used as a core board of the relay protection device, and the input and the output of the data acquisition and the switching value of the whole computer system are concentrated in the printed board. The correctness and performance of the hardware function are directly related to the operation safety and reliability of the device. In the production and debugging stage of the relay protection CPU board, each functional module needs to be tested, and verification and performance evaluation are carried out functionally so as to meet the design requirements. The traditional manual testing method is time-consuming and labor-consuming, even can not achieve the aim of testing, is complex in operation, repeated in operation and easy to make mistakes; manual intervention is needed in manual test, and items to be tested are easily missed in the test process, so that the test function of a CPU main board is imperfect, the production test period of a product is increased, and the maintenance cost is increased.
Disclosure of Invention
The invention aims to provide a relay protection CPU motherboard performance detection method and system, which are used for solving the problems of low detection efficiency and inaccurate detection result in the CPU motherboard performance detection in the prior art.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a relay protection CPU main board performance detection system comprises an upper computer, a test management device and an auxiliary test device; the test management device comprises a first communication interface, a first network port and a first serial port; the measurement management device is connected with the upper computer through the first communication interface; the test management device is used for connecting with a first network port of the CPU main board to be tested through the first network port of the test management device; the auxiliary testing device comprises a front terminal and a back board terminal, the front terminal of the auxiliary testing device is connected with the first serial port of the testing management device, the back board terminal of the auxiliary testing device is connected with a corresponding port of the CPU main board to be tested through a back board connecting line, and the auxiliary testing device is used for being in communication connection with the CPU main board to be tested through a back board bus.
Further, the auxiliary testing device further comprises a D/A conversion module, and the D/A conversion module is connected with the backboard terminal of the auxiliary testing device.
Further, the first communication interface of the test management device and the first network port of the test management device are ethernet interfaces.
Further, the auxiliary test device comprises an FPGA.
The invention also provides a detection method for implementing the relay protection CPU main board performance detection system, which comprises the following steps:
1) The upper computer sends a test command, the test management device receives the test command through a first communication interface of the test management device, sends a digital quantity signal for testing to the auxiliary test device through a first serial port of the test management device, and simultaneously sends the digital quantity signal for testing to a CPU main board to be tested through a first network port of the test management device;
2) The auxiliary testing device receives the digital quantity signal through a front terminal and sends the digital quantity signal to a CPU main board to be tested, and the CPU main board to be tested receives the digital quantity signal through a corresponding port of the CPU main board to be tested;
3) The auxiliary testing device is used for carrying out digital-to-analog conversion on the digital quantity signals, sending the analog quantity after digital-to-analog conversion to a corresponding port of the CPU main board to be tested through a backboard terminal of the auxiliary testing device, carrying out analog-to-digital conversion on the analog quantity by the CPU main board to be tested, comparing the digital quantity after analog-to-digital conversion with digital quantity signals for testing, which are sent from a first network port of the testing management device to a first network port of the CPU main board to be tested, detecting whether the digital quantity signals are consistent or not, and generating a testing result;
4) The CPU main board to be tested sends the test result to a first network port of the test management device through a first network port of the CPU main board to be tested, and the test management device feeds back the test result to the upper computer through a first communication interface of the test management device.
The invention also provides a detection method for implementing the relay protection CPU main board performance detection system, which comprises the following steps:
(1) The upper computer sends a test instruction, the test management device receives the test instruction through a first communication interface of the test management device, a first signal for testing is sent to a first network port of a CPU main board to be tested through a first network port of the test management device, the first signal is sent to the auxiliary test device through a corresponding port of the CPU main board to be tested, the auxiliary test device detects the change of the signal, and a test result is generated; or the auxiliary testing device forwards the first signal to a CPU main board to be tested, and the CPU main board to be tested detects the signal change and generates a testing result; transmitting a test command to the CPU main board to be tested, after the CPU main board to be tested receives the test command, interacting with the auxiliary test device through the backboard bus, and enabling the auxiliary test device to enter a corresponding test mode;
(2) The auxiliary testing device sends the testing result to the CPU main board to be tested through the backboard bus, the CPU main board to be tested sends the testing result to the first network port of the testing management device through the first network port of the CPU main board to be tested, and the testing management device feeds back the testing result to the upper computer through the first communication interface of the testing management device.
Further, the first signal includes an expansion in signal, an expansion out signal, a keyboard, a liquid crystal, an expansion bus, and an I/O signal.
Further, the backplane bus function is tested prior to testing the CPU motherboard performance.
The beneficial effects of the invention are as follows:
the invention provides a CPU main board performance detection system, which comprises an upper computer, a test management device and an auxiliary test device, wherein the upper computer is connected with the test management device, the test management device is used for being connected with a CPU main board to be tested, and the FPGA auxiliary module is used for being connected with the main board to be tested through a backboard bus; the upper computer is used for sending a performance test command sent by the CPU main board; the test management device is used for receiving the test instruction sent by the upper computer, forwarding the test instruction to the CPU main board to be tested, receiving the test result of the CPU main board, and forwarding the test result by the upper computer. The invention realizes the automatic test of the hardware functional module of the CPU board card, improves the detection efficiency and the accuracy of the detection result, saves the cost of manpower and material resources, reduces the artificial error in the test process, and greatly shortens the production and debugging period of the product.
Drawings
FIG. 1 is a schematic diagram of a test principle of auxiliary hardware functional modules of a CPU motherboard;
FIG. 2 is a schematic diagram of the CPU motherboard self-test hardware functional test principle;
FIG. 3 is a block diagram of an FPGA auxiliary test module;
fig. 4 is a schematic diagram of a testing principle of a backplane lead-type hardware functional module.
Detailed Description
The following describes the embodiments of the present invention further with reference to the accompanying drawings:
a relay protection CPU main board performance detection system, as shown in figure 4, comprises an upper computer, a test management device and an auxiliary test device; the test management device comprises a first communication interface P1, a first network port P2 and a first serial port S1; the test management device is connected with the upper computer through a first communication interface P1; the test management device is used for connecting with a first network port E1 of the CPU main board to be tested through a first network port P2 of the test management device; the auxiliary testing device comprises a front terminal C1 and a back board terminal, the front terminal C1 of the auxiliary testing device is connected with a first serial port S1 of the testing management device, the back board terminal of the auxiliary testing device is connected with a corresponding port T1 of the CPU main board to be tested through a back board (connecting line), and the auxiliary testing device is used for being in communication connection with the CPU main board to be tested through a back board bus. The network ports in this embodiment are all ethernet ports, and as other embodiments, other network ports may be used.
The auxiliary test device is an FPGA auxiliary test board, the FPGA is a core component, and the FPGA auxiliary test board mainly comprises an FPGA programmable logic device, a level conversion circuit, an Ethernet port switching circuit, a DA conversion module and the like. As shown in fig. 3, all the back-plate terminal leads of the board under test are all transferred to the FPGA auxiliary test board via the back-plate. And the tested board realizes information interaction with the FPGA auxiliary test board through a bus on the backboard terminal. The FPGA programmable logic device generates a test result by detecting a level reference signal on a corresponding backboard lead and feeds the test result back to the board to be tested; or actively outputting a level reference signal to the corresponding backboard lead wire, and reading the level reference signal back by the tested board and generating a test result.
The level conversion circuit converts 24V or 5V level of an outlet of the backboard terminal, a key and the like into a 3.3V level signal, and the signal is connected into the FPGA programmable logic device. The Ethernet port switching circuit switches the CPU board card backboard network port lead wire to the RJ45 terminal on the front panel of the FPGA auxiliary test board, so that the use is convenient. The DA conversion module mainly comprises a microcontroller and a DC conversion chip, receives a data packet sent by a serial port S1 of the test management device through a serial port C1 of the front terminal, and selects and outputs voltage or current analog quantity through a corresponding channel.
The main functions of the test management device include: receiving a test command sent by an upper computer and forwarding the test command to a tested board; and receiving the test result of the back test board and forwarding the test result to the upper computer.
The detection of the performance of the CPU board card of the relay protection device mainly comprises the detection of the functions of the back board lead type hardware, and the back board lead type hardware functional modules comprise expansion in/out, AD sampling, a keyboard, liquid crystal, an expansion bus, IO signals and the like. The module signals are connected to the FPGA auxiliary test board through the backboard terminals, and the function and performance test evaluation of the module signals are realized under the assistance of the FPGA auxiliary test board.
The CPU board card interacts with the FPGA auxiliary test board through the backboard bus, and the lead signal direction of the backboard of the CPU board card is the signal input direction because the lead signal direction of the backboard of the different hardware modules to be tested is different, and the test implementation is different, for example, the lead signal direction of the backboard of the CPU board card is the signal input direction; other signals to be detected except digital quantity signals (expansion on/off, AD sampling, keyboard, liquid crystal, expansion bus and IO signals), the lead signal direction of the CPU board and backboard is the signal output direction, and the following specific descriptions are provided:
1. when the lead signal direction of the back plate of the CPU board card is the signal input direction, the method comprises the following steps:
1) The upper computer sends a test instruction through the Ethernet port N1, the test management device receives the test instruction through the first communication interface P1 of the test management device, sends a digital quantity signal for testing to the auxiliary test device through the first serial port S1 of the test management device, and simultaneously sends the digital quantity signal for testing to the CPU main board to be tested through the first network port P2 of the test management device.
2) The auxiliary testing device receives the digital quantity signal through the front terminal C1 and sends the digital quantity signal to the CPU main board to be tested, and the CPU main board to be tested receives the digital quantity signal through the corresponding port T1 of the CPU main board to be tested.
3) The auxiliary testing device is used for carrying out digital-to-analog conversion on the digital quantity signals through the DA conversion module, sending the analog quantity after digital-to-analog conversion to a port T1 of the CPU main board to be tested through a backboard terminal of the auxiliary testing device, carrying out analog-to-digital conversion on the analog quantity by the CPU main board to be tested, comparing the digital quantity after analog-to-digital conversion with the digital quantity signals for testing, which are sent from a first network port of the testing management device to a first network port E1 of the CPU main board to be tested, detecting whether the digital quantity signals are consistent or not by the CPU main board to be tested, and generating a testing result.
4) The CPU main board to be tested sends the test result to the test management device through the first network port E1 of the CPU main board to be tested, the test management device receives the test result through the first network port P2, and the test management device feeds the test result back to the upper computer through the first communication interface P1, so that the function and performance of the CPU main board module to be tested are detected.
2. When the lead signal direction of the back plate of the CPU board card is the signal output direction, the method comprises the following steps:
(1) For example, taking an out signal as an example, the upper computer sends a test instruction through the ethernet port N1, the test management device receives the test instruction through the first communication interface P1 of the test management device, the out test instruction is forwarded to the first network port E1 of the CPU motherboard to be tested through the first network port P2 of the test management device, the out test instruction is sent to the auxiliary test device through the port T1 of the CPU motherboard to be tested, the auxiliary test device detects the change of the signal and generates a test result, the result is temporarily stored in the internal register of the FPGA, and the CPU board to be tested reads the test result through the backplane bus.
(2) The auxiliary testing device sends the testing result to the CPU main board to be tested through the backboard bus, the CPU main board to be tested sends the testing result to the first network port P2 of the testing management device through the first network port E1 of the CPU main board to be tested, and the testing management device feeds back the testing result to the upper computer through the first communication interface P1 of the testing management device.
The design and use of the FPGA auxiliary test board provide convenience for testing the back board lead wire type hardware functional module, the test is completed without a product whole device, and extra test equipment is not required to apply excitation, so that the test cost is saved.
In this embodiment, the detection of the relay protection CPU motherboard detects not only the backplane lead function, but also the relay protection device auxiliary function and the CPU motherboard self-checking function.
A. The auxiliary hardware functional modules of the device comprise an Ethernet port, a universal asynchronous serial port, an optical fiber longitudinal difference, B code time synchronization, startup and the like. The module receives and transmits data or receives data issued by the test management device through the same module on the test management device, so that the function and performance test evaluation of the module is realized.
B. The on-board self-checking hardware functional module comprises temperature measurement, a real-time clock, voltage monitoring, FLASH, RAM and the like. The module has no terminal lead, and the function and performance of the module are tested and evaluated through self-read-write self-checking test.
Here, the test management device may provide a communication interface such as an electrical ethernet port, an optical ethernet port, a universal asynchronous serial port, an optical fiber longitudinal error, and reference control signals such as an optical B code, an electrical B code, and an open.
As shown in fig. 1, 2 and 4, the upper computer and the test management device communicate through network ports N1 and P1, so as to realize the sending of test commands and the feedback of test results; the test management device communicates with the tested CPU board card through the network ports P2 and E1, so that the test command forwarding and the feedback of the test result are realized.
As shown in fig. 1, in the test of the auxiliary hardware functional module of the device, the upper computer firstly sends a test command to the network port P1 of the test management device through the network port N1, and then the test management device forwards the test command to the network port E1 of the CPU board card in the device to be tested through the network port P2, and the CPU board card enters a test mode after receiving the test command. When the module T1 to be tested is a communication interface such as a network port, a serial port and the like, the CPU board card sends a data packet to the T1 port of the test management device through the T1, the test management device receives the data packet and sends the data packet back to the CPU board card, and the CPU board card compares and counts the data packet which is received and sent quantitatively to generate a test result. When the module to be tested T1 is the on or B code, the test management device outputs a reference signal through T1 after receiving the test command, and the CPU board card module to be tested T1 generates a test result by detecting the signal. The CPU board card feeds back the test result to the test management device network port P2 through the network port E1, and finally sends the test result to the upper computer through the test management device network port P1, so that the function and performance test evaluation of the module is realized.
As shown in fig. 2, in the test of the on-board self-checking hardware functional module, the communication between the upper computer and the test management device is identical to the auxiliary hardware functional module of the device, and the description thereof is omitted herein. After the network port of the CPU board card E1 receives the test command forwarded by the network port of the test management device P2, the hardware module T1 to be tested enters a read-write self-test to generate a test result, the CPU board card feeds the test result back to the network port P2 of the test management device through the network port E1, and finally the test result is sent to an upper computer through the network port P1 of the test management device to realize the function and performance test evaluation of the module.
The invention also provides a method for detecting the performance of the relay protection CPU main board, and the specific implementation of the method is described in detail in the above embodiments, so that the description is omitted here. The invention divides the CPU board card hardware functional module into three major categories, and respectively adopts different testing methods according to various characteristics, and particularly designs the FPGA auxiliary testing board aiming at the backboard lead wire type hardware module, thereby realizing the automatic test of the CPU board card hardware functional module, avoiding manual intervention in the testing process, realizing the automation of the testing process, effectively avoiding the problems of missing testing items in the manual testing process, quality hidden troubles caused by wrong connection of testing wires and the like, saving the repeated working time consumed by a plurality of testing nodes in the manual testing process, and the like, further saving the labor cost, reducing the maintenance cost, reducing the testing error rate and greatly shortening the production debugging period of the product.
Specific embodiments are given above, but the present invention is not limited to the above-described embodiments. The basic idea of the invention is that the above basic scheme, it is not necessary for a person skilled in the art to design various modified models, formulas, parameters according to the teaching of the invention to take creative effort. Variations, modifications, substitutions and alterations are also possible in the embodiments without departing from the principles and spirit of the present invention.
Claims (1)
1. The detection method of the relay protection CPU main board performance detection system comprises an upper computer, a test management device and an auxiliary test device; the test management device comprises a first communication interface, a first network port and a first serial port; the test management device is connected with the upper computer through the first communication interface; the test management device is used for connecting with a first network port of the CPU main board to be tested through the first network port of the test management device; the auxiliary testing device comprises a front terminal and a back board terminal, the front terminal of the auxiliary testing device is connected with the first serial port of the testing management device, the back board terminal of the auxiliary testing device is connected with a corresponding port of the CPU main board to be tested through a back board connecting line, and the auxiliary testing device is used for being in communication connection with the CPU main board to be tested through a back board bus;
the method is characterized in that the detection method of the relay protection CPU main board performance detection system comprises the following steps:
1) The upper computer sends a test command, the test management device receives the test command through a first communication interface of the test management device, sends a digital quantity signal for testing to the auxiliary test device through a first serial port of the test management device, and simultaneously sends the digital quantity signal for testing to a CPU main board to be tested through a first network port of the test management device;
2) The auxiliary testing device receives the digital quantity signal through a front terminal and sends the digital quantity signal to a CPU main board to be tested, and the CPU main board to be tested receives the digital quantity signal through a corresponding port of the CPU main board to be tested;
3) The auxiliary testing device is used for carrying out digital-to-analog conversion on the digital quantity signals, sending the analog quantity after digital-to-analog conversion to a corresponding port of the CPU main board to be tested through a backboard terminal of the auxiliary testing device, carrying out analog-to-digital conversion on the analog quantity by the CPU main board to be tested, comparing the digital quantity after analog-to-digital conversion with digital quantity signals for testing, which are sent from a first network port of the testing management device to a first network port of the CPU main board to be tested, detecting whether the digital quantity signals are consistent or not, and generating a testing result;
4) The CPU main board to be tested sends the test result to a first network port of the test management device through a first network port of the CPU main board to be tested, and the test management device feeds back the test result to the upper computer through a first communication interface of the test management device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710672439.2A CN109388529B (en) | 2017-08-08 | 2017-08-08 | Relay protection CPU (Central processing Unit) mainboard performance detection method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710672439.2A CN109388529B (en) | 2017-08-08 | 2017-08-08 | Relay protection CPU (Central processing Unit) mainboard performance detection method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109388529A CN109388529A (en) | 2019-02-26 |
| CN109388529B true CN109388529B (en) | 2023-10-20 |
Family
ID=65413804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710672439.2A Active CN109388529B (en) | 2017-08-08 | 2017-08-08 | Relay protection CPU (Central processing Unit) mainboard performance detection method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109388529B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110261761B (en) * | 2019-06-06 | 2024-02-06 | 福建星网智慧科技有限公司 | Mainboard self-checking device and method based on FPGA (field programmable Gate array) electrical signal detection |
| CN111930031B (en) * | 2019-12-26 | 2023-02-14 | 南京南瑞继保电气有限公司 | Relay protection single board debugging system and implementation method thereof |
| CN115389904A (en) * | 2022-07-12 | 2022-11-25 | 浙江众合科技股份有限公司 | Automatic testing system and method for single board of heterogeneous processor in rail transit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138778B1 (en) * | 2005-03-31 | 2012-03-20 | Stephen William Smith | Apparatus for high density low cost automatic test applications |
| CN104253720A (en) * | 2014-09-11 | 2014-12-31 | 烽火通信科技股份有限公司 | Automated test equipment and automated test method for L3 circuit panels |
| CN104468277A (en) * | 2014-12-18 | 2015-03-25 | 国家电网公司 | Consistency testing method and device for transformer substation network and communication protocol |
| CN104572382A (en) * | 2013-10-14 | 2015-04-29 | 昆达电脑科技(昆山)有限公司 | I2C (inter-integrated circuit) bus test jig |
| CN106124888A (en) * | 2016-06-15 | 2016-11-16 | 珠海科众技术有限公司 | The full-automatic adjustment method of a kind of microcomputer protective relay device and system |
| CN106501705A (en) * | 2016-10-26 | 2017-03-15 | 成都交大许继电气有限责任公司 | Traction integrated system protection CPU board automatic checkout system and its detection method |
| CN106909135A (en) * | 2017-02-09 | 2017-06-30 | 许继电气股份有限公司 | A kind of new energy current transformer controls the test device of hardware |
-
2017
- 2017-08-08 CN CN201710672439.2A patent/CN109388529B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138778B1 (en) * | 2005-03-31 | 2012-03-20 | Stephen William Smith | Apparatus for high density low cost automatic test applications |
| CN104572382A (en) * | 2013-10-14 | 2015-04-29 | 昆达电脑科技(昆山)有限公司 | I2C (inter-integrated circuit) bus test jig |
| CN104253720A (en) * | 2014-09-11 | 2014-12-31 | 烽火通信科技股份有限公司 | Automated test equipment and automated test method for L3 circuit panels |
| CN104468277A (en) * | 2014-12-18 | 2015-03-25 | 国家电网公司 | Consistency testing method and device for transformer substation network and communication protocol |
| CN106124888A (en) * | 2016-06-15 | 2016-11-16 | 珠海科众技术有限公司 | The full-automatic adjustment method of a kind of microcomputer protective relay device and system |
| CN106501705A (en) * | 2016-10-26 | 2017-03-15 | 成都交大许继电气有限责任公司 | Traction integrated system protection CPU board automatic checkout system and its detection method |
| CN106909135A (en) * | 2017-02-09 | 2017-06-30 | 许继电气股份有限公司 | A kind of new energy current transformer controls the test device of hardware |
Non-Patent Citations (3)
| Title |
|---|
| 《Three digital closed loops reference generating platform for protective relay testing》;Wenwen Zhou等;《12th IET International Conference on Developments in Power System Protection (DPSP 2014)》;20140731;第1-4页 * |
| 《继电保护装置自动测试系统设计》;王忠等;《电力系统保护与控制》;20150508;第130-135页 * |
| 微机型继电保护测试装置的设计;张粤等;《电力自动化设备》;20120610(第06期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109388529A (en) | 2019-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102092477B (en) | Device and method for automatic test and fault diagnosis of plane audio integrated system | |
| CN104297623B (en) | Automatic test system for onboard cable integrity | |
| CN105404284B (en) | A kind of cross-platform PLC products tooling test system and its test method based on QT | |
| CN109388529B (en) | Relay protection CPU (Central processing Unit) mainboard performance detection method and system | |
| CN103699112B (en) | Based on avionics Autonomous test Authentication devices and the verification method thereof of I/O signal fault simulation | |
| CN101937222A (en) | Board level testing system | |
| CN103019141A (en) | Control module, control method and electric power dynamic recording device and implementation method thereof | |
| CN202339718U (en) | Extendible nuclear power DCS automatic testing device | |
| CN215219508U (en) | A test fixture for machine controller | |
| CN201035741Y (en) | Distributed data acquisition instrument | |
| CN106933215B (en) | PXI bus-based universal equivalent device for external interface of telemetry system | |
| CN202339497U (en) | Verification system of satellite-bone integrated service unit | |
| CN114089649A (en) | Automatic test tool system and method | |
| CN104569697A (en) | Power supply interface detection method for minisatellite comprehensive test | |
| CN209264906U (en) | CVC-200T hardware intelligent test system | |
| CN105182966A (en) | Detection method of PLC and IO extension module | |
| CN203552054U (en) | Test bench based on PEPS system | |
| CN106774262B (en) | The device and its implementation of automatic detection intelligence instrument master control borad hardware performance | |
| CN208351305U (en) | A kind of multi channel signals recorder | |
| CN106372687A (en) | Distribution network automatic detection method and system | |
| CN116908751B (en) | Test board for detecting peripheral interfaces of industrial system, detection system and method | |
| CN208568924U (en) | A kind of electric vehicle rotary parallel operation profession aging testing system | |
| CN113485954B (en) | CAN control unit and ion accelerator power supply controller | |
| CN204442408U (en) | A kind of time message test machine | |
| CN221199923U (en) | Electric energy meter and terminal sorting multiplexing device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |