CN109388529A - A kind of relay protection cpu motherboard method for testing performance and system - Google Patents
A kind of relay protection cpu motherboard method for testing performance and system Download PDFInfo
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- CN109388529A CN109388529A CN201710672439.2A CN201710672439A CN109388529A CN 109388529 A CN109388529 A CN 109388529A CN 201710672439 A CN201710672439 A CN 201710672439A CN 109388529 A CN109388529 A CN 109388529A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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Abstract
The present invention provides a kind of relay protection cpu motherboard method for testing performance and systems; the detection system includes host computer, test and management device, auxiliary test unit; host computer is connect with test and management device; for connecting with cpu motherboard to be measured, FPGA supplementary module is used to connect by core bus with cpu motherboard to be measured test and management device；Host computer is for sending cpu motherboard performance test order；The test instruction that test and management device is used to receive host computer transmission receives cpu motherboard test result, to host computer transmitted test result to cpu motherboard transmitted test order to be measured.The present invention realizes the automatic test of CPU board card hardware function, improves the accuracy rate of detection efficiency and testing result, saves manpower and material resources cost, reduces the mistake in test process, greatly shortens the scheduling and planning period of product.
Description
Technical field
The invention belongs to relay protection of power system and auto-control technical field, in particular to a kind of relay protection
Cpu motherboard method for testing performance and system.
Background technique
In recent years, the development of electric system, it is higher and higher to the reliability requirement of microcomputer protective relay device hardware system,
How to guarantee that the quality of hardware system is our urgent problems, protective relaying device is the main composition portion of electric system
Point, can protective relaying device operate normally the reliability and safety for directly influencing Operation of Electric Systems, CPU board card conduct
The core board of protective relaying device, a whole set of computer system, data acquisition, the input of switching value and output etc. concentrate on this
In one piece of printed board.The correctness of its hardware capability and the quality of performance are directly related to the safety of device operation and reliable
Property.In the relay protection CPU board card scheduling and planning stage, need to test each functional module, functionally carry out verifying and
It is assessed in performance, to meet the requirement of design.Traditional manual testing process is time-consuming and laborious, or even is unable to reach test mesh
, and it is cumbersome, operation is repeated, error is easy；Manual test requires manual intervention, and being easy to miss during the test needs
Project to be tested, causes not perfect to cpu motherboard test function, increases the production test period of product, and increase dimension
Protect cost.
Summary of the invention
The purpose of the present invention is to provide a kind of relay protection cpu motherboard method for testing performance and systems, existing for solving
The problem that detection efficiency is low and testing result is inaccurate when having in technology to cpu motherboard performance detection.
To achieve the above object, the technical scheme is that
A kind of relay protection cpu motherboard performance detecting system, including host computer, test and management device and subtest dress
It sets；The test and management device includes the first communication interface, the first network interface and first serial；Measuring management device passes through described the
One communication interface connects the host computer；Test and management device is used for the first network interface and CPU to be measured by test and management device
First network interface connection of mainboard；The auxiliary test unit includes front terminal and backboard terminal, the front terminal of auxiliary test unit
It is connect with the first serial of the test and management device, the backboard terminal of auxiliary test unit passes through backboard line and CPU to be measured
The connection of mainboard corresponding port, the auxiliary test unit are used for through core bus and cpu motherboard communication connection to be measured.
Further, the auxiliary test unit further includes D/A conversion module, the D/A conversion module and the auxiliary
The backboard terminal of test device connects.
Further, the first network interface of the first communication interface of the test and management device and test and management device is ether
Network interface.
Further, the auxiliary test unit includes FPGA.
The present invention also provides a kind of detection methods for implementing the relay protection cpu motherboard performance detecting system, including
Following steps:
1) host computer sends test instruction, and test and management device receives institute by the first communication interface of test and management device
Test command is stated, the digital quantity signal for test is sent to auxiliary test unit by the first serial of test and management device,
Send the digital quantity signal for test to cpu motherboard to be measured by the first network interface of test and management device simultaneously；
2) auxiliary test unit receives the digital quantity signal by front terminal, and is sent to cpu motherboard to be measured, to be measured
Cpu motherboard receives the digital quantity signal by the corresponding port of cpu motherboard to be measured；
3) auxiliary test unit is used to the digital quantity signal carrying out digital-to-analogue conversion, by the simulation after digital-to-analogue conversion
Amount is sent to the corresponding port of cpu motherboard to be measured by the backboard terminal of auxiliary test unit, by cpu motherboard to be measured to the mould
Analog quantity carries out analog-to-digital conversion, by the first network interface of digital quantity and test and management device after analog-to-digital conversion to cpu motherboard to be measured
The digital quantity signal for test that first network interface is sent is compared, and whether detection digital quantity signal is consistent, and generates test
As a result；
4) test result is sent to test and management dress by the first network interface of cpu motherboard to be measured by cpu motherboard to be measured
The first network interface set, test and management device are fed back to the test result by the first communication interface of test and management device
Position machine.
The present invention also provides a kind of detection methods for implementing the relay protection cpu motherboard performance detecting system, including
Following steps:
(1) host computer sends test instruction, and test and management device is received by the first communication interface of test and management device
The test instruction, is sent to the first network interface of cpu motherboard to be measured for test by the first network interface of test and management device
First signal, first signal are sent to auxiliary test unit by the corresponding port of cpu motherboard to be measured, are filled by subtest
The variation of detection signal is set, and generates test result；Or auxiliary test unit first signal is sent to it is to be measured
Cpu motherboard, cpu motherboard change in detection signal to be measured, and generate test result；It is to be measured to cpu motherboard transmitted test order to be measured
It after cpu motherboard receives test command, is interacted by core bus and auxiliary test unit, auxiliary test unit enters phase
Answer test pattern；
(2) test result is sent to cpu motherboard to be measured, CPU master to be measured by core bus by auxiliary test unit
The test result is sent to the first network interface of test and management device, testing tube by plate by the first network interface of cpu motherboard to be measured
It manages device and the test result is fed back to by host computer by the first communication interface of test and management device.
Further, first signal includes spreading into signal, outputing signal, keyboard, liquid crystal, expansion bus and I/
O signal.
Further, core bus function is detected before to cpu motherboard performance detection.
The beneficial effects of the present invention are:
Cpu motherboard performance detecting system provided by the invention, including host computer, test and management device, auxiliary test unit,
Host computer is connect with the test and management device, and test and management device for connecting with cpu motherboard to be measured, use by FPGA supplementary module
It is connect in passing through core bus with mainboard to be measured；Host computer is for sending cpu motherboard sending performance test command；Test and management dress
It sets the test instruction for receiving host computer transmission and receives cpu motherboard test result to cpu motherboard transmitted test order to be measured,
And host computer transmitted test result.The present invention realizes the automatic test of CPU board card hardware function, improves detection efficiency
With the accuracy rate of testing result, manpower and material resources cost is saved, the mistake in test process is reduced, greatly shortens product
The scheduling and planning period.
Detailed description of the invention
Fig. 1 is cpu motherboard assisted class hardware function test philosophy schematic diagram；
Fig. 2 is cpu motherboard self-test class hardware capability test philosophy schematic diagram；
Fig. 3 is FPGA subtest module composition block diagram；
Fig. 4 is backboard lead class hardware function test philosophy schematic diagram.
Specific embodiment
A specific embodiment of the invention is further described with reference to the accompanying drawing:
A kind of relay protection cpu motherboard performance detecting system, as shown in figure 4, including host computer, test and management device and auxiliary
Help test device；Test and management device includes the first communication interface P1, the first network interface P2 and first serial S1；Test and management device
Pass through the first communication interface P1 connection host computer；Test and management device be used for by the first network interface P2 of test and management device with to
Survey the first network interface E1 connection of cpu motherboard；Auxiliary test unit includes front terminal C1 and backboard terminal, before auxiliary test unit
Terminal C1 is connect with the first serial S1 of test and management device, the backboard terminal of auxiliary test unit by backboard (line) with to
Cpu motherboard corresponding port T1 connection is surveyed, auxiliary test unit is used for through core bus and cpu motherboard communication connection to be measured.This
The network interface of embodiment is all Ethernet interface, can also be using other network interfaces as other embodiments.
Auxiliary test unit is FPGA subtest plate, and FPGA is core component, and FPGA subtest plate is mainly by FPGA
The composition such as programmable logic device, level shifting circuit, Ethernet interface built-up circuit and D/A conversion module.As shown in figure 3, tested
All backboard terminal leads of plate are all forwarded to FPGA subtest plate through backboard.Board Under Test by bus on backboard terminal with
FPGA subtest plate realizes information exchange.FPGA programmable logic device is by detecting level reference letter on corresponding backboard lead
Number, it generates test result and feeds back to Board Under Test；Or corresponding backboard lead output level reference signal is actively given, it is returned by Board Under Test
It reads the level reference signal and generates test result.
Wherein, 24V the or 5V level conversion of the outlet of backboard terminal, key etc. is 3.3V level letter by level shifting circuit
Number access FPGA programmable logic device.CPU board card backboard network interface lead is transferred to FPGA auxiliary by Ethernet interface built-up circuit
RJ45 terminal on test board front panel is easy to use.D/A conversion module is mainly made of microcontroller and DC conversion chip, is led to
The serial ports C1 for crossing front terminal receives the data packet that test and management device serial ports S1 is sent, and selects and passes through respective channel output voltage
Or current-mode analog quantity.
Test and management device major function includes: to receive host computer to send test command, to Board Under Test transmitted test order；
Back drafting board test result is received, and to host computer transmitted test result.
The present embodiment includes mainly to backboard lead class hardware capability to the detection of protective relaying device CPU board card performance
Detection, backboard lead class hardware function include spread into, output, AD sampling, keyboard, liquid crystal, expansion bus, I/O signal
Deng.Such module by signal is connected to FPGA subtest plate through backboard terminal, the realization pair under the assistance of FPGA subtest plate
Its function and performance test assessment.
CPU board card is realized by core bus and is interacted with FPGA subtest plate, due to different hardware module to be tested
The direction of backboard lead signal is different, will be different in test realization, such as the digital quantity signal for AD sampling, CPU board card
Backboard lead signal direction is the direction of signal input；In addition to digital quantity signal (spread into, output, AD sampling, keyboard, liquid
Crystalline substance, expansion bus, I/O signal) other signals to be detected, CPU board card backboard lead signal direction be signal output side
To illustrating separately below:
1, when CPU board card backboard lead signal direction is the direction of signal input, comprising the following steps:
1) host computer sends test instruction by Ethernet interface N1, and test and management device passes through the first of test and management device
Communication interface P1 receives test command, is sent to auxiliary test unit for testing by the first serial S1 of test and management device
Digital quantity signal, while sending to cpu motherboard to be measured by the first network interface P2 of test and management device the number for test
Measure signal.
2) auxiliary test unit receives digital quantity signal by front terminal C1, and is sent to cpu motherboard to be measured, CPU to be measured
Mainboard receives digital quantity signal by the corresponding port T1 of cpu motherboard to be measured.
3) auxiliary test unit is used to digital quantity signal carrying out digital-to-analogue conversion by D/A conversion module, after digital-to-analogue conversion
Analog quantity the port T1 of cpu motherboard to be measured is sent to by the backboard terminal of auxiliary test unit, by cpu motherboard to be measured to upper
It states analog quantity and carries out analog-to-digital conversion, by the first network interface of digital quantity and test and management device after analog-to-digital conversion to CPU master to be measured
The digital quantity signal for test that first network interface E1 of plate is sent is compared, and cpu motherboard detection digital quantity signal to be measured is
It is no consistent, and generate test result.
4) test result is sent to test and management device by the first network interface E1 of cpu motherboard to be measured by cpu motherboard to be measured,
Test and management device receives test result by the first network interface P2, and test and management device will pass through the first communication interface P1 again to be surveyed
Test result feeds back to host computer, realizes the detection to cpu motherboard functions of modules to be measured and performance.
2, when CPU board card backboard lead signal direction is the direction of signal output, comprising the following steps:
(1) for example for outputing signal, host computer sends test instruction by Ethernet interface N1, and test and management device is logical
The the first communication interface P1 for crossing test and management device receives test instruction, by the first network interface P2 of test and management device to be measured
Test command is outputed in the first network interface E1 forwarding of cpu motherboard, is outputed test command and is sent to by the port T1 of cpu motherboard to be measured
Auxiliary test unit by the variation of auxiliary test unit detection signal, and generates test result, and result is kept in FPGA
In portion's register, CPU board card to be measured passes through core bus read test result.
(2) test result is sent to cpu motherboard to be measured by core bus by auxiliary test unit, and cpu motherboard to be measured will
Test result is sent to the first network interface P2 of test and management device, test and management dress by the first network interface E1 of cpu motherboard to be measured
It sets and test result is fed back to by host computer by the first communication interface P1 of test and management device.
The design of above-mentioned FPGA subtest plate is provided convenience using the test for being backboard lead class hardware function,
Do not need to complete to test by product engagement positions, and do not need additional test equipment and apply excitation, saved test at
This.
The present embodiment to the detection of relay protection cpu motherboard other than being detected to backboard lead function, also to relay
Protective device miscellaneous function and cpu motherboard self-checking function are detected.
A. device assisted class hardware function includes Ethernet interface, universal asynchronous serial, optical-fiber longitudinal difference, B code clock synchronization, opens
Enter.The generic module is issued by carrying out sending and receiving data with the uniformity module on test and management device or receiving test and management device
Data, realize and its function and performance test assessed.
B. self-test class hardware function includes thermometric, real-time clock, voltage monitoring, FLASH, RAM etc. on plate.Such mould
Block does not have terminal lead, is realized by itself read-write self-checking and is assessed its function and performance test.
Herein, test and management device can provide electric Ethernet interface, luminiferous ether network interface, universal asynchronous serial, optical-fiber longitudinal difference
Etc. communication interfaces and light B code, electricity B code, output etc. with reference to control signal.
It as shown in Fig. 1,2,4, is communicated between host computer and test and management device by network interface N1 and P1, realizes test
The transmission of order and the feedback of test result；It is communicated between test and management device and tested CPU board card by network interface P2 and E1,
Realize the feedback of test command forwarding and test result.
As shown in Figure 1, host computer passes through network interface N1 to test and management first in the test of device assisted class hardware function
Device network interface P1 sends test command, and test and management device passes through network interface P2 again and test command is transmitted to CPU in tested device
The network interface E1 of board, CPU board clamping enter test pattern after receiving test command.When module T1 to be measured is that network interface, serial ports etc. are logical
When believing interface, CPU board card sends data packet to the t1 port of test and management device by T1, and test and management device receives data
Packet is compared statistics to the data packet of quantitative transmitting-receiving back to CPU board card, CPU board card, generates test result.When module to be measured
T1 be open into or when B code, test and management device passes through T1 output reference signal, CPU board card mould to be measured after receiving test command
Block T1 generates test result by detecting the signal.Test result is fed back to test and management device by network interface E1 by CPU board card
Network interface P2 is sent to host computer eventually by test and management device network interface P1, realizes and assess the functions of modules and performance test.
As shown in Fig. 2, on plate in the test of self-test class hardware function, the communication between host computer and test and management device
With device assisted class hardware function, do not repeat them here herein.When CPU board card E1 network interface receives test and management device P2 net
After the test command of mouth forwarding, hardware module T1 to be measured enters read-write self-checking, generates test result, and CPU board card will be tested
As a result test and management device network interface P2 is fed back to by network interface E1, is sent to eventually by test and management device network interface P1 upper
Machine is realized and is assessed the functions of modules and performance test.
The present invention also provides a kind of relay protection cpu motherboard method for testing performance, and the specific embodiment of this method is
It is described in detail, therefore, is repeated no more herein in the above-described embodiments.The present invention is by above-mentioned CPU board card hardware
Functional module is divided into three categories, and according to all kinds of features, different test methods is respectively adopted, especially for backboard lead class
Hardware module development FPGA subtest plate, realizes the automatic test of CPU board card hardware function, test process is not necessarily to
The problem of manual intervention realizes the automation of test process, effectively prevents test leakage test item during manual testing, mistake
Hidden danger of quality caused by p-wire etc. is connect, the repeated work time spent by multiple test nodes during saving manual testing
Deng, to save human cost, maintenance cost is reduced, reduces and tests error rate, the very big scheduling and planning period for shortening product.
Specific embodiment is presented above, but the present invention is not limited to embodiment described above.The present invention
Basic ideas be above-mentioned basic scheme, for those of ordinary skill in the art, introduction according to the present invention is designed each
The model of kind deformation, formula, parameter do not need to spend creative work.The case where not departing from the principle and spirit of the invention
Under to embodiment carry out change, modification, replacement and modification still fall in protection scope of the present invention.
Claims (8)
1. a kind of relay protection cpu motherboard performance detecting system, which is characterized in that including host computer, test and management device and auxiliary
Help test device；The test and management device includes the first communication interface, the first network interface and first serial；Measuring management device is logical
It crosses first communication interface and connects the host computer；Test and management device be used for by the first network interface of test and management device with
First network interface connection of cpu motherboard to be measured；The auxiliary test unit includes front terminal and backboard terminal, auxiliary test unit
Front terminal is connect with the first serial of the test and management device, the backboard terminal of auxiliary test unit by backboard line with to
The connection of cpu motherboard corresponding port is surveyed, the auxiliary test unit is used for through core bus and cpu motherboard communication connection to be measured.
2. relay protection cpu motherboard performance detecting system according to claim 1, which is characterized in that the subtest
Device further includes D/A conversion module, and the D/A conversion module is connect with the backboard terminal of the auxiliary test unit.
3. relay protection cpu motherboard performance detecting system according to claim 1, which is characterized in that the test and management
First communication interface of device and the first network interface of test and management device are Ethernet interface.
4. relay protection cpu motherboard performance detecting system according to claim 1-3, which is characterized in that described
Auxiliary test unit includes FPGA.
5. a kind of detection method for implementing relay protection cpu motherboard performance detecting system as described in claim 1, feature exist
In including the following steps:
1) host computer sends test instruction, and test and management device receives the survey by the first communication interface of test and management device
Examination order sends the digital quantity signal for test to auxiliary test unit by the first serial of test and management device, simultaneously
The digital quantity signal for being used for test is sent to cpu motherboard to be measured by the first network interface of test and management device；
2) auxiliary test unit receives the digital quantity signal by front terminal, and is sent to cpu motherboard to be measured, CPU master to be measured
Plate receives the digital quantity signal by the corresponding port of cpu motherboard to be measured；
3) auxiliary test unit is used to the digital quantity signal carrying out digital-to-analogue conversion, and the analog quantity after digital-to-analogue conversion is led to
The backboard terminal for crossing auxiliary test unit is sent to the corresponding port of cpu motherboard to be measured, by cpu motherboard to be measured to the analog quantity
Analog-to-digital conversion is carried out, by the first network interface of digital quantity and test and management device after analog-to-digital conversion to the first of cpu motherboard to be measured
The digital quantity signal for test that network interface is sent is compared, and whether detection digital quantity signal is consistent, and generates test result；
4) test result is sent to test and management device by the first network interface of cpu motherboard to be measured by cpu motherboard to be measured
First network interface, test and management device are fed back to the test result by the first communication interface of test and management device upper
Machine.
6. a kind of detection method for implementing relay protection cpu motherboard performance detecting system as described in claim 1, feature exist
In including the following steps:
(1) host computer sends test instruction, and test and management device passes through described in the first communication interface reception of test and management device
Test instruction is sent to the first network interface of cpu motherboard to be measured by the first network interface of test and management device and is used for the first of test
Signal, first signal are sent to auxiliary test unit by the corresponding port of cpu motherboard to be measured, are examined by auxiliary test unit
The variation of signal is surveyed, and generates test result；Or first signal is sent to CPU master to be measured by auxiliary test unit
Plate, cpu motherboard change in detection signal to be measured, and generate test result；To cpu motherboard transmitted test order to be measured, CPU master to be measured
It after plate receives test command, is interacted by core bus and auxiliary test unit, auxiliary test unit enters corresponding survey
Die trial formula；
(2) test result is sent to cpu motherboard to be measured by core bus by auxiliary test unit, and cpu motherboard to be measured will
The test result is sent to the first network interface of test and management device, test and management dress by the first network interface of cpu motherboard to be measured
It sets and the test result is fed back to by host computer by the first communication interface of test and management device.
7. detection method according to claim 6, which is characterized in that first signal includes spreading into signal, opening
Signal, keyboard, liquid crystal, expansion bus and I/O signal out.
8. detection method according to claim 6, which is characterized in that total to backboard before to cpu motherboard performance detection
Line function is detected.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110261761A (en) * | 2019-06-06 | 2019-09-20 | 福建星网智慧科技股份有限公司 | A kind of mainboard self-checking unit and method based on the detection of FPGA electric signal |
| CN111930031A (en) * | 2019-12-26 | 2020-11-13 | 南京南瑞继保电气有限公司 | Relay protection single board debugging system and implementation method thereof |
| CN115389904A (en) * | 2022-07-12 | 2022-11-25 | 浙江众合科技股份有限公司 | Automatic testing system and method for single board of heterogeneous processor in rail transit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138778B1 (en) * | 2005-03-31 | 2012-03-20 | Stephen William Smith | Apparatus for high density low cost automatic test applications |
| CN104253720A (en) * | 2014-09-11 | 2014-12-31 | 烽火通信科技股份有限公司 | Automated test equipment and automated test method for L3 circuit panels |
| CN104468277A (en) * | 2014-12-18 | 2015-03-25 | 国家电网公司 | Consistency testing method and device for transformer substation network and communication protocol |
| CN104572382A (en) * | 2013-10-14 | 2015-04-29 | 昆达电脑科技(昆山)有限公司 | I2C (inter-integrated circuit) bus test jig |
| CN106124888A (en) * | 2016-06-15 | 2016-11-16 | 珠海科众技术有限公司 | The full-automatic adjustment method of a kind of microcomputer protective relay device and system |
| CN106501705A (en) * | 2016-10-26 | 2017-03-15 | 成都交大许继电气有限责任公司 | Traction integrated system protection CPU board automatic checkout system and its detection method |
| CN106909135A (en) * | 2017-02-09 | 2017-06-30 | 许继电气股份有限公司 | A kind of new energy current transformer controls the test device of hardware |
-
2017
- 2017-08-08 CN CN201710672439.2A patent/CN109388529B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8138778B1 (en) * | 2005-03-31 | 2012-03-20 | Stephen William Smith | Apparatus for high density low cost automatic test applications |
| CN104572382A (en) * | 2013-10-14 | 2015-04-29 | 昆达电脑科技(昆山)有限公司 | I2C (inter-integrated circuit) bus test jig |
| CN104253720A (en) * | 2014-09-11 | 2014-12-31 | 烽火通信科技股份有限公司 | Automated test equipment and automated test method for L3 circuit panels |
| CN104468277A (en) * | 2014-12-18 | 2015-03-25 | 国家电网公司 | Consistency testing method and device for transformer substation network and communication protocol |
| CN106124888A (en) * | 2016-06-15 | 2016-11-16 | 珠海科众技术有限公司 | The full-automatic adjustment method of a kind of microcomputer protective relay device and system |
| CN106501705A (en) * | 2016-10-26 | 2017-03-15 | 成都交大许继电气有限责任公司 | Traction integrated system protection CPU board automatic checkout system and its detection method |
| CN106909135A (en) * | 2017-02-09 | 2017-06-30 | 许继电气股份有限公司 | A kind of new energy current transformer controls the test device of hardware |
Non-Patent Citations (3)
| Title |
|---|
| WENWEN ZHOU等: "《Three digital closed loops reference generating platform for protective relay testing》", 《12TH IET INTERNATIONAL CONFERENCE ON DEVELOPMENTS IN POWER SYSTEM PROTECTION (DPSP 2014)》 * |
| 张粤等: "微机型继电保护测试装置的设计", 《电力自动化设备》 * |
| 王忠等: "《继电保护装置自动测试系统设计》", 《电力系统保护与控制》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110261761A (en) * | 2019-06-06 | 2019-09-20 | 福建星网智慧科技股份有限公司 | A kind of mainboard self-checking unit and method based on the detection of FPGA electric signal |
| CN110261761B (en) * | 2019-06-06 | 2024-02-06 | 福建星网智慧科技有限公司 | Mainboard self-checking device and method based on FPGA (field programmable Gate array) electrical signal detection |
| CN111930031A (en) * | 2019-12-26 | 2020-11-13 | 南京南瑞继保电气有限公司 | Relay protection single board debugging system and implementation method thereof |
| CN111930031B (en) * | 2019-12-26 | 2023-02-14 | 南京南瑞继保电气有限公司 | Relay protection single board debugging system and implementation method thereof |
| CN115389904A (en) * | 2022-07-12 | 2022-11-25 | 浙江众合科技股份有限公司 | Automatic testing system and method for single board of heterogeneous processor in rail transit |
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| CN109388529B (en) | 2023-10-20 |
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