CN110867457A - Array substrate with high-capacitance structure and manufacturing method - Google Patents

Abstract

The invention discloses an array substrate with a high-capacitance structure and a manufacturing method thereof, wherein the method comprises the following steps: manufacturing a buffer layer on the array substrate; making holes on the buffer layer; manufacturing a first electrode in the hole; manufacturing a first electrode insulating layer covering the first electrode in the hole; manufacturing a second electrode on the first electrode insulating layer in the hole, and manufacturing a second electrode insulating layer covering the second electrode in the hole; manufacturing a third electrode on the second insulating layer in the hole; a thin film field effect transistor is also arranged on the buffer layer outside the hole; the thin film field effect transistor with the high-capacitance structure is manufactured, a circuit driven by the high-capacitance structure has a better voltage stabilizing effect, the capacitance value of the storage capacitor can be increased, the occupied area of the capacitor is reduced, and the advantages of improving the pixel density (ppi) of the panel and reducing the size of a frame of the panel are also achieved.

Description

Array substrate with high capacitance structure and manufacturing method

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate with a high capacitance structure and a manufacturing method.

Background technique

The rapid development in Active Matrix Organic Light Emitting Diode Displays (AMOLEDs) and High Performance Active Matrix Liquid Crystal Displays (AMLCDs) deserves many high resolution and high frame rate displays. In order to make the driving circuit in the array substrate have a better voltage regulation effect, it is usually necessary to set a large-capacity capacitor. However, the large-capacity capacitor causes the driving circuit to occupy a large area, so that the frame size and pixel size of the display panel cannot be further reduced. Therefore, how to design and fabricate high-performance and small-sized array substrate structures has become a research topic that needs to be overcome more and more.

IGZO (indium gallium zinc oxide) is indium gallium zinc oxide, which is an amorphous oxide containing indium, gallium and zinc. The carrier mobility is 20 to 30 times that of amorphous silicon, which can greatly improve the TFT to the pixel electrode. The higher the charging and discharging rate, the higher the pixel response speed, the faster the panel refresh rate, and the ultra-high-resolution display panel. At the same time, the existing amorphous silicon production line can be compatible with the IGZO process with only minor modifications, so lower temperature polysilicon (LTPS) is more competitive in terms of cost.

SUMMARY OF THE INVENTION

Therefore, it is necessary to provide an array substrate with a high capacitance structure and a manufacturing method, so as to solve the problem of an excessively large area when a display device is equipped with a high capacitance.

In order to achieve the above purpose, the inventor provides a method for fabricating an array substrate with a high capacitance structure, including the following steps:

making a buffer layer on the array substrate;

make holes in the buffer layer;

depositing a first layer of metal, forming a first electrode in the hole, and the first electrode is used as the electrode plate of the lower capacitor structure;

After covering the first insulating layer, continue to deposit a second layer of metal, forming a first electrode insulating layer covering the first electrode in the hole, forming a second electrode on the first electrode insulating layer in the hole, and the second electrode as the upper and lower layers Common plate of capacitor structure;

covering the second insulating layer, and forming a second electrode insulating layer covering the second electrode in the hole;

depositing a third layer of metal, forming a third electrode on the second insulating layer in the hole, and the third electrode is used as a pole plate of the upper capacitor structure;

A thin film field effect transistor is also arranged on the buffer layer outside the hole.

Further, it also includes the following steps:

When depositing the first layer of metal, extend the first electrode in the hole to the surface of the buffer layer; or: after covering the first insulating layer and continue to deposit the second layer of metal, extend the second electrode in the hole to the surface of the first layer of metal. The electrode insulating layer is to the surface of the buffer layer outside the hole; or: when covering the second insulating layer, the second electrode insulating layer in the hole is extended to the surface of the buffer layer outside the hole: or: when the third layer of metal is deposited, extending the third electrode in the hole to the surface of the buffer layer outside the hole; or: connecting the third electrode on the surface of the buffer layer outside the hole and the first electrode on the surface of the buffer layer outside the hole.

Further, the manufacturing steps of the thin film field effect transistor are:

After depositing the first layer of metal, continue to deposit gate metal, and form the first metal and the gate scan line on the buffer layer outside the hole, the first metal is on the buffer layer outside the hole, and the gate scan line is on the first metal superior;

After covering the first insulating layer, continue to deposit a second layer of metal to form a gate insulating layer on the gate scanning line, the gate insulating layer covers and wraps the gate scanning line and the first metal, and forms on the gate insulating layer the second metal;

forming a barrier layer on the second metal while covering the second insulating layer;

When depositing the third layer of metal, a third metal wrapping the second metal and both sides of the barrier layer is formed on the barrier layer, and the third metal exposes a central portion of the barrier layer;

A fourth layer of metal is deposited, a source signal line is formed on one side of the third metal, and a drain is formed on the other side of the third metal.

Further, when depositing the gate metal after depositing the first layer of metal, the following steps are also included:

Coat the photoresist on the gate metal, pattern the photoresist with a half-color mask with semi-transparent area, fully-transparent area, and fully-shielded area, and the semi-transparent area after developing the photoresist is not completely corresponding The developing area, the fully transparent area or the fully shading area corresponds to the fully developed area, the incompletely developed area corresponds to the area of the first electrode in the capacitor structure, and the fully developed area corresponds to the area of the gate scanning line;

Using the photoresist as a mask to etch the gate metal and the first layer of metal on the areas other than the fully developed area and the incompletely developed area;

Remove the photoresist on the first layer of metal in the incompletely developed area by ashing treatment, and retain the photoresist on the gate metal in the fully developed area;

The gate metal in the incompletely developed area is etched to the first layer of metal, the first layer of metal is retained as the first electrode, and the photoresist on the fully developed area is removed to form the first metal and the gate scan line.

Further, after covering the first insulating layer, when continuing to deposit the second layer of metal, the following steps are also included:

Coat photoresist on the second layer of metal, pattern the photoresist with a half-color mask with semi-transparent area, fully-transparent area and fully-shielded area. The fully developed area, the fully transparent area or the fully shading area corresponds to the fully developed area, the incompletely developed area corresponds to the area of the second electrode area in the capacitor structure, and the fully developed area corresponds to the area of the second metal;

Etch the second layer of metal in the incompletely developed area and areas other than the fully developed area, remove the photoresist on the second layer of metal in the incompletely developed area by ashing treatment, and then implant hydrogen ions to remove the first layer of metal in the fully developed area. A photoresist on an insulating layer material, the second metal layer and the first insulating layer in the incompletely developed area are reserved as the second electrode and the first electrode insulating layer, respectively, and the second layer of metal and the first insulating layer in the fully developed area are reserved. as the second metal and gate insulating layer, respectively.

Further, also include the following steps:

Covering the material of the third insulating layer, a passivation layer is formed on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, and the passivation layer protects the capacitor structure and the thin film field effect transistor.

Further, the material of the first layer metal is indium tin oxide.

The present invention provides an array substrate with a high-capacitance structure, characterized in that the array substrate with a high-capacitance structure is prepared by any one of the methods for fabricating an array substrate with a high-capacitance structure described above.

The present invention provides an array substrate with a high capacitance structure, comprising:

A buffer layer is arranged on the array substrate, a hole is arranged on the buffer layer, and a thin film field effect transistor is arranged on the buffer layer outside the hole;

A first electrode, a first electrode insulating layer, a second electrode, a second electrode insulating layer and a third electrode are sequentially arranged in the hole and on the surface of the buffer layer between the holes, and the first electrode serves as the electrode of the lower capacitor structure. plate, the first electrode insulating layer covers the first electrode and serves as the dielectric layer of the lower capacitor structure, the second electrode is on the first electrode insulating layer and serves as the common plate of the upper and lower capacitor structures, and the second electrode insulating layer covers the second electrode And as the dielectric layer of the upper capacitor structure, the third electrode is on the second electrode insulating layer and serves as the electrode plate of the upper capacitor structure.

Further, the thin film field effect transistor includes:

A first metal is arranged on the buffer layer outside the hole, and a gate scan line is arranged on the first metal;

A gate insulating layer is provided on the gate scanning line, and the gate insulating layer covers and wraps the gate scanning line and the first metal;

A second metal is arranged on the gate insulating layer, and a barrier layer is arranged on the second metal;

A third metal is arranged on the barrier layer, the third metal wraps the second metal and both sides of the barrier layer, the third metal exposes the central part of the barrier layer, and a source signal line is arranged on one side of the third metal, A drain is provided on the other side of the third metal.

Different from the prior art, the above technical scheme produces a thin film field effect transistor with a high capacitance structure, and the circuit driven by the high capacitance structure has a better voltage regulation effect, which can increase the capacitance of the storage capacitor and reduce the occupied area of the capacitor. , also has the advantage of increasing the pixel density (ppi) of the panel and reducing the size of the panel bezel.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of fabricating a buffer layer and a hole on an array substrate according to the present invention;

FIG. 2 is a process flow diagram of fabricating a first electrode, a first metal and a gate scan line on an array substrate according to the present invention;

FIG. 3 is a process flow diagram of fabricating a first electrode insulating layer, a gate insulating layer, a second electrode and a second metal on an array substrate according to the present invention;

FIG. 4 is a schematic cross-sectional structural diagram of fabricating a second electrode insulating layer and a barrier layer on an array substrate according to the present invention;

5 is a schematic cross-sectional structure diagram of a thin film field effect transistor according to another embodiment of the present invention;

6 is a schematic cross-sectional structural diagram of fabricating a third electrode, a third metal, a source signal line and a drain on the array substrate according to the present invention;

FIG. 7 is a schematic cross-sectional structure diagram of a passivation layer fabricated on an array substrate according to the present invention;

FIG. 8 is a schematic structural diagram of the grid capacitor structure in parallel according to the present invention;

FIG. 9 is a schematic cross-sectional structural diagram of the gate capacitor structure according to the present invention.

Description of reference numbers:

1. Array substrate;

2. Buffer layer;

201, hole;

3. The first layer of metal;

301. A first electrode;

302, the first metal;

4. Gate metal;

401. gate scan line;

5. Half-color mask;

6. The first insulating layer;

601. A first electrode insulating layer;

602. gate insulating layer;

7. The second layer of metal;

701. The second electrode;

702. Second metal;

8. The second insulating layer;

801. A second electrode insulating layer;

802. barrier layer;

9. The third layer of metal;

901. third electrode;

902, the third metal;

10. The fourth layer of metal;

1001. source signal line;

1002, drain;

1100. Passivation layer.

Detailed ways

In order to describe in detail the technical content, structural features, achieved objectives and effects of the technical solution, the following detailed description is given in conjunction with specific embodiments and accompanying drawings.

Referring to FIGS. 1 to 9 , this embodiment provides a method for fabricating an array substrate with a high capacitance structure. The fabrication method can be performed on the array substrate 1 , and a field thin film effect transistor is fabricated on one side of the array substrate 1 . Fabricating a capacitor structure on the other side of the array substrate 1 includes the following steps: fabricating a buffer layer 2 and a hole 201 on the array substrate 1; please refer to FIG. The material of the buffer layer 2 is one or more of organic photosensitive material, polyimide (PI), silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), and titanium oxide. After the buffer layer 2 is fabricated, holes 201 are formed on the buffer layer 2; a photoresist is coated on the buffer layer 2, and the photoresist is patterned, that is, exposure and development make the part where the holes 201 are to be formed open, and then the photoresist is used as a mask The buffer layer 2 is etched to obtain holes, and the photoresist is removed after the holes are formed. This manufacturing method can produce a plurality of holes 201 at the same time, and the cross-section of the holes 201 can be rectangular, circular, or other irregular shapes. The width gradually decreases from top to bottom, and the width of the bottom of the hole is smaller than the width of the orifice, thereby forming the hole 201 with a strip-shaped grid structure.

Next, a first layer of metal 3 and a gate metal 4 are formed on the array substrate 1 at one time to form a first electrode 301 , a first metal 302 and a gate scan line 401 ; please refer to FIG. 2 , the specific process steps are: The first layer of metal 3 and the gate metal 4 are plated on the top by means of electroplating, evaporation or sputtering, and the gate metal 4 is covered on the first layer of metal 3. The structure is shown in the first figure of FIG. 2 . The material of the first layer metal 3 is indium tin oxide (ITO), the thickness of the indium tin oxide thin film is 100 angstroms to 1000 angstroms, and the material of the gate metal 4 is aluminum, molybdenum, titanium, nickel, copper, silver , one or more metals with good electrical conductivity such as chromium or other alloys. Then, the photoresist on the gate metal 4 is patterned by using the half-color mask 5 having the semi-transparent area 501 , the fully-transparent area 502 and the fully-shielded area 503 , and the structure is shown in the second figure of FIG. 2 . . The light transmittance of the semi-transparent area 501 is 50%, the light transmittance of the fully transparent area 502 is 100%, and the light transmittance of the fully shading area 503 is 0%. The area 501 corresponds to the incompletely developed area, the fully transparent area 502 or the fully shielded area 503 corresponds to the fully developed area, the incompletely developed area corresponds to the area of the first electrode 301 in the capacitor structure, and the fully developed area corresponds to the gate scanning of the thin film field effect transistor Area of line 401. Wherein, if a negative photoresist is coated, the semi-transparent area 501 corresponds to the incomplete development area, that is, the area of the first electrode 301 in the capacitor structure, and the fully transparent area 502 corresponds to the fully developed area, that is, the area of the gate scanning line 401. For example, when a positive photoresist is coated, the semi-transparent area 501 corresponds to the incomplete development area, that is, the area of the first electrode 301 in the capacitor structure, and the fully shading area 503 corresponds to the fully developed area, that is, the area of the gate scanning line 401. In this manufacturing method, a positive photoresist is coated on the gate metal 4, and the photoresist is patterned using a half-color mask having a semi-transparent area 501, a fully-transparent area 502 and a fully-shielded area 503, and the semi-transparent area 501 is used to pattern the photoresist. Corresponding to the incompletely developed area, the incompletely developed area corresponds to the area of the first electrode 301 in the capacitor structure, the fully shading area 503 corresponds to the fully developed area, and the fully developed area corresponds to the area of the gate scanning line 401 in the TFT. After developing the photoresist, the photoresist in the incompletely developed area and the area other than the fully developed area is completely removed, and the photoresist in the incompletely developed area will be thinner than that in the fully developed area. shown in the three figures. Then, the gate metal 4 and the first layer metal 3 on the incompletely developed area and the area outside the fully developed area are etched with photoresist and mask, the structure is shown in the third figure of FIG. 2, and then an ashing process is performed The photoresist on the first layer of metal 3 in the incompletely developed area is removed. The structure is shown in the fourth figure of FIG. 2. The gate metal 4 in the incompletely developed area is removed by etching time control or selective etching solution. Retain the first layer of metal 3 in the incompletely developed area and form the first electrode 301 in the hole 201, retain the gate metal 4 and the first layer of metal 3 in the fully developed area and form the gate on the buffer layer 2 outside the hole 201 The scan line 401 and the first metal 302 are finally lifted off and cleaned. The first electrode 301 and the first metal 302 are on the buffer layer 2 , the first electrode 301 and the first metal 302 have a gap, and the gate scan line 401 is on the first metal 302 . Among them, the first electrode 301 is used as the first plate of the lower capacitor structure. When the first electrode 301 is formed in the hole 201, the useful first electrode 301 is generally reserved. For the surface of the buffer layer 2 between the hole 201 and the hole 201 Or the first layer of metal 3 on the surface of the buffer layer 2 around the holes 201 on both sides can also be reserved as the first electrode 301. On the one hand, the first electrode 301 on the surface of the buffer layer 2 can be used as a capacitor structure and other circuits The connection point, such as the parallel connection between the upper and lower capacitor structures, on the other hand, the first electrode 301 between the holes 201 and the holes 201 can connect the capacitor structures in the two holes 201, thereby further improving the capacitance capacity. In this manufacturing method, the first layer of metal 3 and the gate metal 4 are formed at one time, and only the first layer of metal 3 is reserved as an electrode in the capacitor region. Since the material of the first layer of metal 3 is indium tin oxide, indium tin oxide is relatively thin (100 Angstroms to 1000 Angstroms), which is beneficial to increase the number of strip-shaped grid holes and further improve the capacitance; secondly, the use of indium tin oxide as a bridge to connect the active layer with the source signal line 1001 and the drain 1002 can reduce ohmic contact resistance, and improve the electrical properties of thin film field effect transistors. The manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

After the first electrode, the first metal and the gate scan line are fabricated, the first electrode insulating layer 601, the gate insulating layer 602, the second electrode 701 and the second metal 702 are fabricated; please refer to FIG. 3, the specific process is as follows A first insulating layer 6 is covered on the array substrate 1, and then a second metal layer 7 is continuously plated on the first insulating layer 6. The second metal layer 7 can be fabricated by electroplating, vapor deposition, and sputtering. The structure is shown in the figure 3 is shown in the first figure. The first insulating layer 6 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc., and the second layer metal 7 is indium gallium zinc oxide (IGZO), indium zinc oxide ( IZO), IGZTO and other metal oxides, etc. The photoresist is also patterned using a half-color mask 5 having a semi-transparent area 501 , a fully-transparent area 502 and a fully-shielded area 503 . The light transmittance of the semi-transparent area 501 is 50%, the light transmittance of the fully transparent area 502 is 100%, and the light transmittance of the fully shading area 503 is 0%. The area 501 corresponds to the incompletely developed area, the fully transparent area 502 or the fully shielded area 503 corresponds to the fully developed area, the incompletely developed area corresponds to the area of the second electrode 701 in the capacitor structure, and the fully developed area corresponds to the area of the second metal 702 . Wherein, if a negative photoresist is coated, the semi-transparent area 501 corresponds to the incomplete development area, that is, the area of the second electrode 701 in the capacitor structure, and the fully transparent area 502 corresponds to the fully developed area, that is, the area of the second metal 702. For example, when a positive photoresist is coated, the semi-transparent area 501 corresponds to the incompletely developed area, that is, the area of the second electrode 701 in the capacitor structure, and the fully shading area 503 corresponds to the fully developed area, that is, the area of the second metal 702. Please refer to the second diagram of FIG. 3 , a positive photoresist is applied on the second layer of metal 7 , and a pattern of a half-color mask 5 having a semi-transparent area 501 , a fully-transparent area 502 and a fully-shielded area 503 is used The photoresist, the semi-transparent area 501 corresponds to the incomplete development area, the incomplete development area corresponds to the area of the second electrode 701 in the capacitor structure, the fully shading area 503 corresponds to the fully developed area, and the fully developed area corresponds to the second electrode of the thin film field effect transistor. metal area. After developing the photoresist, the photoresist in the incompletely developed area and the area other than the fully developed area is completely removed, and the photoresist in the incompletely developed area will be thinner than that in the fully developed area. shown in the three figures. Then, the second layer of metal 6 in the incompletely developed area and the area outside the fully developed area is etched with a photoresist and a mask, and the first insulating layer 6 is retained. The structure is shown in the fourth diagram of FIG. 3 . Then, the photoresist on the second layer of metal 7 in the incompletely developed area is removed by ashing treatment, the metal oxide of the capacitor structure is made conductive by hydrogen ion implantation, and the oxide and source signals of the thin film field effect transistor are improved. The ohmic contact characteristics of the line 1001 and the drain 1002 reduce the contact resistance, and the structure is shown in the fifth diagram of FIG. 3 . After hydrogen ion implantation, the first insulating layer 6 in the incompletely developed area is retained, and a first electrode insulating layer 601 covering the first electrode 301 is formed in the hole 201 and on the surface of the buffer layer 2 between the hole 201 and the hole 201. The second layer of metal 7 in the fully developed area and the second electrode 701 are formed in the hole 201, the first insulating layer 6 and the second layer of metal 7 in the fully developed area are reserved and gate insulation is formed on the buffer layer 2 outside the hole 201 Layer 602 and second metal 702, and finally metal lift off and debonding cleaning. When the second electrode 701 is formed in the hole 201, the useful second electrode 701 is generally reserved. A part of the metal 7 also remains as the second electrode 701 , and the second electrode 701 between the holes 201 and the holes 201 can connect the capacitor structures in the two holes 201 . The manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

The first electrode insulating layer 601 covering the first electrode 301 is used as the dielectric layer of the lower capacitor structure, and the first electrode insulating layer 601 realizes the isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, thereby avoiding the first electrode. The electrical connection between the first electrode 301 and the second electrode 701, the second electrode 701 is on the first electrode insulating layer 601, the second electrode 601 serves as the common plate of the upper and lower capacitor structures; the gate insulating layer 602 covers and wraps The gate scan line 401 and the first metal 302 and the second metal 702 are on the gate insulating layer 602 and serve as the active layer of the thin film field effect transistor.

Then, the second electrode insulating layer 801 and the barrier layer 802 are fabricated; please refer to FIG. 4 , the specific process is to cover the second insulating layer 8 on the array substrate 1 . The second insulating layer 8 is made of the same material as the first insulating layer 6 , which is oxidized Silicon composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, etc. Then, the second insulating layer 8 is patterned by photolithography, and the second insulating layer 8 is etched with the photoresist as a mask to expose the two sides of the second metal 702 and the two sides of the gate insulating layer, and form on the second metal 702 The blocking layer 802, using the photoresist as a mask to etch the second insulating layer 8 on the surface of the outer buffer layer 2 of the hole 201 to the first electrode 301 to form a through hole, the bottom of the through hole is the first electrode 301, inside the hole 201 and the A second electrode insulating layer 801 covering the second electrode 701 is formed on the second electrode 701 on the surface of the buffer layer 2 between the hole 201 and the hole 201. The second electrode insulating layer 801 serves as the dielectric layer of the upper capacitor structure, and the second electrode The insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding electrical connection between the second electrode 701 and the third electrode 901 . The first electrode 301 at the bottom of the through hole can be connected to the third electrode 901, so as to realize the connection between the upper-layer capacitor structure and the lower-layer capacitor structure. After the second electrode insulating layer 801 and the blocking layer 802 are formed, the photoresist is removed. In some embodiments, the barrier layer 802 on the second metal 702 does not need to be fabricated, and can be designed as a BCE structure thin film field effect transistor as required, which can save a photomask. The structure is shown in FIG. 5 .

After the second electrode insulating layer 801 and the barrier layer 802 are fabricated, the third electrode 901, the third metal 903, the source signal line 1001 and the drain 1002 are fabricated; please refer to FIG. A third metal 902 is formed on the second metal 702 and the barrier layer 802 , and a third electrode 9 is formed in the hole 201 . The third layer of metal 9 on top also retains a part as the third electrode 901. The third electrode 901 can be connected to the first electrode 301 through the through hole of the second electrode insulating layer 802 on the first electrode 301, and the third electrode 901 is connected to the first electrode 301. After an electrode 301 is connected, the parallel connection of the upper-layer capacitor structure and the lower-layer capacitor structure is realized. The manufacturing method can directly use metal as the electrode of the capacitor structure, which can simplify the process.

The third metal 902 wraps the second metal 702 and both sides of the barrier layer 802 on the barrier layer 802 , and the third metal 902 exposes the central portion of the barrier layer 802 , that is, the third metal 902 has two portions. After the third metal 902 is fabricated, a fourth layer of metal 10 is deposited. The fourth layer of metal 10 is metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc., on the third metal 902 A source signal line 1001 is formed on one side of the third metal 902, a drain 1002 is formed on the other side of the third metal 902, the source signal line 1001 and the drain 1002 have a gap, and the structure is shown in FIG. 6 . After the third electrode 901 , the source signal line 1001 and the drain electrode 1002 are fabricated, the metal is lifted off and the adhesive is removed for cleaning.

In order to protect the capacitor structure and avoid the direct contact between the external structure and the capacitor structure and the thin film field effect transistor, the manufacturing method also performs the manufacture of the passivation layer 1100; please refer to FIG. 7, the passivation can be plated by chemical vapor deposition method The layer 1100 and the passivation layer 1100 are made of silicon oxide composite film (SiOx), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide and other materials. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, etc. After covering, only the passivation layer 1100 can be contacted from the outside, but not the capacitor structure and the thin film Field effect transistor.

Please refer to FIG. 8 to FIG. 9 , the three-dimensional grid structure capacitor of the present invention can effectively reduce the area occupied by the capacitor area compared with the original plate capacitor, and reduce the size of the capacitor under the condition of maintaining the same capacity; The metal oxide is made into a conductor and used as a capacitor electrode, which improves the ohmic contact characteristics, reduces the contact resistance, forms two parallel capacitors with excellent performance, and further increases the capacitance capacity. Please refer to Figure 8. According to the parallel capacitance formula C and = C1+C2, (C1 and C2 are upper and lower capacitance structures), in order to maintain the same capacitance, the actual occupied area of the grid capacitor can be further reduced by 50% compared with the theoretical capacitance area of the plate. %; please refer to Figure 9, where the capacitance area of the grid capacitor S=(S1+S2+S3+S4)*n, _the occupied area S=(S1′+S2+S3+S4′)*n, according to the trigonometric function S1′=Sinα*S1, if S1′=S2=S3 and Taperα=60°, the actual occupied area of the grid capacitor can be reduced by 33% compared with the area of the plate capacitor under the condition of keeping the same capacitance.

The first layer of metal and gate metal are formed at one time, and only indium tin oxide (the material of the first layer of metal) is reserved in the capacitor region as the electrode. The number of grid-shaped holes further increases the capacitance. Secondly, using indium tin oxide as a bridge to connect the active layer with the source and drain can reduce the resistance of the ohmic contact and improve the electrical performance of the thin film field effect transistor. The electrode region of the manufacturing method can also directly use metal as the electrode plate, which can simplify the process.

The present invention provides an array substrate with a high capacitance structure. As shown in FIG. 1 , FIG. 4 to FIG. 9 , the array substrate with a high capacitance structure in this embodiment can be manufactured according to the above method. The array substrate with a high capacitance structure includes: a buffer layer 2 is provided on the array substrate 1, and the material of the buffer layer 2 is an organic photosensitive material, a polyimide film (PI), a silicon oxide composite film (SiOx), and a silicon nitride composite film. One or more of film (SiNx) and titanium oxide. A plurality of holes 201 are provided on the buffer layer 2 , and the structure is shown in FIG. 1 . The cross-section of the hole 201 of the present invention can be rectangular, circular, or other irregular shapes, and the structure is shown in FIG. 6 . For example, the cross-section of the hole 201 of the strip-shaped grid structure is rectangular, and the width of the cross-section is from top to bottom. The width of the bottom of the hole is gradually reduced, and the width of the hole bottom is smaller than the width of the hole. A thin film field effect transistor is provided on the buffer layer 2 outside the hole 201 .

Please refer to FIG. 4 , a first electrode 301 , a first electrode insulating layer 601 and a second electrode 701 are arranged in the hole 201 and between the holes 201 and 201 in sequence; An electrode insulating layer 601 covers the first electrode 301 and serves as the dielectric layer of the lower capacitor structure; the second electrode is on the first electrode insulating layer and serves as the common plate of the upper and lower capacitor structures; the second electrode insulating layer covers the second electrode and As a dielectric layer of the upper capacitor structure, the first electrode insulating layer 601 realizes isolation between the first electrode 301 and the second electrode 701 in the lower capacitor structure, thereby avoiding electrical connection between the first electrode 301 and the second electrode 701 . The first electrode 301 , the first electrode insulating layer 601 and the second electrode 701 form a lower capacitance structure. Since the first electrode 301 and the second electrode 701 on both sides of the inner wall of the hole are grid-like planes, the area of the metal can be greatly increased, so that a larger capacitance value can be realized. At the same time, parasitic capacitance effects and required semiconductor device area are reduced. Please refer to FIG. 9, where the capacitance area of the grid capacitor S=(S1+S2+S3+S4)*n, _the occupied area S=(S1′+S2+S3+S4′)*n, according to the trigonometric function S1′ =Sinα*S1, if S1′=S2=S3 and Taperα=60°, the actual occupied area of the grid capacitor can be reduced by 33% compared with the traditional plate capacitor under the condition of keeping the same capacitance.

The first electrode 301 is indium tin oxide, and indium tin oxide is relatively thin (100 angstroms to 1000 angstroms), which is beneficial to increase the number of first electrodes 301 and further improve the capacitance; secondly, indium tin oxide is used as a bridge to connect the active layer The ohmic contact resistance with the source signal line 1001 and the drain 1002 can be reduced, and the electrical performance of the thin film field effect transistor can be improved. The first electrode insulating layer 601 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like.

Referring to FIG. 6 , a second electrode insulating layer 801 and a third electrode 901 are sequentially disposed in the hole 201 and between the hole 201 and the hole 201 ; the second electrode insulating layer 801 covers the second electrode 701 and serves as a medium for the upper capacitor structure layer, the third electrode 901 is on the second electrode insulating layer 801 and serves as the electrode plate of the upper capacitor structure, the first electrode insulating layer 601, the second electrode insulating layer 801 and the second electrode 701 on the buffer layer 2 surface are exposed to the bottom The first electrode 301 . The second electrode insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding electrical connection between the second electrode 701 and the third electrode 901 . The second electrode 701, the second electrode insulating layer 801 and the third electrode 901 form a lower-layer capacitor structure. Since the second electrode 701 and the third electrode 901 on both sides of the inner wall of the hole are grid-like planes, the area of the metal can be greatly increased, so that a larger capacitance value can be realized. The first electrode 301 and the third electrode 901 on the surface of the buffer layer 2 are connected to realize the parallel connection of the upper and lower capacitance structures. Please refer to FIG. 8. According to the parallel capacitance formula C and = C1 + C2, (C1 and C2 are the upper and lower capacitances In order to keep the capacity equal, the actual occupied area of the grid capacitor can be further reduced by 50% compared with the theoretical capacitor area of the plate.

Please refer to FIG. 6 , a thin film field effect semiconductor is disposed on the buffer layer 2 outside the hole 201 , and the thin film field effect semiconductor includes: a first metal 302 is disposed on the buffer layer 2 outside the hole 201 , and the first metal 302 is oxidized Indium tin; a gate scan line 401 is provided on the first metal 302, and the gate scan line 401 is one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with good conductivity or other alloys .

A gate insulating layer 602 is provided on the gate scanning line 401, the gate insulating layer 602 covers and wraps the gate scanning line 401 and the first metal 302, and the gate insulating layer 602 is made of silicon oxide composite film (SiOx), nitrogen Silicon compound film (SiNx), titanium oxide, aluminum oxide, etc.

A second metal 702 is disposed on the gate insulating layer 602, and the second metal 702 is metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc.; and the second metal 702 is disposed on the second metal 702 There is a barrier layer 802, and a second metal 702 is on the gate insulating layer 602 and serves as the active layer of the thin film field effect transistor. In some embodiments, the barrier layer may not be provided, and the structure is shown in FIG. 5 .

A third metal 902 is disposed on the barrier layer 802. The third metal 902 is metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. The third metal 903 wraps the second metal 702 and both sides of the barrier layer 802, the third metal 902 exposes the central part of the barrier layer 802, the source signal line 1001 is arranged on one side of the third metal 902, and the other side is arranged on the third metal 903. The drain 1002, the source signal line 1001 and the drain 1002 are metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), IGZTO, etc. The source signal line 1001 and the drain 1002 have a gap, the structure As shown in Figure 6.

In order to protect the capacitor structure and avoid direct contact between the external structure and the capacitor structure and the thin film field effect transistor, a passivation layer 1100 is provided on the capacitor region and the thin film field effect transistor, and the passivation layer 1100 is a silicon oxide composite film (SiOx ), silicon nitride composite film (SiNx), titanium oxide, aluminum oxide and other materials. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, etc. After covering, only the passivation layer 1100 can be contacted from the outside, but not the capacitor structure and the thin film Field effect transistor.

It should be noted that, although the above embodiments have been described herein, it does not limit the scope of the patent protection of the present invention. Therefore, based on the innovative concept of the present invention, changes and modifications to the embodiments described herein, or equivalent structures or equivalent process transformations made by using the contents of the description and drawings of the present invention, directly or indirectly apply the above technical solutions In other related technical fields, all are included within the scope of patent protection of the present invention.

Claims (10)

1. A method for making an array substrate with a high capacitance structure, comprising the steps of: making a buffer layer on the array substrate; make holes in the buffer layer; depositing a first layer of metal, forming a first electrode in the hole, and the first electrode is used as the electrode plate of the lower capacitor structure; After covering the first insulating layer, continue to deposit a second layer of metal, forming a first electrode insulating layer covering the first electrode in the hole, forming a second electrode on the first electrode insulating layer in the hole, and the second electrode as the upper and lower layers Common plate of capacitor structure; covering the second insulating layer, and forming a second electrode insulating layer covering the second electrode in the hole; depositing a third layer of metal, forming a third electrode on the second insulating layer in the hole, and the third electrode is used as a pole plate of the upper capacitor structure; A thin film field effect transistor is also arranged on the buffer layer outside the hole. 2. The method for fabricating an array substrate with a high capacitance structure according to claim 1, further comprising the following steps: When depositing the first layer of metal, extend the first electrode in the hole to the surface of the buffer layer; or: after covering the first insulating layer and continue to deposit the second layer of metal, extend the second electrode in the hole to the surface of the first layer of metal. The electrode insulating layer is to the surface of the buffer layer outside the hole; or: when covering the second insulating layer, the second electrode insulating layer in the hole is extended to the surface of the buffer layer outside the hole: or: when the third layer of metal is deposited, extending the third electrode in the hole to the surface of the buffer layer outside the hole; or: connecting the third electrode on the surface of the buffer layer outside the hole and the first electrode on the surface of the buffer layer outside the hole. 3. The method for fabricating an array substrate with a high capacitance structure according to claim 2, wherein the fabrication steps of the thin film field effect transistor are: After depositing the first layer of metal, continue to deposit gate metal, and form the first metal and the gate scan line on the buffer layer outside the hole, the first metal is on the buffer layer outside the hole, and the gate scan line is on the first metal superior; After covering the first insulating layer, continue to deposit a second layer of metal to form a gate insulating layer on the gate scanning line, the gate insulating layer covers and wraps the gate scanning line and the first metal, and forms on the gate insulating layer the second metal; forming a barrier layer on the second metal while covering the second insulating layer; When depositing the third layer of metal, a third metal wrapping the second metal and both sides of the barrier layer is formed on the barrier layer, and the third metal exposes a central portion of the barrier layer; A fourth layer of metal is deposited, a source signal line is formed on one side of the third metal, and a drain is formed on the other side of the third metal. 4. The method for fabricating an array substrate with a high capacitance structure according to claim 3, wherein after depositing the first layer of metal, when depositing the gate metal, the method further comprises the following steps: Coat the photoresist on the gate metal, pattern the photoresist with a half-color mask with semi-transparent area, fully-transparent area, and fully-shielded area, and the semi-transparent area after developing the photoresist is not completely corresponding The developing area, the fully transparent area or the fully shading area corresponds to the fully developed area, the incompletely developed area corresponds to the area of the first electrode in the capacitor structure, and the fully developed area corresponds to the area of the gate scanning line; Using the photoresist as a mask to etch the gate metal and the first layer of metal on the areas other than the fully developed area and the incompletely developed area; Remove the photoresist on the first layer of metal in the incompletely developed area by ashing treatment, and retain the photoresist on the gate metal in the fully developed area; The gate metal in the incompletely developed area is etched to the first layer of metal, the first layer of metal is retained as the first electrode, and the photoresist on the fully developed area is removed to form the first metal and the gate scan line. 5. The method for fabricating an array substrate with a high capacitance structure according to claim 3, wherein after the first insulating layer is covered and the second layer of metal is continuously deposited, the method further comprises the following steps: Coat photoresist on the second layer of metal, pattern the photoresist with a half-color mask with semi-transparent area, fully-transparent area and fully-shielded area. The fully developed area, the fully transparent area or the fully shading area corresponds to the fully developed area, the incompletely developed area corresponds to the area of the second electrode area in the capacitor structure, and the fully developed area corresponds to the area of the second metal; Etch the second layer of metal in the incompletely developed area and areas other than the fully developed area, remove the photoresist on the second layer of metal in the incompletely developed area by ashing treatment, and then implant hydrogen ions to remove the first layer of metal in the fully developed area. A photoresist on an insulating layer material, the second metal layer and the first insulating layer in the incompletely developed area are reserved as the second electrode and the first electrode insulating layer, respectively, and the second layer of metal and the first insulating layer in the fully developed area are reserved. as the second metal and gate insulating layer, respectively. 6. a kind of manufacture method of the array substrate with high capacitance structure according to claim 1 or 2 or 3, is characterized in that, also comprises the steps: Covering the material of the third insulating layer, a passivation layer is formed on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, and the passivation layer protects the capacitor structure and the thin film field effect transistor. 7 . The method for fabricating an array substrate with a high capacitance structure according to claim 1 , wherein the material of the first layer of metal is indium tin oxide. 8 . 8 . An array substrate with a high-capacitance structure, wherein the array substrate with a high-capacitance structure is produced by the manufacturing method according to any one of claims 1 to 7 . 9. An array substrate with a high capacitance structure, comprising: A buffer layer is arranged on the array substrate, a hole is arranged on the buffer layer, and a thin film field effect transistor is arranged on the buffer layer outside the hole; A first electrode, a first electrode insulating layer, a second electrode, a second electrode insulating layer and a third electrode are sequentially arranged in the hole and on the surface of the buffer layer between the holes, and the first electrode serves as the electrode of the lower capacitor structure. plate, the first electrode insulating layer covers the first electrode and serves as the dielectric layer of the lower capacitor structure, the second electrode is on the first electrode insulating layer and serves as the common plate of the upper and lower capacitor structures, and the second electrode insulating layer covers the second electrode And as the dielectric layer of the upper capacitor structure, the third electrode is on the second electrode insulating layer and serves as the electrode plate of the upper capacitor structure. 10. The array substrate with a high capacitance structure according to claim 9, wherein the thin film field effect transistor comprises: A first metal is arranged on the buffer layer outside the hole, and a gate scan line is arranged on the first metal; A gate insulating layer is provided on the gate scanning line, and the gate insulating layer covers and wraps the gate scanning line and the first metal; A second metal is arranged on the gate insulating layer, and a barrier layer is arranged on the second metal; A third metal is arranged on the barrier layer, the third metal wraps the second metal and both sides of the barrier layer, the third metal exposes the central part of the barrier layer, and a source signal line is arranged on one side of the third metal, A drain is provided on the other side of the third metal.

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