CN110867457A - Array substrate with high-capacitance structure and manufacturing method - Google Patents
Array substrate with high-capacitance structure and manufacturing method Download PDFInfo
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- CN110867457A CN110867457A CN201911135019.6A CN201911135019A CN110867457A CN 110867457 A CN110867457 A CN 110867457A CN 201911135019 A CN201911135019 A CN 201911135019A CN 110867457 A CN110867457 A CN 110867457A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses an array substrate with a high-capacitance structure and a manufacturing method thereof, wherein the method comprises the following steps: manufacturing a buffer layer on the array substrate; making holes on the buffer layer; manufacturing a first electrode in the hole; manufacturing a first electrode insulating layer covering the first electrode in the hole; manufacturing a second electrode on the first electrode insulating layer in the hole, and manufacturing a second electrode insulating layer covering the second electrode in the hole; manufacturing a third electrode on the second insulating layer in the hole; a thin film field effect transistor is also arranged on the buffer layer outside the hole; the thin film field effect transistor with the high-capacitance structure is manufactured, a circuit driven by the high-capacitance structure has a better voltage stabilizing effect, the capacitance value of the storage capacitor can be increased, the occupied area of the capacitor is reduced, and the advantages of improving the pixel density (ppi) of the panel and reducing the size of a frame of the panel are also achieved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate with a high-capacitance structure and a manufacturing method thereof.
Background
Rapid developments in active matrix organic light emitting diode displays (AMOLEDs) and high performance Active Matrix Liquid Crystal Displays (AMLCDs) merit many high resolution and high frame rate displays. In order to make the driving circuit have a better voltage stabilizing effect, a large-capacity capacitor is usually required to be arranged in the array substrate, but the large-capacity capacitor causes a large occupied area of the driving circuit, so that the frame size and the pixel size of the display panel cannot be further reduced. Therefore, how to design and manufacture a high-performance and small-sized array substrate structure is an increasingly challenging research topic.
IGZO (indium gallium zinc oxide) is indium gallium zinc oxide, is amorphous oxide containing indium, gallium and zinc, has carrier mobility 20-30 times that of amorphous silicon, can greatly improve the charge-discharge rate of a TFT to a pixel electrode, improves the response speed of pixels, has faster panel refreshing frequency, and can realize an ultrahigh-resolution display panel. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).
Disclosure of Invention
Therefore, it is desirable to provide an array substrate with a high-capacitance structure and a manufacturing method thereof, so as to solve the problem that the area is too large when a high capacitor is provided during the manufacturing of the display device.
In order to achieve the above object, the inventor provides a method for manufacturing an array substrate with a high capacitance structure, comprising the following steps:
manufacturing a buffer layer on the array substrate;
making holes on the buffer layer;
depositing a first layer of metal, and forming a first electrode in the hole, wherein the first electrode is used as a polar plate of a lower-layer capacitor structure;
after covering the first insulating layer, continuously depositing a second layer of metal, forming a first electrode insulating layer covering the first electrode in the hole, forming a second electrode on the first electrode insulating layer in the hole, wherein the second electrode is used as a common electrode plate of the upper-layer and lower-layer capacitor structures;
covering the second insulating layer, and forming a second electrode insulating layer covering the second electrode in the hole;
depositing a third layer of metal, and forming a third electrode on the second insulating layer in the hole, wherein the third electrode is used as a polar plate of the upper-layer capacitor structure;
and a thin film field effect transistor is also arranged on the buffer layer outside the hole.
Further, the method also comprises the following steps:
extending the first electrode in the hole to the surface of the buffer layer when depositing the first layer of metal; or: after covering the first insulating layer, extending the second electrode and the first electrode insulating layer in the hole to the surface of the buffer layer outside the hole when continuously depositing the second layer of metal; or: when covering the second insulating layer, extending the second electrode insulating layer in the hole to the surface of the buffer layer outside the hole: or: extending the third electrode in the hole to the surface of the buffer layer outside the hole when depositing the third layer of metal; or: connecting the third electrode on the face of the outer buffer layer of the hole with the first electrode on the face of the outer buffer layer of the hole.
Further, the manufacturing steps of the thin film field effect transistor are as follows:
after depositing the first layer of metal, continuing to deposit gate metal, and forming a first metal and a gate scanning line on the buffer layer outside the hole, wherein the first metal is on the buffer layer outside the hole, and the gate scanning line is on the first metal;
after covering the first insulating layer, continuously depositing a second layer of metal, forming a grid electrode insulating layer on the grid electrode scanning line, covering and wrapping the grid electrode scanning line and the first metal by the grid electrode insulating layer, and forming a second metal on the grid electrode insulating layer;
forming a barrier layer on the second metal while covering the second insulating layer;
when depositing a third layer of metal, forming a third metal wrapping the second metal and two sides of the barrier layer on the barrier layer, wherein the third metal is exposed out of the central part of the barrier layer;
and depositing a fourth layer of metal, forming a source signal line on one side of the third metal, and forming a drain on the other side of the third metal.
Further, after depositing the first layer of metal, when continuing to deposit the gate metal, the method further comprises the following steps:
coating a photoresist on the gate metal, patterning the photoresist by using a half-color mask with a semi-transparent region, a full-transparent region and a full-shading region, wherein the semi-transparent region corresponds to an incomplete developing region after the photoresist is developed, the full-transparent region or the full-shading region corresponds to the complete developing region, the incomplete developing region corresponds to a region of a first electrode in the capacitor structure, and the complete developing region corresponds to a region of a gate scanning line;
etching the gate metal and the first layer of metal on the areas outside the complete development area and the incomplete development area by using the photoresist as a mask;
removing the photoresist on the first layer of metal in the incomplete developing area through ashing treatment, and reserving the photoresist on the gate metal in the complete developing area;
etching the gate metal in the incomplete developing area to the first layer of metal, reserving the first layer of metal as a first electrode, and removing the photoresist on the complete developing area to form the first metal and a gate scanning line.
Further, after covering the first insulating layer, when continuing to deposit the second metal layer, the method further comprises the following steps:
coating a photoresist on the second layer of metal, patterning the photoresist by using a half-color mask plate with a semi-transparent area, a full-transparent area and a full-light-shielding area, wherein the semi-transparent area corresponds to an incomplete developing area after the photoresist is developed, the full-transparent area or the full-light-shielding area corresponds to the complete developing area, the incomplete developing area corresponds to the area of the second electrode in the capacitor structure, and the complete developing area corresponds to the area of the second metal;
etching the second layer of metal on the incomplete developing area and the area outside the complete developing area, removing photoresist on the second layer of metal in the incomplete developing area through ashing treatment, then, injecting hydrogen ions, removing photoresist on the first insulating layer material in the complete developing area, reserving the second layer of metal and the first insulating layer in the incomplete developing area as a second electrode and a first electrode insulating layer respectively, and reserving the second layer of metal and the first insulating layer in the complete developing area as a second metal and a grid electrode insulating layer respectively.
Further, the method also comprises the following steps:
and covering a third insulating layer material, and forming a passivation layer on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, wherein the passivation layer protects the capacitor structure and the thin film field effect transistor.
Further, the material of the first layer of metal is indium tin oxide.
The invention provides an array substrate with a high-capacitance structure, which is characterized in that the array substrate with the high-capacitance structure is prepared by any one of the methods for preparing the array substrate with the high-capacitance structure.
The invention provides an array substrate with a high-capacitance structure, which comprises:
the array substrate is provided with a buffer layer, the buffer layer is provided with holes, and the buffer layer outside the holes is provided with a thin film field effect transistor;
a first electrode, a first electrode insulating layer, a second electrode insulating layer and a third electrode are sequentially arranged in the hole and on the surface of the buffer layer between the hole and the hole, the first electrode is used as a polar plate of a lower-layer capacitor structure, the first electrode insulating layer covers the first electrode and is used as a dielectric layer of the lower-layer capacitor structure, the second electrode is arranged on the first electrode insulating layer and is used as a shared polar plate of an upper-layer capacitor structure, the second electrode insulating layer covers the second electrode and is used as a dielectric layer of an upper-layer capacitor structure, and the third electrode is arranged on the second electrode insulating layer and is used as a polar plate of the upper-layer capacitor structure.
Further, the thin film transistor includes:
a first metal is arranged on the buffer layer outside the hole, and a grid scanning line is arranged on the first metal;
a grid electrode insulation layer is arranged on the grid electrode scanning line, and covers and wraps the grid electrode scanning line and the first metal;
a second metal is arranged on the grid electrode insulating layer, and a barrier layer is arranged on the second metal;
and a third metal is arranged on the barrier layer, wraps the second metal and the two sides of the barrier layer, is exposed out of the center part of the barrier layer, is provided with a source signal line on one side and is provided with a drain on the other side.
Different from the prior art, the thin film field effect transistor with the high-capacitance structure is manufactured by the technical scheme, the circuit driven by the high-capacitance structure has a better voltage stabilizing effect, the capacitance value of the storage capacitor can be increased, the occupied area of the capacitor is reduced, and the advantages of improving the pixel density (ppi) of the panel and reducing the frame size of the panel are also achieved.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a buffer layer and a hole formed in an array substrate according to the present invention;
FIG. 2 is a process flow diagram of fabricating a first electrode, a first metal and a gate scan line on an array substrate according to the present invention;
FIG. 3 is a process flow diagram of fabricating a first electrode insulating layer, a gate insulating layer, a second electrode and a second metal on an array substrate according to the present invention;
FIG. 4 is a schematic cross-sectional view illustrating the fabrication of a second electrode insulating layer and a barrier layer on an array substrate according to the present invention;
fig. 5 is a schematic cross-sectional view of a thin film transistor according to another embodiment of the present invention;
FIG. 6 is a cross-sectional view of a third electrode, a third metal, a source signal line and a drain formed on an array substrate according to the present invention;
FIG. 7 is a schematic cross-sectional view illustrating a passivation layer formed on an array substrate according to the present invention;
FIG. 8 is a schematic diagram of a parallel configuration of the grid capacitor structure according to the present invention;
fig. 9 is a schematic cross-sectional structure diagram of the gate capacitor structure according to the present invention.
Description of reference numerals:
1. an array substrate;
2. a buffer layer;
201. an aperture;
3. a first layer of metal;
301. a first electrode;
302. a first metal;
4. a gate metal;
401. a gate scan line;
5. a half-color mask plate;
6. a first insulating layer;
601. a first electrode insulating layer;
602. a gate insulating layer;
7. a second layer of metal;
701. a second electrode;
702. a second metal;
8. a second insulating layer;
801. a second electrode insulating layer;
802. a barrier layer;
9. a third layer of metal;
901. a third electrode;
902. a third metal;
10. a fourth layer of metal;
1001. a source signal line;
1002. a drain electrode;
1100. and a passivation layer.
Detailed Description
To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 to 9, the present embodiment provides a method for manufacturing an array substrate with a high capacitance structure, which may be performed on the array substrate 1, wherein a field-effect transistor is manufactured on one side of the array substrate 1, and a capacitance structure is manufactured on the other side of the array substrate 1, and the method includes the following steps: manufacturing a buffer layer 2 and a hole 201 on an array substrate 1; referring to fig. 1, a buffer layer 2 is covered on an array substrate 1, and the buffer layer 2 is made of one or more of an organic photosensitive material, Polyimide (PI), a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), and titanium oxide. After the buffer layer 2 is manufactured, a hole 201 is formed in the buffer layer 2; coating photoresist on the buffer layer 2, patterning the photoresist, namely exposing and developing to open the part of the hole 201 to be manufactured, etching the buffer layer 2 by using the photoresist as a mask to obtain a hole, and removing the photoresist after the hole is manufactured. The manufacturing method can manufacture a plurality of holes 201 at the same time, the cross section of each hole 201 can be rectangular, circular or other irregular shapes, for example, the manufacturing method shows that the manufactured holes 201 with the rectangular cross section are gradually reduced from top to bottom, the width of the hole bottom is smaller than that of the hole opening, so that the holes 201 with strip-shaped grid-shaped structures are formed, and grid-shaped capacitor structures can be manufactured in the holes 201 and between the holes 201 and the holes 201.
Then, forming a first layer of metal 3 and a gate metal 4 on the array substrate 1 at one time to form a first electrode 301, a first metal 302 and a gate scanning line 401; referring to fig. 2, the specific process steps include plating a first metal layer 3 and a gate metal layer 4 on the array substrate 1 by electroplating, evaporation or sputtering, and the gate metal layer 4 covers the first metal layer 3, as shown in the first diagram of fig. 2. The first layer metal 3 is made of Indium Tin Oxide (ITO), the thickness of the ITO film is 100 to 1000 angstroms, and the gate metal 4 is made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity or other alloys. Then, the photoresist on the gate metal 4 is patterned by using a half-color mask 5 having a half-transmissive region 501, a full-transmissive region 502 and a full-opaque region 503, and the structure is as shown in the second diagram of fig. 2. The light transmittance of the semi-light-transmitting region 501 is 50%, the light transmittance of the full-light-transmitting region 502 is 100%, the light transmittance of the full-light-shielding region 503 is 0%, the semi-light-transmitting region 501 corresponds to an incomplete development region after the photoresist development, the full-light-transmitting region 502 or the full-light-shielding region 503 corresponds to a complete development region, the incomplete development region corresponds to a region of the first electrode 301 in the capacitor structure, and the complete development region corresponds to a region of the gate scanning line 401 of the thin film field effect transistor. When a negative photoresist is coated, the semi-transmissive region 501 corresponds to an incomplete developing region, i.e., a region of the first electrode 301 in the capacitor structure, and the fully transmissive region 502 corresponds to a complete developing region, i.e., a region of the gate scan line 401; if a positive photoresist is coated, the semi-transmissive region 501 corresponds to an incomplete developing region, i.e., a region of the first electrode 301 in the capacitor structure, and the fully opaque region 503 corresponds to a complete developing region, i.e., a region of the gate scan line 401. The manufacturing method comprises the steps of coating a positive photoresist on a gate metal 4, and patterning the photoresist by using a half-color mask plate with a semi-light-transmitting area 501, a full-light-transmitting area 502 and a full-light-shielding area 503, wherein the semi-light-transmitting area 501 corresponds to an incomplete developing area, the incomplete developing area corresponds to an area of a first electrode 301 in a capacitor structure, the full-light-shielding area 503 corresponds to a full developing area, and the full developing area corresponds to an area of a gate scanning line 401 in a thin film field effect transistor. After developing the photoresist, the photoresist in the incomplete developing area and the area outside the complete developing area is completely removed, and the photoresist in the incomplete developing area is thinner than the photoresist in the complete developing area, and the structure is shown in the third diagram of fig. 2. Then, etching the gate metal 4 and the first layer of metal 3 on the incomplete development area and the area outside the complete development area by using a photoresist and a mask, wherein the structure is shown in the third diagram of fig. 2, then removing the photoresist on the first layer of metal 3 in the incomplete development area by ashing treatment, wherein the structure is shown in the fourth diagram of fig. 2, removing the gate metal 4 in the incomplete development area by controlling the etching time or selectively etching the liquid medicine, retaining the first layer of metal 3 in the incomplete development area and forming the first electrode 301 in the hole 201, retaining the gate metal 4 and the first layer of metal 3 in the complete development area and forming the gate scanning line 401 and the first metal 302 on the buffer layer 2 outside the hole 201, and finally performing metal lift-off and photoresist stripping cleaning. The first electrode 301 and the first metal 302 are on the buffer layer 2, the first electrode 301 and the first metal 302 have a gap, and the gate scan line 401 is on the first metal 302. The first electrode 301 is used as a first electrode plate of the lower-layer capacitor structure, when the first electrode 301 is formed in the hole 201, the useful first electrode 301 is generally reserved, a part of the first-layer metal 3 on the surface of the buffer layer 2 between the hole 201 and the hole 201 or on the surfaces of the buffer layer 2 around the holes 201 on both sides can also be reserved as the first electrode 301, on one hand, the first electrode 301 on the surface of the buffer layer 2 can be used as a connection point of the capacitor structure and other circuits, for example, parallel connection between the upper-layer capacitor structure and the lower-layer capacitor structure, on the other hand, the first electrode 301 between the hole 201 and the hole 201 can be connected with the capacitor structures in the two holes 201, and therefore, the capacitor capacity is further. The manufacturing method forms a first layer of metal 3 and a grid metal 4 at one time, only the first layer of metal 3 is reserved in a capacitance area to be used as an electrode, and the first layer of metal 3 is made of indium tin oxide which is thin (100 to 1000 angstrom), so that the number of strip-shaped grid-shaped holes is increased, and the capacitance is further improved; and secondly, the indium tin oxide is used as a bridging connection source layer, the source signal line 1001 and the drain electrode 1002, so that the ohmic contact resistance value can be reduced, and the electrical performance of the thin film field effect transistor is improved. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.
After the first electrode, the first metal and the gate scanning line are manufactured, manufacturing a first electrode insulating layer 601, a gate insulating layer 602, a second electrode 701 and a second metal 702; referring to fig. 3, the specific process is to cover the array substrate 1 with the first insulating layer 6, and then continue to plate the second metal layer 7 on the first insulating layer 6, where the second metal layer 7 can be formed by electroplating, evaporation, or sputtering, and the structure is shown in the first diagram of fig. 3. The first insulating layer 6 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like, and the second metal layer 7 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), IGZTO, or the like. The photoresist is patterned by using a half-tone mask 5 having a half-transmissive region 501, a full-transmissive region 502, and a full-opaque region 503. The light transmittance of the semi-light-transmitting region 501 is 50%, the light transmittance of the full-light-transmitting region 502 is 100%, the light transmittance of the full-light-shielding region 503 is 0%, the semi-light-transmitting region 501 corresponds to an incomplete developing region after the photoresist development, the full-light-transmitting region 502 or the full-light-shielding region 503 corresponds to a complete developing region, the incomplete developing region corresponds to a region of the second electrode 701 in the capacitor structure, and the complete developing region corresponds to a region of the second metal 702. When a negative photoresist is coated, the semi-light-transmitting region 501 corresponds to an incomplete developing region, i.e., a region of the second electrode 701 in the capacitor structure, and the fully light-transmitting region 502 corresponds to a complete developing region, i.e., a region of the second metal 702; if a positive photoresist is coated, the semi-light-transmitting region 501 corresponds to an incomplete developing region, i.e., a region of the second electrode 701 in the capacitor structure, and the fully-light-shielding region 503 corresponds to a fully developing region, i.e., a region of the second metal 702. Referring to the second diagram of fig. 3, a positive photoresist is coated on the second metal layer 7, and the photoresist is patterned by using a half-color mask 5 having a semi-transmissive region 501, a fully transmissive region 502 and a fully opaque region 503, wherein the semi-transmissive region 501 corresponds to an incomplete developing region, the incomplete developing region corresponds to a region of the second electrode 701 in the capacitor structure, the fully opaque region 503 corresponds to a full developing region, and the full developing region corresponds to a region of the second metal of the thin film transistor. After developing the photoresist, the photoresist in the incomplete developing area and the area outside the complete developing area is completely removed, and the photoresist in the incomplete developing area is thinner than the photoresist in the complete developing area, and the structure is shown in the third diagram of fig. 3. The second layer of metal 6 is then etched with photoresist and mask in the areas not fully developed and not fully developed leaving the first insulating layer 6, the structure of which is shown in the fourth drawing of fig. 3. Then, the photoresist on the second metal layer 7 in the incomplete development area is removed by ashing, the metal oxide of the capacitor structure is made conductive by hydrogen ion implantation, and the ohmic contact characteristics between the oxide of the thin film transistor and the source signal line 1001 and the drain 1002 are improved, so that the contact resistance is reduced, and the structure is shown in the fifth diagram of fig. 3. After the hydrogen ion implantation, the first insulating layer 6 of the incomplete development area is reserved, a first electrode insulating layer 601 covering the first electrode 301 is formed on the surface of the buffer layer 2 in the hole 201 and between the hole 201 and the hole 201, the second metal layer 7 of the incomplete development area is reserved, a second electrode 701 is formed in the hole 201, the first insulating layer 6 and the second metal layer 7 of the complete development area are reserved, a gate insulating layer 602 and a second metal 702 are formed on the buffer layer 2 outside the hole 201, and finally metal lift-off and photoresist removal cleaning are carried out. When the second electrode 701 is formed in the hole 201, the useful second electrode 701 is generally remained, and a part of the second metal layer 7 on the surface of the buffer layer 2 between the hole 201 and the hole 201 or on the surfaces of the buffer layer 2 around the holes 201 is also remained as the second electrode 701, and the second electrode 701 between the hole 201 and the hole 201 can be connected with the capacitor structures in the two holes 201. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.
The first electrode insulating layer 601 covering the first electrode 301 is used as a dielectric layer of a lower-layer capacitor structure, the first electrode insulating layer 601 realizes the isolation between the first electrode 301 and the second electrode 701 in the lower-layer capacitor structure, so as to avoid the electrical connection between the first electrode 301 and the second electrode 701, the second electrode 701 is arranged on the first electrode insulating layer 601, and the second electrode 601 is used as a common electrode plate of the upper-layer capacitor structure and the lower-layer capacitor structure; the gate insulating layer 602 covers and encloses the gate scan line 401 and the first metal 302, and the second metal 702 is on the gate insulating layer 602 and serves as an active layer of the thin film transistor.
Then, a second electrode insulating layer 801 and a barrier layer 802 are manufactured; referring to fig. 4, a second insulating layer 8 is covered on the array substrate 1, and the second insulating layer 8 and the first insulating layer 6 are made of the same material, such as a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like. Then, the second insulating layer 8 is patterned by photolithography, the second insulating layer 8 is etched by using a photoresist as a mask, two sides of the second metal 702 and two sides of the gate insulating layer are exposed, a barrier layer 802 is formed on the second metal 702, the second insulating layer 8 on the surface of the buffer layer 2 outside the hole 201 is etched to the first electrode 301 by using the photoresist as a mask to form a through hole, the bottom of the through hole is the first electrode 301, a second electrode insulating layer 801 covering the second electrode 701 is formed on the second electrode 701 in the hole 201 and on the surface of the buffer layer 2 between the hole 201 and the hole 201, the second electrode insulating layer 801 is used as a dielectric layer of the upper capacitor structure, and the second electrode insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding electrical connection between the second electrode 701 and the third electrode 901. The first electrode 301 at the bottom of the through hole can be connected with the third electrode 901, so as to realize the connection between the upper layer capacitor structure and the lower layer capacitor structure. After the second electrode insulating layer 801 and the barrier layer 802 are formed, the photoresist is removed. In some embodiments, the blocking layer 802 on the second metal 702 does not need to be fabricated, and can be designed as a BCE tft if necessary, so that a mask can be omitted, as shown in fig. 5.
After the second electrode insulating layer 801 and the barrier layer 802 are manufactured, a third electrode 901, a third metal 903, a source signal line 1001 and a drain 1002 are manufactured; referring to fig. 6, a third layer of metal 9 is deposited, a third metal 902 is formed on the second metal 702 and the barrier layer 802, a third electrode 9 is formed in the hole 201, a portion of the third layer of metal 9 on the surface of the buffer layer 2 between the hole 201 and the hole 201 or on the surfaces of the buffer layer 2 around the hole 201 is also reserved as a third electrode 901, the third electrode 901 can be connected with the first electrode 301 through the via hole of the second electrode insulating layer 802 on the first electrode 301, and after the third electrode 901 is connected with the first electrode 301, the parallel connection of the upper capacitor structure and the lower capacitor structure is realized. The manufacturing method can directly use metal as the electrode of the capacitor structure, and can simplify the process.
A third metal 902 wraps around the second metal 702 and both sides of the barrier layer 802 on the barrier layer 802, and the third metal 902 exposes a central portion of the barrier layer 802, i.e., the third metal 902 has two portions. After the third metal 902 is manufactured, a fourth layer of metal 10 is deposited, where the fourth layer of metal 10 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), or IGZTO, a source signal line 1001 is formed on one side of the third metal 902, a drain 1002 is formed on the other side of the third metal 902, and a gap is formed between the source signal line 1001 and the drain 1002, as shown in fig. 6. After the third electrode 901, the source signal line 1001 and the drain 1002 are manufactured, the metal is lifted off and the photoresist is removed for cleaning.
In order to protect the capacitor structure and avoid direct contact between an external structure and the capacitor structure as well as the thin film field effect transistor, the manufacturing method also carries out the manufacturing of a passivation layer 1100; referring to fig. 7, a passivation layer 1100 may be deposited by a chemical vapor deposition method, where the passivation layer 1100 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, and the like, and after the passivation layer 1100 is covered, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film transistor are not contacted.
Referring to fig. 8 to 9, the capacitor with a three-dimensional grid structure of the present invention can effectively reduce the occupied area of the capacitor area compared to the conventional flat-plate capacitor, and reduce the size of the capacitor while maintaining the same capacitance; the metal oxide is reserved in the array substrate capacitor area and is conducted to be used as a capacitor electrode, so that the ohmic contact characteristic is improved, the contact resistance is reduced, two groups of parallel capacitors with excellent performance are formed, and the number of the parallel capacitors is further increasedLarge capacitance capacity. Referring to fig. 8, according to the parallel capacitance formula C, when the capacitance is equal to C1+ C2 (C1 and C2 are upper and lower capacitor structures), the actual occupied area of the gate capacitor is further reduced by 50% compared with the theoretical capacitance area of the plate; referring to fig. 9, the capacitance area S of the grid capacitor is (S1+ S2+ S3+ S4) × n, and occupies the area SFruit of Chinese wolfberryWhen the storage capacity is equal to (S1 '+ S2+ S3+ S4')/n, the triangular function S1 '═ Sin α × S1, and S1' ═ S2 ═ S3, Taper α ═ 60 °, the area actually occupied by the grid capacitor can be reduced by 33% compared with the area occupied by the flat capacitor.
The first layer of metal and the grid metal are formed at one time, and only indium tin oxide (material of the first layer of metal) is reserved in the capacitor area to be used as an electrode, wherein the indium tin oxide is thin (100-1000 angstrom), so that the number of strip-shaped grid-shaped holes is increased, and the capacitor capacity is further improved. And secondly, the indium tin oxide is used as a bridging connection to connect the active layer with the source electrode and the drain electrode, so that the ohmic contact resistance value can be reduced, and the electrical property of the thin film field effect transistor is improved. The electrode area of the manufacturing method can also directly use metal as an electrode plate, so that the process can be simplified.
The present invention provides an array substrate having a high capacitance structure, as shown in fig. 1, 4 to 9, the array substrate having a high capacitance structure of the present embodiment may be manufactured according to the above method. The array substrate having a high capacitance structure includes: the array substrate 1 is provided with a buffer layer 2, and the buffer layer 2 is made of one or more of organic photosensitive materials, polyimide films (PI), silicon oxide composite films (SiOx), silicon nitride composite films (SiNx) and titanium oxide. A plurality of holes 201 are formed on the buffer layer 2, and the structure is shown in fig. 1. The cross section of the hole 201 of the present invention may be rectangular, circular, or other irregular shapes, and the structure is as shown in fig. 6, for example, the cross section of the hole 201 with a bar-shaped grid structure is rectangular, and the width of the cross section is gradually reduced from top to bottom, the width of the hole bottom is smaller than the width of the hole opening, and grid-shaped capacitor structures are disposed in the hole 201 and between the hole 201 and the hole 201. A thin film field effect transistor is provided on the buffer layer 2 outside the hole 201.
Referring to fig. 4, a first electrode is sequentially disposed in the hole 201 and between the hole 201 and the hole 201A pole 301, a first electrode insulating layer 601, and a second electrode 701; the first electrode 301 is used as a polar plate of a lower-layer capacitor structure, the first electrode insulating layer 601 covers the first electrode 301 and is used as a dielectric layer of the lower-layer capacitor structure, and the second electrode is arranged on the first electrode insulating layer and is used as a common polar plate of an upper-layer capacitor structure and a lower-layer capacitor structure; the second electrode insulating layer covers the second electrode and serves as a dielectric layer of the upper-layer capacitor structure, and the first electrode insulating layer 601 realizes isolation between the first electrode 301 and the second electrode 701 in the lower-layer capacitor structure, so that electrical connection between the first electrode 301 and the second electrode 701 is avoided. The first electrode 301, the first electrode insulating layer 601 and the second electrode 701 constitute a lower capacitor structure. Because the first electrode 301 and the second electrode 701 on the two sides of the inner wall of the hole are grid-shaped planes, the area of metal can be greatly increased, and therefore a larger capacitance value can be realized. While reducing the parasitic capacitance impact and the required semiconductor device area. Referring to fig. 9, the capacitance area S of the grid capacitor is (S1+ S2+ S3+ S4) × n, and occupies the area SFruit of Chinese wolfberryWhen the capacitance is equal to (S1 '+ S2+ S3+ S4')/n, and according to the trigonometric function S1 '═ Sin α × S1, if S1' ═ S2 ═ S3 and Taper α ═ 60 °, the actual occupied area of the grid capacitor can be reduced by 33% compared with the conventional plate capacitor.
The first electrode 301 is indium tin oxide, and the indium tin oxide is thin (100 to 1000 angstrom), so that the quantity of the first electrode 301 is increased, and the capacitance capacity is further increased; and secondly, the indium tin oxide is used as a bridging connection source layer, the source signal line 1001 and the drain electrode 1002, so that the ohmic contact resistance value can be reduced, and the electrical performance of the thin film field effect transistor is improved. The first electrode insulating layer 601 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like.
Referring to fig. 6, a second electrode insulating layer 801 and a third electrode 901 are sequentially disposed in the hole 201 and between the hole 201 and the hole 201; the second electrode insulating layer 801 covers the second electrode 701 and serves as a dielectric layer of the upper capacitor structure, the third electrode 901 is arranged on the second electrode insulating layer 801 and serves as an electrode plate of the upper capacitor structure, and the first electrode insulating layer 601, the second electrode insulating layer 801 and the second electrode 701 on the surface of the buffer layer 2 are exposed out of the first electrode 301 below. The second electrode insulating layer 801 realizes isolation between the second electrode 701 and the third electrode 901 in the upper capacitor structure, thereby avoiding electrical connection between the second electrode 701 and the third electrode 901. The second electrode 701, the second electrode insulating layer 801, and the third electrode 901 form a lower capacitor structure. The second electrode 701 and the third electrode 901 on the two sides of the inner wall of the hole are grid-shaped planes, so that the area of metal can be greatly increased, and a larger capacitance value can be realized. The first electrode 301 and the third electrode 901 on the surface of the buffer layer 2 are connected to realize parallel connection of the upper and lower capacitor structures, and referring to fig. 8, when the parallel capacitance formula C is C1+ C2, (C1, C2 are the upper and lower capacitor structures) is that the holding capacities are equal, the actual occupied area of the gate capacitor can be further reduced by 50% compared with the theoretical capacitor area of the flat plate.
Referring to fig. 6, a thin film field effect semiconductor is disposed on the buffer layer 2 outside the hole 201, and includes: a first metal 302 is arranged on the buffer layer 2 outside the hole 201, and the first metal 302 is indium tin oxide; a gate scan line 401 is provided over the first metal 302, and the gate scan line 401 is made of one or more metals having excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, and chromium, or other alloys.
A gate insulating layer 602 is disposed on the gate scan line 401, the gate insulating layer 602 covers and wraps the gate scan line 401 and the first metal 302, and the gate insulating layer 602 is a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide, aluminum oxide, or the like.
A second metal 702 is provided on the gate insulating layer 602, and the second metal 702 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), IGZTO, or the like; a barrier layer 802 is disposed over the second metal 702, the second metal 702 being over the gate insulating layer 602 and acting as an active layer for the thin film field effect transistor. In some embodiments, the barrier layer may not be provided and the structure is shown in FIG. 5.
A third metal 902 is disposed on the barrier layer 802, the third metal 902 is a metal oxide such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), or IGZTO, the third metal 903 wraps two sides of the second metal 702 and the barrier layer 802, the third metal 902 exposes a central portion of the barrier layer 802, a source signal line 1001 is disposed on one side of the third metal 902, a drain 1002 is disposed on the other side of the third metal 903, the source signal line 1001 and the drain 1002 are metal oxides such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), or IGZTO, and the source signal line 1001 and the drain 1002 have a gap, as shown in fig. 6.
In order to protect the capacitor structure and prevent an external structure from being in direct contact with the capacitor structure and the thin film field effect transistor, a passivation layer 1100 is arranged on the capacitor region and the thin film field effect transistor, and the passivation layer 1100 is made of materials such as a silicon oxide composite film (SiOx), a silicon nitride composite film (SiNx), titanium oxide and aluminum oxide. The passivation layer 1100 covers the third metal 902, the barrier layer 802, the gate insulating layer 602, the third electrode 901, and the like, and after the passivation layer 1100 is covered, only the passivation layer 1100 is contacted from the outside, and the capacitor structure and the thin film transistor are not contacted.
It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.
Claims (10)
1. A manufacturing method of an array substrate with a high-capacitance structure is characterized by comprising the following steps:
manufacturing a buffer layer on the array substrate;
making holes on the buffer layer;
depositing a first layer of metal, and forming a first electrode in the hole, wherein the first electrode is used as a polar plate of a lower-layer capacitor structure;
after covering the first insulating layer, continuously depositing a second layer of metal, forming a first electrode insulating layer covering the first electrode in the hole, forming a second electrode on the first electrode insulating layer in the hole, wherein the second electrode is used as a common electrode plate of the upper-layer and lower-layer capacitor structures;
covering the second insulating layer, and forming a second electrode insulating layer covering the second electrode in the hole;
depositing a third layer of metal, and forming a third electrode on the second insulating layer in the hole, wherein the third electrode is used as a polar plate of the upper-layer capacitor structure;
and a thin film field effect transistor is also arranged on the buffer layer outside the hole.
2. The method for manufacturing the array substrate with the high-capacitance structure according to claim 1, further comprising the following steps:
extending the first electrode in the hole to the surface of the buffer layer when depositing the first layer of metal; or: after covering the first insulating layer, extending the second electrode and the first electrode insulating layer in the hole to the surface of the buffer layer outside the hole when continuously depositing the second layer of metal; or: when covering the second insulating layer, extending the second electrode insulating layer in the hole to the surface of the buffer layer outside the hole: or: extending the third electrode in the hole to the surface of the buffer layer outside the hole when depositing the third layer of metal; or: connecting the third electrode on the face of the outer buffer layer of the hole with the first electrode on the face of the outer buffer layer of the hole.
3. The method for manufacturing the array substrate with the high-capacitance structure according to claim 2, wherein the thin film transistor is manufactured by the following steps:
after depositing the first layer of metal, continuing to deposit gate metal, and forming a first metal and a gate scanning line on the buffer layer outside the hole, wherein the first metal is on the buffer layer outside the hole, and the gate scanning line is on the first metal;
after covering the first insulating layer, continuously depositing a second layer of metal, forming a grid electrode insulating layer on the grid electrode scanning line, covering and wrapping the grid electrode scanning line and the first metal by the grid electrode insulating layer, and forming a second metal on the grid electrode insulating layer;
forming a barrier layer on the second metal while covering the second insulating layer;
when depositing a third layer of metal, forming a third metal wrapping the second metal and two sides of the barrier layer on the barrier layer, wherein the third metal is exposed out of the central part of the barrier layer;
and depositing a fourth layer of metal, forming a source signal line on one side of the third metal, and forming a drain on the other side of the third metal.
4. The method as claimed in claim 3, further comprising the following steps when continuing to deposit the gate metal after depositing the first metal layer:
coating a photoresist on the gate metal, patterning the photoresist by using a half-color mask with a semi-transparent region, a full-transparent region and a full-shading region, wherein the semi-transparent region corresponds to an incomplete developing region after the photoresist is developed, the full-transparent region or the full-shading region corresponds to the complete developing region, the incomplete developing region corresponds to a region of a first electrode in the capacitor structure, and the complete developing region corresponds to a region of a gate scanning line;
etching the gate metal and the first layer of metal on the areas outside the complete development area and the incomplete development area by using the photoresist as a mask;
removing the photoresist on the first layer of metal in the incomplete developing area through ashing treatment, and reserving the photoresist on the gate metal in the complete developing area;
etching the gate metal in the incomplete developing area to the first layer of metal, reserving the first layer of metal as a first electrode, and removing the photoresist on the complete developing area to form the first metal and a gate scanning line.
5. The method as claimed in claim 3, further comprising the following steps when continuing to deposit the second metal layer after covering the first insulating layer:
coating a photoresist on the second layer of metal, patterning the photoresist by using a half-color mask plate with a semi-transparent area, a full-transparent area and a full-light-shielding area, wherein the semi-transparent area corresponds to an incomplete developing area after the photoresist is developed, the full-transparent area or the full-light-shielding area corresponds to the complete developing area, the incomplete developing area corresponds to the area of the second electrode in the capacitor structure, and the complete developing area corresponds to the area of the second metal;
etching the second layer of metal on the incomplete developing area and the area outside the complete developing area, removing photoresist on the second layer of metal in the incomplete developing area through ashing treatment, then, injecting hydrogen ions, removing photoresist on the first insulating layer material in the complete developing area, reserving the second layer of metal and the first insulating layer in the incomplete developing area as a second electrode and a first electrode insulating layer respectively, and reserving the second layer of metal and the first insulating layer in the complete developing area as a second metal and a grid electrode insulating layer respectively.
6. The method for manufacturing the array substrate with the high-capacitance structure according to claim 1, 2 or 3, further comprising the following steps:
and covering a third insulating layer material, and forming a passivation layer on the third electrode of the capacitor structure and the third metal of the thin film field effect transistor, wherein the passivation layer protects the capacitor structure and the thin film field effect transistor.
7. The method as claimed in claim 1, 2 or 3, wherein the first metal layer is indium tin oxide.
8. An array substrate with a high-capacitance structure, wherein the array substrate with the high-capacitance structure is manufactured by the manufacturing method of any one of claims 1 to 7.
9. An array substrate having a high capacitance structure, comprising:
the array substrate is provided with a buffer layer, the buffer layer is provided with holes, and the buffer layer outside the holes is provided with a thin film field effect transistor;
a first electrode, a first electrode insulating layer, a second electrode insulating layer and a third electrode are sequentially arranged in the hole and on the surface of the buffer layer between the hole and the hole, the first electrode is used as a polar plate of a lower-layer capacitor structure, the first electrode insulating layer covers the first electrode and is used as a dielectric layer of the lower-layer capacitor structure, the second electrode is arranged on the first electrode insulating layer and is used as a shared polar plate of an upper-layer capacitor structure, the second electrode insulating layer covers the second electrode and is used as a dielectric layer of an upper-layer capacitor structure, and the third electrode is arranged on the second electrode insulating layer and is used as a polar plate of the upper-layer capacitor structure.
10. The array substrate with a high capacitance structure as claimed in claim 9, wherein the thin film transistor comprises:
a first metal is arranged on the buffer layer outside the hole, and a grid scanning line is arranged on the first metal;
a grid electrode insulation layer is arranged on the grid electrode scanning line, and covers and wraps the grid electrode scanning line and the first metal;
a second metal is arranged on the grid electrode insulating layer, and a barrier layer is arranged on the second metal;
and a third metal is arranged on the barrier layer, wraps the second metal and the two sides of the barrier layer, is exposed out of the center part of the barrier layer, is provided with a source signal line on one side and is provided with a drain on the other side.
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| CN102916014A (en) * | 2011-08-01 | 2013-02-06 | 三星显示有限公司 | Thin-film transistor array substrate, organic light-emitting display having the same, and method of manufacturing the organic light-emitting display |
| CN104218041A (en) * | 2014-08-15 | 2014-12-17 | 京东方科技集团股份有限公司 | Array substrate and production method thereof and display device |
| CN210668373U (en) * | 2019-11-19 | 2020-06-02 | 福建华佳彩有限公司 | Array substrate with high-capacitance structure |
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| CN101359136A (en) * | 2007-07-31 | 2009-02-04 | 北京京东方光电科技有限公司 | TFT LCD array substrate structure and method for manufacturing same |
| US20110278565A1 (en) * | 2010-05-12 | 2011-11-17 | Hoon Yim | Oxide thin film transistor and method of fabricating the same |
| CN102916014A (en) * | 2011-08-01 | 2013-02-06 | 三星显示有限公司 | Thin-film transistor array substrate, organic light-emitting display having the same, and method of manufacturing the organic light-emitting display |
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