CN112909025A - Array substrate and preparation method thereof - Google Patents
Array substrate and preparation method thereof Download PDFInfo
- Publication number
- CN112909025A CN112909025A CN202110177349.2A CN202110177349A CN112909025A CN 112909025 A CN112909025 A CN 112909025A CN 202110177349 A CN202110177349 A CN 202110177349A CN 112909025 A CN112909025 A CN 112909025A
- Authority
- CN
- China
- Prior art keywords
- layer
- electrode
- electrode layer
- glass substrate
- etching barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 83
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000002184 metal Substances 0.000 claims abstract description 83
- 239000011521 glass Substances 0.000 claims abstract description 54
- 238000002161 passivation Methods 0.000 claims abstract description 52
- 230000004888 barrier function Effects 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000003990 capacitor Substances 0.000 claims abstract description 43
- 239000000463 material Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 5
- 230000008020 evaporation Effects 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 229910004205 SiNX Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 4
- 229920001621 AMOLED Polymers 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- -1 IGZO Chemical class 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Images
Classifications
-
- H01L27/1255—
-
- H01L27/1225—
-
- H01L27/1259—
-
- H01L28/75—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention relates to the technical field of array substrates, in particular to an array substrate and a preparation method thereof, the array substrate comprises a glass substrate and a buffer layer arranged on one side surface of the glass substrate, at least one groove is arranged on a capacitance area on one side surface of the buffer layer far away from the glass substrate, a first electrode layer is filled in the groove, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side surface of the first electrode layer far away from the buffer layer, a grid metal layer, a grid insulating layer, an active layer, a second etching barrier layer, a source drain electrode metal layer and a second passivation layer are sequentially stacked and covered on a TFT area on one side surface of the buffer layer far away from the glass substrate, the material of the first electrode layer is the same as that of the grid metal layer, the material of the third electrode, meanwhile, the occupied area of the capacitor can be reduced.
Description
Technical Field
The invention relates to the technical field of array substrates, in particular to an array substrate and a preparation method thereof.
Background
With the development of active matrix organic light emitting diode displays (AMOLEDs) and high performance Active Matrix Liquid Crystal Displays (AMLCDs), in order to obtain high resolution and high frame rate displays, how to design and fabricate high performance and small size array substrate structures is an increasingly challenging research topic.
IGZO is an amorphous oxide containing indium, gallium and zinc, the carrier mobility is 20-30 times of that of amorphous silicon, the charge and discharge rate of a TFT (Thin Film Transistor, english is called a Thin Film Transistor) to a pixel electrode can be greatly increased, the response speed of a pixel is increased, the panel refresh rate is higher, and an ultrahigh-resolution display panel can be realized. Meanwhile, the existing amorphous silicon production line can be compatible with the IGZO process only by slightly changing, so that the cost is more competitive than that of low-temperature polycrystalline silicon (LTPS).
The oxide semiconductor mobility (10-30 cm2/V.s) can meet the driving requirement of the AMOLED display array substrate, the IGZO TFT device has a better Ioff compared with a low-temperature polysilicon TFT, the pixel TFT can inhibit the electric leakage problem only by a single grid electrode, the miniaturization of the TFT device is facilitated, and the manufacturing of the ultra-high resolution TFT substrate is realized. Therefore, the high-resolution OLED display matched with the IGZO TFT drive circuit has good market prospect and is a research and development hotspot of main panel manufacturing factories at home and abroad at present.
The GOA technology (GOA: Gate Driver IC on Array) is a new type of panel development in recent years, which directly etches the IC driving the Gate signal on the panel, and saves the cost of the Gate Driver IC and the process of binding the IC on the panel, and more importantly, because the Gate Driver IC and the display panel are integrated, the product is thinner, the resolution is higher, and the stability and the vibration resistance are better. At present, the GOA technology has become the mainstream of the mobile terminal industry, and smart phones almost use the liquid crystal panel.
In order to make the driving circuit have a better voltage stabilizing effect in the array substrate, a capacitor with a larger capacity is usually required to be arranged, which causes the occupied area of the driving circuit to be larger, and the frame size and the pixel size of the display panel cannot be further reduced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: an array substrate capable of improving capacitance capacity and a method for manufacturing the same are provided.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
an array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side face, away from the buffer layer, of the first electrode layer;
a gate metal layer, a gate insulating layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer are sequentially stacked and covered on a TFT (thin film transistor) region on one side face, far away from the glass substrate, of the buffer layer, wherein a first through hole is formed in the source drain metal layer, and the second passivation layer is filled in the first through hole;
the material of the first electrode layer is the same as that of the grid metal layer;
the material of the second electrode layer is the same as that of the active layer;
and the material of the third electrode layer is the same as that of the source drain electrode metal layer.
The second technical scheme adopted by the invention is as follows:
a preparation method of an array substrate comprises the following steps:
s1, providing a glass substrate, wherein the surface of the glass substrate is covered with a buffer layer; forming at least one groove in a capacitor area on one side surface of the buffer layer, which is far away from the glass substrate;
s2, forming a first electrode layer and a grid electrode metal layer, wherein the first electrode layer is filled in the groove, and the grid electrode metal layer covers the TFT area on one side face, far away from the glass substrate, of the buffer layer;
s3, forming a first insulating layer and a grid insulating layer, wherein the first insulating layer covers the surface of the first electrode layer, and the grid insulating layer covers the surface of the grid metal layer;
s4, forming a second electrode layer and an active layer, wherein the second electrode layer covers the surface of the first insulating layer, and the active layer covers the surface of the gate insulating layer;
s5, forming a first etching barrier layer and a second etching barrier layer, wherein the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the active layer;
s6, forming a third electrode layer and a source drain metal layer, wherein the third electrode layer covers the surface of the first etching barrier layer, and the source drain metal layer covers the surface of the second etching barrier layer; forming a first through hole in the source drain metal layer;
and S7, forming a first passivation layer and a second passivation layer, wherein the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source and drain electrode metal layer, and the first via holes are filled with the second passivation layer.
The invention has the beneficial effects that:
the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT region of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a grid metal layer, a grid insulation layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the grid metal layer, the material of the third electrode layer is the same as that of the source drain metal layer, the first electrode layer is made of the same material as that of the grid metal layer, the third electrode layer is made of the same material as that of the source drain metal layer, the capacity of the capacitor can be further improved while the photomask is saved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of.
Drawings
Fig. 1 is a schematic structural diagram of an array substrate according to the present invention;
FIG. 2 is a flowchart illustrating a method for fabricating an array substrate according to the present invention;
description of reference numerals:
1. a glass substrate;
2. a buffer layer;
3. a capacitive region; 31. a first electrode layer; 32. a first insulating layer; 33. a second electrode layer; 34. a first etch stop layer; 35. a third electrode layer; 36. a first passivation layer;
4. a TFT region; 41. a gate metal layer; 42. a gate insulating layer; 43. an active layer; 44. a second etch stop layer; 45. a source drain metal layer; 46. a second passivation layer.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, a technical solution provided by the present invention:
an array substrate comprises a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side face, away from the buffer layer, of the first electrode layer;
a gate metal layer, a gate insulating layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer are sequentially stacked and covered on a TFT (thin film transistor) region on one side face, far away from the glass substrate, of the buffer layer, wherein a first through hole is formed in the source drain metal layer, and the second passivation layer is filled in the first through hole;
the material of the first electrode layer is the same as that of the grid metal layer;
the material of the second electrode layer is the same as that of the active layer;
and the material of the third electrode layer is the same as that of the source drain electrode metal layer.
From the above description, the beneficial effects of the present invention are:
the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT region of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a grid metal layer, a grid insulating layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the grid metal layer, the material of the third electrode layer is the same as that of the source drain metal layer, the first electrode layer is made of the same material as that of the grid metal layer, and the third electrode layer is made of the same material as that of the source drain metal layer.
Further, the thickness range of the first electrode layer is
As can be seen from the above description, the thickness of the first electrode layer ranges from
The capacitance capacity can be further improved.
Further, the first electrode layer in the groove is in contact with the glass substrate.
Further, the vertical cross section of the groove is square.
Referring to fig. 2, another technical solution provided by the present invention:
a preparation method of an array substrate comprises the following steps:
s1, providing a glass substrate, wherein the surface of the glass substrate is covered with a buffer layer; forming at least one groove in a capacitor area on one side surface of the buffer layer, which is far away from the glass substrate;
s2, forming a first electrode layer and a grid electrode metal layer, wherein the first electrode layer is filled in the groove, and the grid electrode metal layer covers the TFT area on one side face, far away from the glass substrate, of the buffer layer;
s3, forming a first insulating layer and a grid insulating layer, wherein the first insulating layer covers the surface of the first electrode layer, and the grid insulating layer covers the surface of the grid metal layer;
s4, forming a second electrode layer and an active layer, wherein the second electrode layer covers the surface of the first insulating layer, and the active layer covers the surface of the gate insulating layer;
s5, forming a first etching barrier layer and a second etching barrier layer, wherein the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the active layer;
s6, forming a third electrode layer and a source drain metal layer, wherein the third electrode layer covers the surface of the first etching barrier layer, and the source drain metal layer covers the surface of the second etching barrier layer; forming a first through hole in the source drain metal layer;
and S7, forming a first passivation layer and a second passivation layer, wherein the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source and drain electrode metal layer, and the first via holes are filled with the second passivation layer.
From the above description, the beneficial effects of the present invention are:
the capacitor comprises a buffer layer, a glass substrate, a capacitor body and a first electrode layer, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially overlapped on one side face, far away from the buffer layer, of the first electrode layer, the second electrode layer, the third electrode layer and the first passivation layer are respectively used as electrode layers of the capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor; the TFT region of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a grid metal layer, a grid insulation layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the grid metal layer, the material of the third electrode layer is the same as that of the source drain metal layer, the first electrode layer is made of the same material as that of the grid metal layer, the third electrode layer is made of the same material as that of the source drain metal layer, the capacity of the capacitor can be further improved while the photomask is saved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of.
Further, the thickness range of the first electrode layer is
As can be seen from the above description, the thickness of the first electrode layer ranges from
The capacitance capacity can be further improved.
Further, the first electrode layer in the groove is in contact with the glass substrate.
Further, the vertical cross section of the groove is square.
Referring to fig. 1, a first embodiment of the present invention is:
an array substrate comprises a glass substrate 1 and a buffer layer 2 arranged on one side face of the glass substrate 1, wherein at least one groove is formed in a capacitor area 3 on one side face, far away from the glass substrate 1, of the buffer layer 2, a first electrode layer 31 is filled in the groove, and a first insulating layer 32, a second electrode layer 33, a first etching barrier layer 34, a third electrode layer 35 and a first passivation layer 36 are sequentially laminated and covered on one side face, far away from the buffer layer 2, of the first electrode layer 31;
a gate metal layer 41, a gate insulating layer 42, an active layer 43, a second etching barrier layer 44, a source and drain metal layer 45 and a second passivation layer 46 are sequentially stacked and covered on the TFT region 4 on one side surface of the buffer layer 2, which is far away from the glass substrate 1, wherein a first through hole is formed in the source and drain metal layer 45, and the second passivation layer 46 is filled in each first through hole;
the material of the first electrode layer 31 is the same as that of the gate metal layer 41;
the material of the second electrode layer 33 is the same as that of the active layer 43;
the material of the third electrode layer 35 is the same as that of the source/drain metal layer 45.
The thickness range of the first electrode layer 31 is
Preferably, it is
The first electrode layer 31 in the recess is in contact with the glass substrate 1.
The vertical cross section of the groove is square.
The thickness range of the buffer layer 2 is 0.2-3 μm, preferably 2 μm; the buffer layer 2 can be made of organic photosensitive materials, PI, SiOx, SiNx, titanium oxide and the like;
the thickness range of the first electrode layer 31 is
Preferably, it is
The first electricityThe electrode layer 31 and the gate metal layer 41 are made of the same material, and can be made of one or more of metals with excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and the like, and alloys;
the thickness of the first insulating layer 32 is in the range of
Preferably, it is
The first insulating layer 32 and the gate insulating layer 42 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;
the thickness range of the second electrode layer 33 is
Preferably, it is
The second electrode layer 33 and the active layer 43 are made of the same material, and may be made of metal oxide such as IGZO, IZO, IGZTO, etc.;
the third electrode layer 35 and the source/drain metal layer 45 are made of the same material, and can be made of one or more of aluminum, molybdenum, titanium, nickel, copper, silver, chromium and other metals with excellent conductivity, and alloys;
the first etch stop layer 48 has a thickness in the range of
Preferably, it is
The thickness of the second etch stop layer 35 ranges from
Preferably, it is
The first etch stop layer 34 and the second etch stop layer 44 are made of the same material, and may be selected from SiOx, SiNx, titanium oxide, and the like,Alumina, etc.;
the thickness of the first passivation layer 36 ranges from
Preferably, it is
The first passivation layer 36 and the second passivation layer 46 are made of the same material, and may be made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;
in the actual process, the first electrode layer 31 and the gate metal layer 41 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;
the first insulating layer 32 and the gate insulating layer 42 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;
the second electrode layer 33 and the active layer 43 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;
the first etching barrier layer 34 and the second etching barrier layer 44 are the same film layer distributed in different areas, and are formed simultaneously during the evaporation process;
the third electrode layer 35 and the source/drain metal layer 45 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;
the first passivation layer 36 and the second passivation layer 46 are the same film layer distributed in different regions, and are formed simultaneously during the evaporation process;
according to the array substrate designed by the scheme, under the condition that the capacity is kept equal, the actually occupied area of the three-dimensional grid-shaped capacitor is smaller than that of a flat capacitor, and the theoretical capacitor area can be further reduced by 50%.
Referring to fig. 2, the second embodiment of the present invention is:
a preparation method of an array substrate comprises the following steps:
s1, providing a glass substrate 1, and covering a buffer layer 2 on the surface of the glass substrate 1; at least one groove is formed in a capacitor area 3 on one side surface of the buffer layer 2 away from the glass substrate 1;
s2, forming a first electrode layer 31 and a gate metal layer 41, wherein the first electrode layer 31 is filled in the groove, and the gate metal layer 41 covers the TFT region 4 on one side surface of the buffer layer 2 away from the glass substrate 1;
s3, forming a first insulating layer 32 and a gate insulating layer 42, wherein the first insulating layer 32 covers the surface of the first electrode layer 31, and the gate insulating layer 42 covers the surface of the gate metal layer 41;
s4, forming a second electrode layer 33 and an active layer 43, wherein the second electrode layer 33 covers the surface of the first insulating layer 32, and the active layer 43 covers the surface of the gate insulating layer 42;
s5, forming a first etching barrier layer 34 and a second etching barrier layer 44, wherein the first etching barrier layer 34 covers the surface of the second electrode layer 33, and the second etching barrier layer 44 covers the surface of the active layer 43;
s6, forming a third electrode layer 35 and a source and drain electrode metal layer 45, wherein the third electrode layer 35 covers the surface of the first etching barrier layer 34, and the source and drain electrode metal layer 45 covers the surface of the second etching barrier layer 44; forming a first via hole in the source-drain metal layer 45;
and S7, forming a first passivation layer 36 and a second passivation layer 46, wherein the first passivation layer 36 covers the surface of the third electrode layer 35, the second passivation layer 46 covers the surface of the source and drain electrode metal layer 45, and the first via holes are filled with the second passivation layer 46.
The thickness range of the first electrode layer 31 is
Preferably, it is
The first electrode layer 31 in the recess is in contact with the glass substrate 1.
The vertical cross section of the groove is square.
In summary, according to the array substrate and the preparation method thereof provided by the invention, at least one groove is formed in a capacitor area on one side surface of the buffer layer away from the glass substrate, the groove is filled with the first electrode layer, a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially stacked and covered on one side surface of the first electrode layer away from the buffer layer, the first electrode layer, the second electrode layer and the third electrode layer are respectively used as electrode layers of a capacitor, the first electrode layer, the first insulating layer and the second electrode layer form a capacitor, and the second electrode layer, the first etching barrier layer and the third electrode layer form a capacitor to form two capacitors connected in parallel, so that the capacitance capacity of the capacitor is further increased; the TFT region of one side of the buffer layer far away from the glass substrate is sequentially laminated and covered with a grid metal layer, a grid insulation layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer, the material of the first electrode layer is the same as that of the grid metal layer, the material of the third electrode layer is the same as that of the source drain metal layer, the first electrode layer is made of the same material as that of the grid metal layer, the third electrode layer is made of the same material as that of the source drain metal layer, the capacity of the capacitor can be further improved while the photomask is saved, meanwhile, the occupied area of the capacitor can be reduced, and the PPI of the panel is improved, and the frame size of.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (8)
1. The array substrate is characterized by comprising a glass substrate and a buffer layer arranged on one side face of the glass substrate, wherein at least one groove is formed in a capacitor area on one side face, far away from the glass substrate, of the buffer layer, a first electrode layer is filled in the groove, and a first insulating layer, a second electrode layer, a first etching barrier layer, a third electrode layer and a first passivation layer are sequentially laminated and covered on one side face, far away from the buffer layer, of the first electrode layer;
a gate metal layer, a gate insulating layer, an active layer, a second etching barrier layer, a source drain metal layer and a second passivation layer are sequentially stacked and covered on a TFT (thin film transistor) region on one side face, far away from the glass substrate, of the buffer layer, wherein a first through hole is formed in the source drain metal layer, and the second passivation layer is filled in the first through hole;
the material of the first electrode layer is the same as that of the grid metal layer;
the material of the second electrode layer is the same as that of the active layer;
and the material of the third electrode layer is the same as that of the source drain electrode metal layer.
2. The array substrate of claim 1, wherein the first electrode layer has a thickness in a range of
3. The array substrate of claim 1, wherein the first electrode layer in the groove is in contact with a glass substrate.
4. The array substrate of claim 1, wherein the vertical cross-sectional shape of the groove is square.
5. The method for preparing the array substrate of claim 1, comprising the following steps:
s1, providing a glass substrate, wherein the surface of the glass substrate is covered with a buffer layer; forming at least one groove in a capacitor area on one side surface of the buffer layer, which is far away from the glass substrate;
s2, forming a first electrode layer and a grid electrode metal layer, wherein the first electrode layer is filled in the groove, and the grid electrode metal layer covers the TFT area on one side face, far away from the glass substrate, of the buffer layer;
s3, forming a first insulating layer and a grid insulating layer, wherein the first insulating layer covers the surface of the first electrode layer, and the grid insulating layer covers the surface of the grid metal layer;
s4, forming a second electrode layer and an active layer, wherein the second electrode layer covers the surface of the first insulating layer, and the active layer covers the surface of the gate insulating layer;
s5, forming a first etching barrier layer and a second etching barrier layer, wherein the first etching barrier layer covers the surface of the second electrode layer, and the second etching barrier layer covers the surface of the active layer;
s6, forming a third electrode layer and a source drain metal layer, wherein the third electrode layer covers the surface of the first etching barrier layer, and the source drain metal layer covers the surface of the second etching barrier layer; forming a first through hole in the source drain metal layer;
and S7, forming a first passivation layer and a second passivation layer, wherein the first passivation layer covers the surface of the third electrode layer, the second passivation layer covers the surface of the source and drain electrode metal layer, and the first via holes are filled with the second passivation layer.
6. The method for preparing the array substrate of claim 5, wherein the thickness of the first electrode layer is in the range of
7. The method for preparing the array substrate of claim 5, wherein the first electrode layer in the groove is in contact with the glass substrate.
8. The method of claim 5, wherein the vertical cross-sectional shape of the groove is square.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110177349.2A CN112909025A (en) | 2021-02-09 | 2021-02-09 | Array substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110177349.2A CN112909025A (en) | 2021-02-09 | 2021-02-09 | Array substrate and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112909025A true CN112909025A (en) | 2021-06-04 |
Family
ID=76123036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110177349.2A Pending CN112909025A (en) | 2021-02-09 | 2021-02-09 | Array substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112909025A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4362632A1 (en) * | 2022-10-25 | 2024-05-01 | Samsung Display Co., Ltd. | Display device, flexible display device, and manufacturing method for display device |
-
2021
- 2021-02-09 CN CN202110177349.2A patent/CN112909025A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4362632A1 (en) * | 2022-10-25 | 2024-05-01 | Samsung Display Co., Ltd. | Display device, flexible display device, and manufacturing method for display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11289518B2 (en) | Array substrate and method for making same | |
| US9589995B2 (en) | TFT substrate having three parallel capacitors | |
| US9502517B2 (en) | Array substrate and fabrication method thereof, and display device | |
| CN103681659A (en) | Array substrate, production method and display device | |
| WO2022179142A1 (en) | Display panel and manufacturing method therefor, and display device | |
| US20210408068A1 (en) | Array substrate, method of manufacturing same, and display device | |
| US11895870B2 (en) | Display panel and display device | |
| US20220262932A1 (en) | Amorphous metal thin film transistors | |
| CN110534577B (en) | Thin film transistor and preparation method thereof | |
| CN101924122B (en) | Active matrix/organic light emitting display and manufacturing method thereof | |
| US20210327993A1 (en) | Organic light-emitting diode array substrate and manufacturing method thereof | |
| CN102629611B (en) | Display device, array substrate and manufacturing method thereof | |
| CN108269856B (en) | Oxide semiconductor thin film transistor, preparation method thereof and array substrate | |
| CN104409462A (en) | Array substrate, manufacturing method thereof and display device | |
| WO2019041954A1 (en) | Display panel, manufacturing method therefor, and display device | |
| CN109545836B (en) | OLED display device and manufacturing method thereof | |
| CN110707106A (en) | Thin film transistor, preparation method and display device | |
| CN112909025A (en) | Array substrate and preparation method thereof | |
| CN112599540B (en) | Array substrate, preparation method thereof and display panel | |
| CN111724736A (en) | Array substrate, OLED display panel and display device | |
| CN215266302U (en) | Array substrate | |
| CN112909027A (en) | Array substrate with high-capacity capacitor structure and preparation method thereof | |
| CN215266300U (en) | Display device | |
| CN215220722U (en) | Display panel | |
| CN112909028A (en) | Display device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |