CN110839349A - 包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件及制造方法 - Google Patents

包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件及制造方法 Download PDF

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CN110839349A
CN110839349A CN201980001932.9A CN201980001932A CN110839349A CN 110839349 A CN110839349 A CN 110839349A CN 201980001932 A CN201980001932 A CN 201980001932A CN 110839349 A CN110839349 A CN 110839349A
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substrate
layer
optoelectronic device
dilute nitride
single junction
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尼基尔·杰恩
布兰登·凯斯
何甘
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Utica Leaseco LLC
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Awbscqemgk Inc
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Abstract

描述了一种薄膜柔性光电器件。在一个方面，一种用于制造单结光电器件的方法包括：在衬底上形成p‑n结构，该p‑n结构包括具有与衬底的晶格常数匹配的晶格常数的半导体，该半导体包括稀释氮化物，并且该单结光电器件包括该p‑n结构；以及将该单结光电器件从衬底分离。所述稀释氮化物包括GaInNAs、GaInNAsSb、其合金或其衍生物中的一种或多种。

Description

包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件及制 造方法
相关申请的交叉引用
本申请涉及2018年6月18日提交的名称为“THIN-FILM,FLEXIBLE MULTI-JUNCTIONOPTOELECTRONIC DEVICES INCORPORATING LATTICE-MATCHED DILUTE NITRIDE JUNCTIONSAND METHODS OF FABRICATION”的美国专利申请No.16/011,516，其内容通过引用整体并入本文。本申请要求2018年6月18日提交的名称为“THIN-FILM,FLEXIBLE OPTOELECTRONICDEVICES AND INCORPORATING A SINGLE LATTICE-MATCHED DILUTE NITRIDE JUNCTIONAND METHODS OF FABRICATION”的美国专利申请No.16/011,531的权益，该申请通过引用明确地整体并入本文。
技术领域
本公开的各方面一般涉及光电器件，更具体地涉及包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件以及制造该光电器件的方法。
背景技术
需要提供与常规光电器件的效率相比具有更针对性的改进的能量捕获效率的光电器件(例如，光伏电池)。然而，这些改进的器件需要具有成本效益、易于实现和/或适应现有环境。实现更好的柔性和轻质设计也是高度期望的。本公开描述了解决这些需求的技术解决方案的各个方面。
发明内容
以下给出一个或多个方面的简要概述，以便提供对这些方面的基本理解。该概述不是对所有考虑到的方面的广泛概述，并且既不旨在确定所有方面的关键或重要要素，也不旨在描绘任何或所有方面的范围。其目的是以简化形式给出一个或多个方面的一些概念，作为稍后给出的更详细描述的序言。
本公开描述了包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件以及制造该光电器件的方法。例如，本公开描述了使用可以生长为与GaAs衬底或Ge衬底晶格匹配的稀释氮化物的太阳能电池设计的各个方面，其中该设计还可以与外延剥离(epitaxiallift-off,ELO)或类似的衬底重复使用技术(如剥落(spalling)、激光剥离(laser lift-off)、剥离(exfoliation)等)兼容。此外，本文描述的技术允许单结光电器件沿反方向生长。
在一个方面，描述了一种用于制造单结光电器件的方法。该方法包括在衬底上形成p-n结构，该p-n结构包括具有与衬底的晶格常数匹配的晶格常数的半导体，该半导体包括稀释氮化物，并且该单结光电器件包括该p-n结构。此外，该方法包括将该单结光电器件从所述衬底分离。
本文描述的具有单个稀释氮化物结的单结光电器件可以被配置为还包括背反射层和/或其他光学工程结构或层，其可以与该单结光电器件的p-n结构或子单元一起生长、沉积或形成。该器件的这些光学工程背面允许增强光吸收。
还描述了涉及包含单个晶格匹配的稀释氮化物结的薄膜柔性光电器件以及制造这些光电器件的方法的另外方面。
附图说明
附图仅示出了一些实施方式，因此不应视为限制范围。
图1是示出根据本公开的方面的具有单个稀释氮化物结的光电器件的示例的示图。
图2A是示出根据本公开的方面的具有单个稀释氮化物结的光电器件的具体示例的示图。
图2B是示出根据本公开的方面的图2A中的光电器件从衬底分离的示例的示图。
图3、4和5是示出根据本公开的方面的具有单个稀释氮化物结的光电器件的示例的示图。
图6是示出根据本公开的方面的用于制造具有单个稀释氮化物结的光电器件的方法的示例的流程图。
具体实施方式
以下结合附图给出的详细描述旨在作为对各种配置的描述，而无意表示可实践本文描述的概念的仅有配置。该详细描述包括用于提供对各种概念的透彻理解的目的的具体细节。然而，对于本领域技术人员显而易见的是，可以在没有这些具体细节的情况下实践这些概念。在一些实例中，众所周知的组件以框图形式示出，以避免模糊这些概念。
如上所述，本公开涉及包含单个晶格匹配的稀释氮化物结的光电器件以及用于形成这种光电器件的制造工艺。因此，本公开描述了可以用作本文描述的光电器件的诸如光伏器件、发光二极管(LED)或其他光电器件的薄膜器件的制造的各个方面。
例如，期望改善诸如光伏电池或LED等光电器件的性能以提高其效率，而不会显著影响成本或增加器件的总尺寸。因此，这些器件应具有成本效益，易于实施和/或适应现有环境。实现更好的柔性和轻质设计也是高度期望的。本公开描述了解决这些需求的技术解决方案的各个方面。
通常，通过改善电池的光吸收/转换效率或LED的光产生效率来改善诸如光伏电池(例如，太阳能电池)或LED等光电器件的性能。可以通过生长具有特定或针对性的带隙的材料或者通过生长具有不同带隙的材料使得最高带隙材料位于面向光的一侧(例如，正面)并且最低带隙材料位于相对侧(例如，背面)来制造高效光伏电池。这导致不同层吸收不同能量的光子，从而提高光伏电池的效率，因为这种布置导致更多的光子被吸收并因此产生更大的电流。通过串联组合堆叠的太阳能电池(例如，相邻p-n结构或子单元)，每一个可以具有相同电流，并且它们各自的电压被线性地相加以提供总体较高的效率并因此提供总体较高的功率。这可以使用不同的方法(晶格匹配、失配、键合等)来实现；然而，每种方法都有其自身的优点和缺点。
生长具有特定带隙的材料层或者不同带隙材料(即，具有不同能隙的材料)的多层可能需要不同晶格常数的材料来实现最佳带隙组合。生长衬底和不同层之间的晶格失配可能降低所得光伏电池的总效率(在发光二极管的操作中出现类似的低效率)。另一种方法是使用变质渐变层来生长晶格失配的光电器件(例如，晶格失配的太阳能电池)以允许晶格常数的差异，例如，使用InGaAs作为底部结。这种变质方法导致大量浪费的金属有机化学气相沉积(MOCVD)前体材料和降低的MOCVD工具吞吐量以及较大和较厚的器件。
对于诸如光伏电池(例如，太阳能电池)和LED等光电器件，使用诸如(AlGaIn)(PAsSb)的标准合金的基于III-V族半导体材料的晶格匹配系统不允许生长GaAs带隙(～1.41eV)以下的晶格匹配材料。如上所述，为了提高光电器件的效率，可以使用具有特定带隙的针对性的结或者具有不同带隙的多结来捕获或收集来自光谱的不同部分的能量。因此，为了增加针对特定目标光谱的太阳能电池效率，吸收材料的带隙需要可调性，同时保持与GaAs或Ge衬底的晶格匹配。这可以通过使用合成渐变缓冲层以桥接晶格常数来在GaAs或Ge衬底上生长变质(或晶格失配)的结。然而，该方法需要昂贵且体积大的变质缓冲层。
稀释氮化物合金或仅稀释氮化物(例如，GaInAsN(Sb)合金)可以生长为与GaAs衬底晶格匹配，其带隙可调低于或处于1.4eV至(例如，0.8eV至1.4eV)。因此，稀释氮化物合金可以允许针对特定的目标光谱具有带隙可调性的单结(1J)或p-n结构的晶格匹配的太阳能电池，并且不需要厚的变质梯度缓冲层来相对于起始衬底桥接所需吸收材料的晶格常数。此外，作为底部结的稀释氮化物还可以使得能够使用(AlGaIn)(AsPSb)在GaAs或Ge衬底上实现超过四(4)个结或p-n结构的晶格匹配太阳能电池，其中顶部三个结的带隙跨度在2.2到1.4eV的范围内。由于各种原因，这种方法很有吸引力。例如，可以晶格匹配地并且在反方向上外延生长光电器件的整个堆叠或层以补充现有的外延剥离(ELO)工艺。所提出的方法可以实现轻质且柔性的光电器件(例如，太阳能电池)，而不需要厚且昂贵的变质缓冲层。
因此，本公开提出了在反方向上并且使用剥离工艺制造具有单个稀释氮化物结或p-n结构的光电器件。p-n结构内的P-n结可以定位在光入射的一侧附近或者进一步远离朝向使用稀释氮化物材料的光电器件的下部。也就是说，结的位置(每个p-n结构中的p-n结的位置)可以形成在器件的正面(光入射侧)附近或者远离光的入射侧(通常称为后-异质结器件)。每个相应的p-n结构可以是同质结(即，p-n结构中的结的两侧由相同材料构成)或者可以是异质结(即，p-n结构中的结的一侧可以由比厚的吸收层/基极层具有更大带隙的材料构成。该方法使得能够制造轻质且柔性的薄膜光电器件，并且通过包括单个稀释氮化物结可以提供高效率。例如，该光电器件可以制成柔性的，使得它们可以支持例如1cm至850cm的曲率半径。此外，这些光电器件可以是轻质的，因为其可以具有例如500W/kg至5000W/kg的比功率(或能量密度)、200W/m2至500W/m2的面积能量密度以及0.05kg/m2至0.5kg/m2的面积质量密度(重量/面积)。此外，这些光电器件支持从AM0至AM1.5的光谱。
本文描述的薄膜柔性器件(例如，诸如光伏电池或LED的光电器件)一般包含外延生长层，所述外延生长层形成在设置于支撑衬底或晶片上或上方的释放层或牺牲层上。由此形成的薄膜器件可以是柔性单晶器件。通过外延工艺形成薄膜器件后，例如在外延剥离(ELO)工艺、激光剥离(LLO)工艺或剥落工艺期间，从支撑衬底或晶片移除或分离薄膜器件。
如在本公开中使用的，层可以被描述为沉积或生长在一个或多个其他层“上”或“上方”。在一些实施例或实施方式中该术语表示该层可以直接沉积或生长在其他层的顶部上，或者可以表示一个或多个附加层可以沉积在该层和其他层之间。而且，所述其他层可以以任何顺序排列。为了更详细地描述本公开的特征，结合附图参考以下讨论。
图1示出示图100，其示出了具有由稀释氮化物制成的单个结或p-n结构(例如，1J光电器件)的光电器件的一般示例。在该示例中，存在衬底或晶片110，在衬底或晶片110上设置有释放层115。虽然衬底110显示为单层，但它可包括多个层。例如，衬底110可以由GaAs或Ge制成。
释放层115有时被称为牺牲层，可以提供释放层115以使多结光电器件能够从衬底100剥离或分离。在一些实施方式中，可以例如在沉积p-n结构之前在衬底上设置释放层115，以能够通过使用外延剥离(ELO)工艺或其他类似工艺来剥离或分离p-n结构。释放层115可包括AlAs、AlGaAs、AlGaInP或AllnP、或具有高Al含量的其他层、或其组合，并用于形成包含在多结光电器件内的各层的晶格结构，然后在ELO工艺期间蚀刻并移除。在其他实施方式中，可以使用替代的剥离工艺，如激光剥离(LLO)、离子注入和剥离、通过蚀刻掩埋氧化物层或掩埋多孔层的剥离、或剥落。释放层115中的Al含量可以变化。例如，当释放层115包括AlGaAs时，含量可以是AlxGa1-xAs(其中x＝1至0.3)。在另一示例中，当释放层115包括AlGaInP时，含量可以是(AlxGa1-x)0.5In0.5P(其中x＝1至0)。
然后在释放层115上方生长、沉积或形成(这些术语可以互换使用)光电器件。例如，该示例中的光电器件包括如上所述的单个结或p-n结构。在释放层115上外延生长稀释氮化物p-n结构120。
p-n结构可以指具有一个或多个半导体层的结构，并且其中一个或多个p-n结由所述一个或多个半导体层形成。因此，示图100a中的多结光电器件中的每个p-n结构可以包括一个或多个p-n结。此外，示图100a中的光电器件中的每个p-n结构与衬底110晶格匹配。即，制造p-n结构(例如，稀释氮化物p-n结构120)的材料的晶格常数与制造衬底的材料的晶格常数相同。普通技术人员可以认识到，晶格常数的这种匹配还包括具有几乎(基本上)彼此匹配的晶格常数的材料。晶格常数的匹配或基本匹配是指允许形成两个不同且相邻的半导体材料的带隙变化区域而不引入晶体结构的变化。在一个示例中，稀释氮化物p-n结构的材料或半导体的晶格常数以<0.4％的失配或应变与衬底110的晶格常数匹配。
稀释氮化物p-n结构120可以由稀释氮化物合金制成，如GaInNAs或GaInNAsSb，更一般地称为GaInAsN(Sb)，或其衍生物。在一个组成示例中，稀释氮化物p-n结构120包括Ga1-yInyAs1-x-zNxSbz，其中In的含量y在0至20％的范围内，N的含量x在0至6％的范围内，并且Sb的含量z在0至8％的范围内。
稀释氮化物p-n结构120可以通过使用各种技术的外延生长形成，例如，金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、金属有机气相外延(MOVPE或OMVPE)、液相外延(LPE)、氢化物气相外延(HVPE)、近空间气相输运(CSVT)外延等。在一些实施方式中，稀释氮化物p-n结构120基本上是单晶。也就是说，稀释氮化物p-n结构120可包括单晶半导体材料。
在一些实施方式中，可使用高生长速率工艺来形成稀释氮化物的一个或多个外延生长层。高生长速率工艺使得生长的材料具有足够的质量以用于本文所述的光电器件的类型。高生长速率工艺允许生长速率大于1μm/小时，如约10μm/小时或更高，或高达约100μm/小时或更高。例如，生长速率可为约10μm/小时、约20μm/小时、约30μm/小时、约40μm/小时、约50μm/小时、约60μm/小时、约70μm/小时、约80μm/小时、约90μm/小时、或约100μm/小时、这些值中的任何两个之间的某些特定速率(例如，约25μm/小时-20μm/小时至30μm/小时之间)、或这些值中的任何两个之间的某一范围(例如，范围从约20μm/小时至约30μm/小时)。在一些实施方式中，高生长速率工艺允许生长速率大于100μm/小时，包括约120μm/小时的生长速率。如在本公开中使用的术语“约”可以表示例如偏离标称值的1％、2％、3％、4％、5％或10％的变化。
在一些实施方式中，稀释氮化物p-n结构120可具有在发射极层和基极层之间形成的界面或中间层(例如，在p-n结或p-n结构中的发射极层与基极层之间)。中间层可以是n掺杂的、p掺杂的或非有意掺杂的。例如，中间层的厚度可以在约5nm至约3000nm的范围内。中间层位于p掺杂层和n掺杂层之间，并且可以由与n掺杂层或p掺杂层相同的材料构成，或者可以由与n掺杂层或p掺杂层不同的材料构成，和/或可以是渐变组分的层。由此形成的中间层可以为一个或多个异质结提供从相应的p-n结偏移的位置。这种偏移可以允许降低器件内的暗电流，从而改善其性能。
在稀释氮化物p-n结构120内，可以形成异质结构，该异质结构包括包含AlGaAs/GaInAsN(Sb)或AlGaInP/GaInAsN(Sb)的合金的组合。异质结在异质结构内的位置可以更靠近太阳光入射侧或朝向器件的背面远离。
如本文所述，用于形成稀释氮化物p-n结构120的工艺可以在各种类型的沉积室中进行。例如，一个连续进料沉积室可用于生长、沉积或以其他方式形成稀释氮化物。
图2A示出示图200a，其示出了根据本公开的各方面的具有单个稀释氮化物结的光电器件的具体示例。
在第一示例中，图2A中的光电器件包括：由GaAs或Ge制成的衬底(在示图200a中称为GaAs或Ge衬底210)、与上述释放层115基本相似的释放层215、以及由带隙约0.9至1.4eV，更具体地1.1eV至1.35eV的稀释氮化物制成的单个p-n结构(称为GaInAsN(Sb)p-n结构220)。
在第二示例中，图2A中的光电器件包括：GaAs或Ge衬底210、释放层215、和由带隙约1.3eV至1.4eV的稀释氮化物制成的GaInAsN(Sb)p-n结构220。
在第三示例中，图2A中的光电器件包括：GaAs或Ge衬底210、释放层215、和由带隙约1.34eV的稀释氮化物制成的GaInAsN(Sb)p-n结构220。
在第四示例中，图2A中的光电器件包括：GaAs或Ge衬底210、释放层215、和由带隙约0.9eV至1.4eV的稀释氮化物制成的GaInAsN(Sb)p-n结构220。
图2B示出示图200b，其示出了使用例如包括ELO工艺的本文所述的不同剥离技术中的任何一个从基板210分离图2A中的光电器件。示图200b示出GaAs或Ge衬底210被从光电器件移除或分离，至少留下GaInAsN(Sb)p-n结构220。
图3示出示图300，其示出了光电器件的另一个一般示例。在该示例中，存在由GaAs制成的对应于衬底110的GaAs晶片310。GaAs缓冲层320设置在GaAs晶片310上，并且释放层115设置在GaAs缓冲层320上。接触层330形成在释放层115上，并且前窗340形成在接触层330上。
接触层330可以是重n掺杂的。在一些实施方式中，掺杂浓度可在大于约5×1018cm-3的范围内，例如，大于约5×1018cm-3至约5×1019cm-3。接触层330的高掺杂允许与稍后沉积的金属层形成欧姆接触，而不执行任何退火步骤以形成这种欧姆接触。
接触层330可以是掺杂有硅(Si)的GaAs。例如，在如上所述的高生长速率用于形成多结光电器件的各层的一些实施方式中，可以使用硅掺杂剂(作为n掺杂剂)来使掺杂浓度达到5×1018cm-3或更高。例如，可以以快速生长速率工艺引入前体乙硅烷，以沉积硅掺杂剂。在其他实施方式中，硒(Se)或碲(Te)可用作形成多结光电器件的至少一些层时的掺杂剂。
在示图300中所示的示例中，在从GaAs晶片310和GaAs缓冲层320移除或分离光电器件之前清楚地形成有接触层330。所示结构的其余部分包括与如上结合图1所述的相同或相似的层。例如，稀释氮化物p-n结构120形成在前窗340上。可选地，反射层350(也称为后反射层)可以形成在稀释氮化物p-n结构120上。
可以在从GaAs晶片310分离光电器件之前或之后在最后生长的p-n结构上沉积支撑层(未示出)。当在分离之前沉积时，可以将光电器件和支撑层一起从GaAs晶片310和GaAs缓冲层320剥离(例如，分离、移除)。
支撑层可包括介电层、半导体接触层(或简称接触层)、钝化层、透明导电氧化物层、抗反射涂层、金属涂层、粘合层、环氧树脂层或塑料涂层中的一个或多个。在一个实施例或实施方式中，支撑层由一种或多种材料构成，所述材料对例如用作剥离工艺(例如ELO)的一部分的酸具有化学耐酸性。在包括介电层作为支撑层的一部分的那些情况下，介电层包括有机或无机的介电材料。有机介电材料包括聚烯烃、聚碳酸酯、聚酯、环氧树脂、含氟聚合物、其衍生物及其组合中的任何一种，并且无机介电材料包括三硫化砷、硒化砷、α氧化铝(蓝宝石)、氟化镁、其衍生物及其组合中的任何一种。在包括接触层(或多个接触层)作为支撑层的一部分的那些情况下，根据最终的光电器件的所需组成，接触层可以包含III-V族半导体材料，如GaAs。
图4示出示图400，其图示了从GaAs晶片310和GaAs缓冲层320分离之后的图3中的光电器件。在示图400中，光电子器件被示出为阳光侧向上，在背面添加有反射层410，在正面添加有金属430和抗反射(AR)涂层420。
反射层410，也可称为反射背接触，是金属反射层或金属-介电反射层。反射层410可以对应于图3中所示的反射层350。这些反射背接触可以在多结光电器件被剥离之前或之后沉积，并且可以包括银、铝、金、铂、铜、镍、钼或其合金中的一种或多种。具有反射背接触的层可以通过气相沉积工艺沉积，如物理气相沉积(PVD)、溅射、电子束沉积(e-beam)、ALD、CVD、PE-ALD或PE-CVD，或者通过其他沉积工艺，包括喷墨印刷、丝网印刷、蒸发、电镀、无电沉积(e-less)或其组合。
图5示出示图500，其示出了包括添加在背面的反射层410以及添加到正面的金属430和AR涂层420的图4中的多结光电器件。另外，在反射层410和稀释氮化物p-n结构120之间，存在纹理层520、与纹理化层520相邻的可选AR涂层530、与反射层410接触的一种或多种金属510以及在所述一种或多种金属940的端部的可选的接触层540。由纹理层520和/或相邻的可选AR涂层530提供的表面纹理可以改善光在该表面处的散射，以及改善与金属和介电层的粘附性。
与光电器件相关联的纹理化不必限于纹理层520和/或可选的相邻AR涂层530。可以在包括p-n结构的材料的生长期间实现表面的纹理化。这可以至少部分地通过使用p-n结构中的至少两种材料之间的晶格失配来实现，例如在Stranski-Krastanov工艺或Volmer-Weber工艺中，以在材料之间的界面处产生纹理。在另一实施方式中，p-n结构中或上的层可充当蚀刻掩模并且可以通过蚀刻工艺提供纹理。在又一个实施方式中，纹理可以通过物理研磨提供，如砂纸或喷砂或颗粒喷射或类似工艺。在又一个实施方式中，纹理可以通过不均匀的蚀刻工艺提供，该工艺在表面上产生微观上不均匀的特征。此外，可以使用与硅纹理化中使用的技术类似的技术来实现纹理化，包括例如使用例如KOH的“随机金字塔”或“倒金字塔”蚀刻。
p-n结构的背面(如在该示例中)和/或正面(例如，最接近光被光伏电池接收或由LED发射的一侧)可以被纹理化以改善进入和/或离开器件的光散射。在如图5中所示的背面纹理中，可以使用上述一种或多种纹理化技术对稀释氮化物材料进行纹理化。
图6是示出根据本公开的方面的用于制造单结光电器件的方法600的流程图。
在框610处，方法600包括在衬底(例如，衬底110)上形成p-n结构，该p-n结构包括具有与衬底的晶格常数匹配的晶格常数的半导体，该半导体包括稀释氮化物(例如，稀释氮化物p-n结构120)，并且该单结光电器件包括该p-n结构。衬底由GaAs或Ge中的一种制成或者包括GaAs或Ge中的一种。
在框620处，方法600包括将单结光电器件从衬底分离。
在方法600的一个方面中，将单结光电器件从衬底分离包括将该单结光电器件定向，使得该p-n结构最接近单结光电器件的光入射到其上的表面。
在方法600的一个方面，该方法还包括在该单结光电器件的最接近该p-n结构的表面上形成附加层，作为背面处理的一部分。
在方法600的一个方面，该方法还包括为该单结光电器件提供具有介电层、半导体接触层、钝化层、透明导电氧化物层、抗反射涂层、金属涂层、粘合剂层、环氧树脂层或塑料涂层中的一个或多个的支撑层。
在方法600的一个方面，该稀释氮化物包括GaInNAs、GaInNAsSb、其合金或其衍生物中的一种或多种。在一个组成示例中，稀释氮化物包括Ga1-yInyAs1-x-zNxSbz，其中In的含量y在0至20％的范围内，N的含量x在0至6％的范围内，Sb的含量z在0至8％的范围内。
在方法600的一个方面，半导体的晶格常数与衬底的晶格常数以<0.4％的失配或应变匹配。
在方法600的一个方面，在衬底上形成第一p-n结构包括使用外延生长工艺沉积p-n结构。在一个示例中，外延生长工艺是分子束外延(MBE)工艺。外延生长工艺可包括下列中的一种或多种：金属有机化学气相沉积(MOCVD)工艺、氢化物气相外延(HVPE)工艺、分子束外延(MBE)工艺、金属有机气相外延(MOVPE或OMVPE)工艺、液相外延(LPE)工艺、近空间气相输运(CSVT)外延工艺、等离子体增强化学气相沉积(PECVD)工艺、物理气相沉积(PVD)工艺、大气压化学气相沉积(APCVD)工艺、原子层沉积(ALD)工艺、低压化学气相沉积(LPCVD)工艺、热丝化学气相沉积(HWCVD)工艺、电感耦合等离子体增强化学气相沉积(ICP-CVD)工艺或其他形式的CVD。
在方法600的一个方面，将该单结光电器件从衬底分离包括执行外延剥离(ELO)工艺以将该单结光电器件从衬底剥离。
在方法600的一个方面，该方法还包括在衬底和p-n结构之间提供释放层(例如，参见释放层115)，其中将该单结光电器件从衬底分离包括移除牺牲层。在一个示例中，释放层包括AlAs。
在方法600的一个方面，释放层包括AlGaAs，含量为AlxGa1-xAs，其中x＝1至0.3。
在方法600的一个方面，释放层包括AlGaInP，含量为(AlxGa1-x)0.5In0.5P，其中x＝1至0。
在方法600的一个方面，衬底包括GaAs或Ge，并且稀释氮化物具有约1.1eV至1.35eV的带隙(例如，参见图2A)。
在方法600的一个方面，衬底包括GaAs或Ge，并且稀释氮化物具有约1.31eV至1.4eV的带隙(例如，参见图2A)。
在方法600的一个方面，衬底包括GaAs或Ge，并且稀释氮化物具有约1.34eV的带隙(例如，参见图2A)。
在方法600的一个方面，衬底包括GaAs或Ge，并且稀释氮化物具有约0.9eV至1.4eV的带隙(例如，参见图2A)。
在方法600的一个方面，该方法还包括在p-n结构上形成反射层，并且将该单结光电器件从衬底分离包括从衬底分离p-n结构和反射层。
尽管已经根据所示的实施方式提供了本公开，但是本领域普通技术人员将容易认识到，实施例可以有变化，并且那些变化将在本公开的范围内。因此，在不脱离所附权利要求的范围的情况下，本领域普通技术人员可以进行许多修改。

Claims (24)

1.一种用于制造单结光电器件的方法，包括：
在衬底上形成p-n结构，所述p-n结构包括具有与所述衬底的晶格常数匹配的晶格常数的半导体，所述半导体包括稀释氮化物，并且所述单结光电器件包括所述p-n结构；和
将所述单结光电器件从所述衬底分离。
2.根据权利要求1所述的方法，其中将所述单结光电器件从所述衬底分离包括将所述单结光电器件定向为使得所述p-n结构最接近所述单结光电器件的光入射表面。
3.根据权利要求1所述的方法，还包括在所述单结光电器件的最接近所述p-n结构的表面上形成附加层，作为背面处理的一部分。
4.根据权利要求1所述的方法，还包括：为所述单结光电器件提供支撑层，所述支撑层具有介电层、半导体接触层、钝化层、透明导电氧化物层、抗反射涂层、金属涂层、粘合剂层、环氧树脂层或塑料涂层中的一个或多个。
5.根据权利要求1所述的方法，其中所述衬底包括GaAs或Ge之一。
6.根据权利要求1所述的方法，其中所述稀释氮化物包括GaInNAs、GaInNAsSb、其合金或其衍生物中的一个或多个。
7.根据权利要求1所述的方法，其中：
所述稀释氮化物包括Ga1-yInyAs1-x-zNxSbz，
In的含量y在0至20％的范围内，
N的含量x在0至6％的范围内，并且
Sb的含量z在0至8％的范围内。
8.根据权利要求1所述的方法，其中所述半导体的晶格常数与所述衬底的晶格常数以<0.4％的失配或应变匹配。
9.根据权利要求1所述的方法，其中在所述衬底上形成所述p-n结构包括使用外延生长工艺沉积所述p-n结构。
10.根据权利要求9所述的方法，其中所述外延生长工艺是分子束外延MBE工艺。
11.根据权利要求9所述的方法，其中所述外延生长工艺包括以下中的一个或多个：
金属有机化学气相沉积MOCVD工艺、
氢化物气相外延HVPE工艺、
分子束外延MBE工艺、
金属有机气相外延MOVPE或OMVPE工艺、
液相外延LPE工艺、
近空间气相传输CSVT外延工艺、
等离子体增强化学气相沉积PECVD工艺、
物理气相沉积PVD工艺、
大气压化学气相沉积APCVD工艺、
原子层沉积ALD工艺、
低压化学气相沉积LPCVD工艺、
热丝化学气相沉积HWCVD工艺、
电感耦合等离子体增强化学气相沉积ICP-CVD工艺、
或
其他形式的CVD。
12.根据权利要求9所述的方法，其中所述外延生长工艺包括MBE和MOCVD的组合。
13.根据权利要求1所述的方法，其中将所述单结光电器件从所述衬底分离包括执行外延剥离ELO工艺以将所述单结光电器件从所述衬底剥离。
14.根据权利要求1所述的方法，还包括在所述衬底和所述p-n结构之间提供释放层，
其中将所述单结光电器件从所述衬底分离包括移除所述释放层。
15.根据权利要求14所述的方法，其中所述释放层包括AlAs。
16.根据权利要求14所述的方法，其中所述释放层包括AlGaAs，含量为AlxGa1-xAs，其中x＝1至0.3。
17.根据权利要求14所述的方法，其中所述释放层包括AlGaInP，含量为(AlxGa1-x)0.5In0.5P，其中x＝1至0。
18.根据权利要求1所述的方法，其中：
所述衬底包括GaAs或Ge，并且
所述稀释氮化物具有约为1.1eV至1.35eV的带隙。
19.根据权利要求1所述的方法，其中：
所述衬底包括GaAs或Ge，并且
所述稀释氮化物具有约为1.3eV至1.4eV的带隙。
20.根据权利要求1所述的方法，其中：
所述衬底包括GaAs或Ge，并且
所述稀释氮化物具有约为1.34eV的带隙。
21.根据权利要求1所述的方法，其中：
所述衬底包括GaAs或Ge，并且
所述稀释氮化物具有约为0.9eV至1.4eV的带隙。
22.根据权利要求1所述的方法，还包括：
在所述p-n结构上形成反射层，并且
将所述单结光电器件从所述衬底分离包括将所述p-n结构和所述反射层从所述衬底分离。
23.根据权利要求1所述的方法，其中所述p-n结构包括p-n结，所述p-n结的位置靠近所述单结光电器件的正面或者远离光入射侧。
24.根据权利要求1所述的方法，其中所述p-n结构可以是异质结或同质结。
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