CN110828409A - 半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法 - Google Patents

半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法 Download PDF

Info

Publication number
CN110828409A
CN110828409A CN201910650002.8A CN201910650002A CN110828409A CN 110828409 A CN110828409 A CN 110828409A CN 201910650002 A CN201910650002 A CN 201910650002A CN 110828409 A CN110828409 A CN 110828409A
Authority
CN
China
Prior art keywords
circuit
semiconductor device
external terminal
metal plate
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910650002.8A
Other languages
English (en)
Inventor
日野泰成
田中阳
菊池正雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of CN110828409A publication Critical patent/CN110828409A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49537Plurality of lead frames mounted in one device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • H01L23/49562Geometry of the lead-frame for devices being provided for in H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45014Ribbon connectors, e.g. rectangular cross-section
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/4501Shape
    • H01L2224/45012Cross-sectional shape
    • H01L2224/45015Cross-sectional shape being circular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/8122Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/81224Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1027IV
    • H01L2924/10272Silicon Carbide [SiC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/1026Compound semiconductors
    • H01L2924/1032III-V
    • H01L2924/1033Gallium nitride [GaN]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Dispersion Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Inverter Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本发明涉及半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法。抑制端子接合的接合强度的波动,提高装置的可靠性。半导体装置具备:绝缘基板(3),其形成有电路面(3b);以及外部端子(7B),其与电路面接合。电路面的上表面与外部端子的下表面的一部分接触而接合,在电路面的上表面与外部端子的下表面接触的部位的至少一部分形成电路面和外部端子的熔融部(11),在电路面的上表面与外部端子的下表面之间产生的间隙的尺寸小于或等于20μm,电路面以及外部端子均为铜或者铜合金。

Description

半导体装置、电力变换装置、半导体装置的制造方法及电力变 换装置的制造方法
技术领域
本申请说明书所公开的技术涉及半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法。
背景技术
近年来,与环境法规的强化对应地,对考虑了环境问题的高效率且节能的半导体装置的需求提高。
半导体装置用于工业设备、具备电机的家电的驱动控制设备、面向电动汽车或者面向混合动力汽车的车载控制设备、铁路控制设备乃至太阳能发电的控制设备等,谋求实现更高功率、高耐压以及高耐久。
特别地,就车载控制设备或者铁路控制设备而言,从节能的观点或者抑制电能的变换损耗的观点出发,半导体装置是在高负载环境下(即,高温环境下)使用的(即,正在高Tj化),谋求即使在这样的高温环境下也高效率且低损耗地进行动作。
具体地说,至今为止的通常的动作温度Tj(结温)为125℃或者150℃以下,但今后,需要应对Tj为175℃或者200℃以上的高温环境下的动作。
因此,为了在如上述的高温环境下,通过抑制通断损耗而实现低损耗化、即实现高温状态下的高效化,需要重新设计半导体装置的构造。
特别地,半导体装置内的配线连接部(即,接合部)最容易劣化,实现该配线连接部(即,接合部)的高品质、高可靠性以及长寿命成为大的课题(例如,参照专利文献1)。
专利文献1:国际公开第2017/195625号公报
近年来,取代焊料,而使用钇-铝-石榴石(YAG)激光、CO2激光或者半导体激光等来实现接合的配线连接开发正在推进。
另外,光纤激光的振荡器所涉及的技术开发得到推进,能够实现该激光的高输出化,因此开始了为了针对激光反射率(即,热量的吸收率)低的铜(Cu)应用该激光的研究。
然而,对于使用光纤激光的功率半导体装置的内部配线,耐久性成为课题,特别地,关于端子接合,接合强度的波动(或者,焊入深度的波动)大。因此,难以确保接合稳定性,要求高可靠性的功率半导体装置的实用化困难。
发明内容
本申请说明书所公开的技术就是为了解决以上所记载的问题而提出的,其目的在于提供一种用于抑制端子接合的接合强度的波动,提高装置的可靠性的技术。
本申请说明书所公开的技术的第1方案具备:绝缘基板,其至少在上表面形成电路面;半导体元件,其经由接合材料而配置于所述电路面的上表面;以及外部端子,其与所述电路面的上表面接合,所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm,所述电路面以及所述外部端子均为铜或者铜合金。
另外,本申请说明书所公开的技术的第2方案具备:金属板;半导体元件,其经由接合材料而配置于所述金属板的上表面;以及外部端子,其与所述金属板的上表面接合,所述金属板的上表面与所述外部端子的下表面经由导电材料而接触,在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部,所述金属板以及所述外部端子均为铜或者铜合金。
另外,本申请说明书所公开的技术的第3方案具备:变换电路,其具有上述中的任意的半导体装置,且该变换电路将被输入进来的电力进行变换而输出;驱动电路,其将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出;以及控制电路,其将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
另外,本申请说明书所公开的技术的第4方案是,准备绝缘基板,该绝缘基板至少在上表面形成电路面,经由接合材料而将半导体元件配置于所述电路面的上表面,在所述电路面的上表面配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面与所述电路面的上表面接合,所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm。
另外,本申请说明书所公开的技术的第5方案是,准备金属板,经由接合材料而将半导体元件配置于所述电路面的上表面,在所述金属板的上表面经由导电材料而配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面经由所述导电材料而与所述金属板的上表面接合,所述金属板的上表面与所述外部端子的下表面经由所述导电材料而接触,在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部。
另外,本申请说明书所公开的技术的第6方式是,设置变换电路,该变换电路具有上述中的任意的半导体装置,且该变换电路将被输入进来的电力进行变换而输出,设置驱动电路,该驱动电路将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出,设置控制电路,该控制电路将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
发明的效果
本申请说明书所公开的技术的第1方案具备:绝缘基板,其至少在上表面形成电路面;半导体元件,其经由接合材料而配置于所述电路面的上表面;以及外部端子,其与所述电路面的上表面接合,所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm,所述电路面以及所述外部端子均为铜或者铜合金。根据上述的结构,通过熔融部,在电路面与外部端子之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。因此,能够提高半导体装置的可靠性。
另外,本申请说明书所公开的技术的第2方案具备:金属板;半导体元件,其经由接合材料而配置于所述金属板的上表面;以及外部端子,其与所述金属板的上表面接合,所述金属板的上表面与所述外部端子的下表面经由导电材料而接触,在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部,所述金属板以及所述外部端子均为铜或者铜合金。根据上述的结构,通过熔融部,夹在金属板的上表面与外部端子之间的导电材料确保接合强度,因此能够抑制接合强度的波动。因此,能够提高半导体装置的可靠性。
另外,本申请说明书所公开的技术的第3方案具备:变换电路,其具有上述中的任意的半导体装置,且该变换电路将被输入进来的电力进行变换而输出;驱动电路,其将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出;以及控制电路,其将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。根据上述的结构,通过熔融部,在被接合材料与外部端子之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。
另外,本申请说明书所公开的技术的第4方案是,准备绝缘基板,该绝缘基板至少在上表面形成电路面,经由接合材料而将半导体元件配置于所述电路面的上表面,在所述电路面的上表面配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面与所述电路面的上表面接合,所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm。根据上述的结构,通过使用光纤激光形成熔融部,从而在电路面与外部端子之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。因此,能够提高半导体装置的可靠性。
另外,本申请说明书所公开的技术的第5方案是,准备金属板,经由接合材料而将半导体元件配置于所述电路面的上表面,在所述金属板的上表面经由导电材料而配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面经由所述导电材料而与所述金属板的上表面接合,所述金属板的上表面与所述外部端子的下表面经由所述导电材料而接触,在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部。根据上述的结构,通过使用光纤激光形成熔融部,从而夹在金属板的上表面与外部端子之间的导电材料确保接合强度,因此能够抑制接合强度的波动。因此,能够提高半导体装置的可靠性。
另外,本申请说明书所公开的技术的第6方式是,设置变换电路,该变换电路具有上述中的任意的半导体装置,且该变换电路将被输入进来的电力进行变换而输出,设置驱动电路,该驱动电路将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出,设置控制电路,该控制电路将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。根据上述的结构,能够通过熔融部而抑制接合强度的波动。因此,能够提高电力变换装置的可靠性。
另外,本申请说明书所公开的技术涉及的目的、特征、方案以及优点通过以下所示的详细说明和附图变得更清楚。
附图说明
图1是概略地表示实施方式涉及的能够在高温环境下动作的功率半导体装置的结构的例子的剖面图。
图2是放大示出实施方式涉及的功率半导体装置的端子与绝缘基板之间的接触部分的结构的图。
图3是放大示出实施方式涉及的功率半导体装置的端子与绝缘基板之间的接触部分的结构的图。
图4是表示实施方式涉及的在端子与电路面之间产生的间隙和接合强度的相关关系的例子的图。
图5是概略地表示实施方式涉及的功率半导体装置的结构的例子的剖面图。
图6是放大示出实施方式涉及的功率半导体装置的端子与导电性金属板之间的接触部分的结构的图。
图7是示意地表示实施方式涉及的包含电力变换装置的电力变换系统的结构的例子的图。
标号的说明
1A、1B半导体元件,2接合材料,3绝缘基板,3a绝缘材料,3b电路面,4散热板,5配线,6壳体,7A、7B端子,8封装材料,9金属性导电材料,10A、10B导电性金属板,11、11A熔融部,100电源,200电力变换装置,201变换电路,202驱动电路,203控制电路,300负载。
具体实施方式
以下,一边参照附图一边对实施方式进行说明。
此外,附图是概略地示出的,为了便于说明,适当进行结构的省略或者结构的简化。另外,在不同的附图分别示出的结构等的尺寸以及位置的相互关系不一定是准确地记载的,能够适当变更。另外,在不是剖面图的俯视图等附图中,为了易于理解实施方式的内容,有时也标注阴影线。
另外,在以下所示的说明中,对同样的结构要素标注相同的标号而进行图示,它们的名称和功能也相同。因此,有时为了避免重复,会省略关于它们的详细的说明。
另外,在以下所述的说明中,即使有时会使用“上”、“下”、“左”、“右”、“侧”、“底”、“表”或者“背”等表示特定的位置和方向的用语,但这些用语是为了易于理解实施方式的内容,出于方便而使用的,与实际实施时的方向没有关系。
<第1实施方式>
以下,对本实施方式涉及的半导体装置以及半导体装置的制造方法进行说明。
<关于功率半导体装置的结构>
图1是概略地表示本实施方式涉及的能够在高温环境下动作的功率半导体装置的结构的例子的剖面图。
在本实施方式中例示的功率半导体装置具备:散热板4,其具有散热性;绝缘基板3,其经由接合材料2而与散热板4的上表面接合,且具有绝缘性;半导体元件1A,其经由接合材料2而与绝缘基板3的上表面接合;以及半导体元件1B,其经由接合材料2而与绝缘基板3的上表面接合。
在此,绝缘基板3具备:绝缘材料3a;以及电路面3b,其形成于绝缘材料3a的上表面以及下表面。
与功率半导体装置的外部输入输出连接的铜或者铜合金的端子7A、或者其他半导体元件1B的上表面经由配线5而与半导体元件1A的上表面电连接。端子7B是铜或者铜合金,且与绝缘基板3的上表面的电路面3b接合。
并且,功率半导体装置被壳体6包围而搭载于壳体6,在壳体6的内部填充有绝缘材料即封装材料8。
绝缘基板3、半导体元件1A、半导体元件1B、一部分の端子7A以及一部分的端子7B被封装材料8覆盖。
半导体元件1A以及半导体元件1B的一边的长度例如大于或等于3mm且小于或等于18mm,半导体元件1A以及半导体元件1B例如是绝缘栅型双极晶体管(insulated gatebipolar transistor,即,IGBT)、金属-氧化膜-半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,即,MOSFET)等具有能够进行电力变换的通断功能的元件或者二极管。
半导体元件1A以及半导体元件1B例如是使用Si或者能够以更低损耗以及高效率实现控制的宽带隙半导体(例如,SiC或者GaN等)的半导体元件。
例如,在半导体元件1A以及半导体元件1B是IGBT的情况下,在半导体元件1A以及半导体元件1B的下表面形成的背面电极是集电极(collector)电极(electrode),在半导体元件1A以及半导体元件1B的上表面形成的上表面电极是发射极电极以及栅极电极。各电极通过溅射方法或者镀敷方法,由将Al、Au、Ag或者铜(Cu)作为主要成分的材料构成。
散热板4是一边的长度例如大于或等于30mm且小于或等于300mm、厚度例如大于或等于3mm且小于或等于20mm的由铜、铜合金复合物、Al、Al合金复合物或者AlSiC构成的热容量大的散热板。
散热板4经由接合材料2而与绝缘基板3的下表面连接。并且,散热板4的下表面从封装材料8露出。
在此虽未图示,但在未搭载半导体元件1A以及半导体元件1B的面,即,散热板4的下表面经由散热脂或者热界面材料(thermal interface material;TIM)而连接有鳍片形状的结构。此外,上述的鳍片形状的结构可以与散热板4一体地形成,也可以与水冷套一体地形成。
由于半导体元件1A以及半导体元件1B在进行通断动作时发热,因此如上所述,通过散热板4而确保热容量,并且由散热板4直接冷却,由此半导体元件1A以及半导体元件1B能够得到损耗小的所希望的通断功能。
配线5是将Al或者铜(Cu)作为主要成分的线材,用作功率半导体装置的内部配线。配线5在图1中被用作多根导线键合。
配线5的直径例如大于或等于300μm且小于或等于500μm。由于与Al相比铜(Cu)能够使电流密度更大,因此考虑线材以及线径,根据功率半导体装置的电流规格而区分使用。
另外,配线5也可以是厚度例如大于或等于0.1mm且小于或等于0.5mm的扁平形状(例如,带状)的线材。如果是这样的形状,则配线5能够应对各种大小的电流,另外,由于电阻低,因此能够抑制自身的发热量。
在半导体元件1A、半导体元件1B与绝缘基板3的上表面的电路面3b之间、以及绝缘基板3的下表面的电路面3b与散热板4之间使用的接合材料2例如是将Sn作为主要成分的无Pb焊料材料。或者,接合材料2是由Ag或者铜(Cu)的微小金属颗粒以及溶剂等构成的烧结接合材料,是具有大于或等于400℃的高耐热性的材料。
因此,上述的接合材料2还能够应对搭载在高温环境下动作的SiC元件或者GaN元件等的功率半导体装置。
由接合材料2形成的接合厚度例如大于或等于10μm且小于或等于300μm。该接合厚度是考虑到对半导体元件1A以及半导体元件1B的损伤而决定的。此外,由于接合材料2具有充分的热导率,因此不会产生由于接合厚度厚而导致的热阻的问题。
在散热板4的俯视观察时的周围通过粘接剂(在此未图示)等而粘接有成为功率半导体装置的外轮廓的壳体6。
壳体6在俯视观察时包围半导体元件1A、半导体元件1B、配线5以及绝缘基板3的周围。由聚苯硫醚(poly phenylene sulfide,即,PPS)树脂或者聚对苯二甲酸丁二醇酯(polybutylene terephthalate,即,PBT)树脂等构成的壳体6与端子7A以及端子7B一体成型。
被壳体6包围的内侧的区域例如由将环氧树脂作为主要成分的树脂或者凝胶状的硅树脂即封装材料8封装(即,注入)。
另外,虽然在图1中未图示,但搭载驱动电路或者保护电路的控制基板有时被封装在由壳体6包围的内侧的区域。
在搭载上述的控制基板的情况下,端子7A或者端子7B的一部分与搭载驱动电路或者保护电路的控制基板连接,用于进行通断动作的控制信号被从端子7A或者端子7B向控制基板输入。
在被壳体6包围的内侧的区域搭载的控制基板由端子7A或者端子7B支撑,在散热板4的上表面,以与绝缘基板3或者散热板4大致平行的状态配置。
从半导体元件1A经由将Al或者铜(Cu)作为主要成分的配线5(即,导线)而配线连接的端子7A以及与绝缘基板3的上表面的电路面3b通过光纤激光而接合的端子7B是进行与外部的输入输出的AC输出端子、输入输出端子以及进行控制的信号端子。端子7A以及端子7B由厚度1mm左右的铜或者铜合金构成。
端子7A以及端子7B例如分别向电机等电动机、电池或者线束进行配线连接。
绝缘基板3呈具备绝缘材料3a以及形成于绝缘材料3a的上表面以及下表面的电路面3b的结构。绝缘材料3a是AlN、Si3N4或者Al2O3,绝缘材料3a的厚度例如小于或等于1mm。
绝缘基板3的上表面的电路面3b是铜或者铜合金。由铜或者铜合金构成的电路面3b容易氧化,因此也可以实施镀Ni或者镀Sn。
图2以及图3是放大示出本实施方式涉及的功率半导体装置的端子与绝缘基板之间的接触部分的结构的图。
如图2所例示的那样,绝缘基板3的上表面的电路面3b与端子7B之间的接合呈端子7B的下表面中的一部分与电路面3b的上表面接触的状态,即,端子7B的下表面中的其它部分不与电路面3b的上表面接触的状态。另外,在端子7B的下表面与电路面3b的上表面未接触的部位产生的间隙的尺寸不是均匀的,其尺寸例如为小于或等于20μm。
接下来,如图3所例示的那样,在如图2所示端子7B的下表面的一部分未与电路面3b的上表面接触的状态下,向端子7B的上表面、即端子7B的与电路面3b接触的面的相反侧的面,局部地照射高能量密度的光纤激光。并且,利用该照射的热量,仅使端子7B以及电路面3b熔融而形成熔融部11,与此同时,使端子7B的下表面与电路面3b的上表面接合。
在此,熔融部11的俯视观察时的尺寸例如大于或等于5mm2且小于或等于12mm2
在此,光纤激光的波长例如大于或等于500nm且小于或等于1200nm。另外,光纤激光以小于或等于1s的时间,从端子7B的上表面铅垂向下照射。
就以往的YAG激光、CO2激光或者半导体激光等而言,针对激光能量的吸收率低的铜,能量不足。但是,如果是光纤激光,则能够得到几KW的充分的输出。
图4是表示本实施方式涉及的在端子与电路面之间产生的间隙和接合强度的相关关系的例子的图。在图4中,纵轴是接合强度[MPa],横轴是间隙的尺寸[μm]。
如图4所示,作为由标准规定的接合强度,为了满足例如20MPa,在端子与电路面之间产生的间隙的尺寸需要小于或等于20μm。
在图2以及图3所例示的情况下,由于端子7B与电路面3b在一部分进行接触,因此只要实现在以不存在相接触的部位为前提的图4的相关关系下满足标准值的接合强度,则能够充分地满足所需要的接合强度。
根据以上所述,使用高能量密度的光纤激光,能够如图3所例示的那样,从端子7B的上表面到绝缘基板3的上表面的电路面3b,得到充分的焊入、即熔融部11。
另外,在同一端子7B与电路面3b之间的接合部位,通过向多个部位照射光纤激光,从而能够使端子7B与电路面3b之间的接合面积进一步变大。因此,能够提高接合的稳定性,实现可靠性高的配线连接,进而,实现功率半导体装置的长寿命化。
另外,由于光纤激光具有高能量密度,因此用于接合的照射时间非常短。具体地说,几十至几百ms/照射点即可,因此成为小于或等于1s/接合。因此,能够提高生产率。
通常,在通过YAG激光、CO2激光或者半导体激光等进行接合的情况下,需要通过按压工具等对接合部位的周围进行按压。按压工具将端子7B朝向绝缘基板3沿铅垂向下方向进行按压。
另一方面,只要使用光纤激光等高能量密度的激光而形成熔融部11,而且在端子7B与电路面3b之间产生的间隙的尺寸小于或等于20μm,则能够得到满足接合强度的标准值的接合而无需使用按压工具。
另外,近年来,特别是针对搭载于铁路或者车辆的功率半导体装置,从安装空间受到限制的观点出发,要求装置的小型化。因此,所搭载的绝缘基板3的尺寸也逐渐小型化,与此相伴,存在端子7B与电路面3b之间的接合面积也被限制得小的倾向。与此相对,如果是本实施方式涉及的端子7B与电路面3b之间的接合,则由于能够实现充分的接合强度而无需使用按压工具,因此还能够应对功率半导体装置的小型化。
另一方面,根据绝缘基板3的配置位置与端子7B的配置位置之间的关系,有时端子7B与电路面3b之间的间隙不会成为小于或等于20μm。在这样的情况下,必须使用按压工具。
在上述的情况下,是对成为弯曲形状(即,弯折形状)的部位使用按压工具进行按压,而不是端子7B与电路面3b之间的接合部位的附近。
这样,由于通过按压工具而按压的部位与接合部位远离,因此在接合部位处的端子7B的前端,大多还是如图2所示的那样产生间隙。
即使在上述的情况下,如果是本实施方式涉及的端子7B与电路面3b之间的接合,则由于在端子7B与电路面3b之间产生的间隙的尺寸小于或等于20μm,因而能够在实现良好的接合的同时得到满足标准值的接合强度。
<第2实施方式>
对本实施方式涉及的半导体装置以及半导体装置的制造方法进行说明。在以下的说明中,对与以上所记载的实施方式中说明的结构要素相同的结构要素标注相同的标号而图示,适当地省略其详细说明。
<关于功率半导体装置的结构>
图5是概略地表示本实施方式涉及的功率半导体装置的结构的例子的剖面图。在本实施方式中所例示的功率半导体装置具备:导电性金属板10A;导电性金属板10B,其与导电性金属板10A分离而配置;半导体元件1A,其经由接合材料2而与导电性金属板10B的上表面接合;半导体元件1B,其经由接合材料2而与导电性金属板10B的上表面接合;配线5,其连接半导体元件1A与半导体元件1B,将Al或者铜(Cu)作为主要成分;铜或者铜合金的端子7A,其经由金属性导电材料9而与导电性金属板10A的上表面连接;铜或者铜合金的端子7B,其经由金属性导电材料9而与导电性金属板10B的上表面连接;以及配线5,其将半导体元件1A的上表面与导电性金属板10A的上表面连接。
将端子7A的一部分、端子7B的一部分、导电性金属板10A、导电性金属板10B、半导体元件1A以及半导体元件1B使用环氧树脂类树脂等封装材料8,例如通过传递成形而封装。
上述中的导电性金属板10A以及导电性金属板10B是彼此不同的电位(电极)。
此外,也可以在导电性金属板10A的下表面以及导电性金属板10B的下表面形成有具有绝缘性的绝缘金属层。
在此,绝缘金属层是绝缘层和保护金属层的层叠构造。作为该绝缘层使用混入了氮化硼或者氧化铝等填料的环氧树脂。并且,向该绝缘层固接由热导性高的铜或者铝等构成的保护金属层。
就半导体元件1A以及半导体元件1B而言,例如设想的是作为背面电极而具备集电极电极、作为表面电极而具备栅极电极以及发射极电极的IGBT等半导体元件,或者,具有二极管功能的半导体元件。在本实施方式涉及的功率半导体装置中,将这2种半导体元件用作半导体元件1A以及半导体元件1B这一对。
通过端子7A以及端子7B而实现来自外部的信号输入,进行功率半导体装置的动作控制(具体地说,通断动作的接通/断开控制等)。半导体元件1A以及半导体元件1B不限于使用Si的IGBT、MOSFET或者二极管,也可以是例如使用SiC或者GaN的上述元件。
导电性金属板10A以及导电性金属板10B是由铜或者铜合金构成的平板。导电性金属板10A以及导电性金属板10B的厚度例如大于或等于0.2mm且小于或等于1mm。因此,就导电性金属板10A以及导电性金属板10B而言,电路上的位置不稳定,发生翘曲或倾斜。
图6是放大示出本实施方式涉及的功率半导体装置的端子与导电性金属板之间的接触部分的结构的图。
如图6所例示的那样,在端子7B与导电性金属板10B之间产生不均匀尺寸的间隙,但通过夹设金属性导电材料9,且将高能量密度的光纤激光从端子7B的上表面进行照射,从而能够使从端子7B至金属性导电材料9、进而至导电性金属板10B为止熔融而形成熔融部11A。在该状态下,导电性金属板10B的上表面与端子7B的下表面经由金属性导电材料9而接触。
在此,熔融部11A的俯视观察时的尺寸例如大于或等于5mm2且小于或等于12mm2
在此,金属性导电材料9在俯视观察时,超过导电性金属板10B与端子7B重叠的范围而形成。即,金属性导电材料9在俯视观察时,从导电性金属板10B与端子7B重叠的范围探出而形成。
此外,在导电性金属板10B的上表面与端子7B的下表面之间的接合部位,金属性导电材料9的厚度小于或等于200μm,或者,小于或等于300μm。即,在形成大于或等于20μm的间隙的情况下,为了确保接合强度而在该间隙形成金属性导电材料9。
在此,光纤激光的波长例如大于或等于500nm且小于或等于1200nm。
如上所示,在位置关系不稳定的端子7B与导电性金属板10B之间,也形成具有充分的焊入深度的熔融部11A,从而能够实现具有所需的接合强度的稳定性高的接合。因此,能够实现可靠性高的配线连接,进而实现功率半导体装置的长寿命化。
此外,在图6中,端子7B与导电性金属板10B之间的接合部位为一个部位,但如果存在多个部位的熔融部11A,则接合强度更加稳定。
<第3实施方式>
对本实施方式涉及的电力变换装置以及电力变换装置的制造方法进行说明。在以下的说明中,对与以上所记载的实施方式中说明的结构要素相同的结构要素标注相同的标号而图示,适当地省略其详细说明。
<关于电力变换装置的结构>
本实施方式是将以上所记载的实施方式涉及的功率半导体装置应用于电力变换装置。应用的电力变换装置不限定于特定的用途,但以下,对应用于三相逆变器的情况进行说明。
图7是示意地表示本实施方式涉及的包含电力变换装置的电力变换系统的结构的例子的图。
如图7所例示的那样,电力变换系统具备电源100、电力变换装置200以及负载300。电源100是直流电源,且向电力变换装置200供给直流电力。电源100能够由各种电源构成,例如,能够由直流系统、太阳能电池或者蓄电池等构成。另外,电源100也可以由与交流系统连接的整流电路或AC-DC转换器等构成。另外,也可以使电源100由将从直流系统输出的直流电力变换为规定的电力的DC-DC转换器构成。
电力变换装置200是连接在电源100和负载300之间的三相逆变器。电力变换装置200将从电源100供给的直流电力变换为交流电力,并且,向负载300供给该交流电力。
另外,电力变换装置200如图7所例示的那样,具备:变换电路201,其将直流电力变换为交流电力而输出;驱动电路202,其输出用于对变换电路201的各开关元件进行驱动的驱动信号;以及控制电路203,其将用于对驱动电路202进行控制的控制信号向驱动电路202输出。
负载300是由从电力变换装置200供给的交流电力进行驱动的三相电动机。此外,负载300不限定于特定的用途,是搭载于各种电气设备的电动机,例如,用作面向混合动力汽车、电动汽车、铁路车辆、电梯或者空调设备的电动机。
以下,对电力变换装置200的详细情况进行说明。变换电路201具备开关元件和续流二极管(在此,未图示)。并且,通过开关元件进行通断动作,从而将从电源100供给的直流电力变换为交流电力,并且,向负载300供给。
变换电路201的具体的电路结构存在各种结构,但本实施方式涉及的变换电路201是2电平的三相全桥电路,且具备6个开关元件和与各个开关元件逆并联连接的6个续流二极管。
向变换电路201的各开关元件和各续流二极管的至少一者,应用以上所记载的实施方式的任意者的功率半导体装置。6个开关元件两个两个地串联连接而构成上下桥臂,各上下桥臂构成全桥电路的各相(即,U相、V相以及W相)。并且,各上下桥臂的输出端子(即,变换电路201的3个输出端子)与负载300连接。
驱动电路202生成用于对变换电路201的开关元件进行驱动的驱动信号,并且,向变换电路201的开关元件的控制电极供给该驱动信号。具体地说,基于从后述的控制电路203输出的控制信号,向各开关元件的控制电极输出将开关元件设为接通状态的驱动信号和将开关元件设为断开状态的驱动信号。
在将开关元件维持为接通状态的情况下,驱动信号是大于或等于开关元件的阈值电压的电压信号(即,接通信号),在将开关元件维持为断开状态的情况下,驱动信号成为小于或等于开关元件的阈值电压的电压信号(即,断开信号)。
控制电路203对变换电路201的开关元件进行控制,以向负载300供给期望的电力。具体地说,基于应向负载300供给的电力,对变换电路201的各开关元件应成为接通状态的时间(即,接通时间)进行计算。例如,能够通过与应输出的电压相对应地对开关元件的接通时间进行调制的PWM控制,对变换电路201进行控制。
并且,控制电路203向驱动电路202输出控制指令(即,控制信号),以在各时刻分别向应成为接通状态的开关元件输出接通信号,向应成为断开状态的开关元件输出断开信号。驱动电路202基于该控制信号,将接通信号或者断开信号作为驱动信号而向各开关元件的控制电极输出。
在本实施方式涉及的电力变换装置200中,由于作为变换电路201的开关元件而应用以上所记载的实施方式的任意者的功率半导体装置,因此能够使经过了通电循环之后的接通电阻稳定。
此外,在本实施方式中,说明了向2电平的三相逆变器应用以上所记载的实施方式的任意者的功率半导体装置的例子,但应用例不限定于此,能够将以上所记载的实施方式的任意者的功率半导体装置应用于各种电力变换装置。
另外,在本实施方式中,对2电平的电力变换装置进行了说明,但也可以向3电平或多电平的电力变换装置应用以上所记载的实施方式的任意者的功率半导体装置。另外,在向单相负载供给电力的情况下,也可以向单相逆变器应用以上所记载的实施方式的任意者的功率半导体装置。
另外,在向直流负载等供给电力的情况下,也能够向DC-DC转换器或者AC-DC转换器应用以上所记载的实施方式的任意者的功率半导体装置。
另外,应用了以上所记载的实施方式的任意者的功率半导体装置的电力变换装置不限定于上述的负载为电动机的情况,例如,也能够用作放电加工机、激光加工机、感应加热烹调器或者非接触器供电系统的电源装置。另外,应用了以上所记载的实施方式的任意者的功率半导体装置的电力变换装置也能够用作太阳能发电系统或者蓄电系统等的功率调节器。
<关于通过以上所记载的实施方式而产生的效果>
接下来,示出通过以上所记载的实施方式而产生的效果的例子。此外,在下面的说明中,虽然是基于以上所记载的实施方式所例示的具体结构而记载该效果,但在产生相同的效果的范围,也可以与本申请说明书所例示的其他具体的结构进行置换。
另外,该置换也可以跨多个实施方式而实施。即,也可以是将在不同的实施方式中例示的各种结构组合而产生相同的效果的情况。
根据以上所记载的实施方式,功率半导体装置具备绝缘基板3、半导体元件1A以及外部端子。在此,外部端子例如是与端子7B对应的端子。绝缘基板3至少在上表面形成电路面3b。半导体元件1A经由接合材料2而配置于电路面3b的上表面。端子7B与电路面3b的上表面接合。电路面3b的上表面与端子7B的下表面的一部分接触而接合。另外,在电路面3b的上表面与端子7B接触的部位的至少一部分形成电路面3b和端子7B的熔融部11。另外,在电路面3b的上表面与端子7B的下表面之间产生的间隙的尺寸小于或等于20μm。并且,电路面3b以及端子7B均为铜或者铜合金。
根据上述的结构,通过熔融部11,在电路面3b与端子7B之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。因此,能够提高功率半导体装置的可靠性。另外,无需为了形成具有充分的接合强度的接合而使用焊料等接合材料,因此,能够缓和由于不同种类金属即接合材料2与端子7B、电路面3b之间的热膨胀系数的差而产生的热应力或者热变形的影响。另外,熔融部11仅以从端子7B到达电路面3b为止的深度而形成,没有到达位于电路面3b的下方的绝缘材料3a。因此,还能够维持绝缘基板3的绝缘性。
此外,能够适当省略除上述结构以外的本申请说明书所例示的其它结构。即,只要至少具备上述结构,则能够产生以上所记载的效果。
但是,即使在向以上所记载的结构适当追加了本申请说明书所例示的其它结构中的至少1个的情况下、即适当追加了没有作为以上所记载的结构而提及的本申请说明书所例示的其它结构的情况下,也能够产生同样的效果。
此外,熔融部例如如《溶接の事典》(“蓮井淳、橋本達哉、太田省三郎著、朝倉書店出版”、225页)所记载的那样,是表示熔填材料熔融后的焊接金属与母材(被焊接或者切断的材料)熔融后的状态的用语。另外,熔填材料熔融后的焊接金属与母材熔融后的状态例如是指,通过直至熔融为止的端子7B和电路面3b的流动痕迹的有无等,从而明显区别于未熔融的端子7B以及电路面3b的构造(由于急剧的热经历,晶粒不同)。
因此,“熔融部”这一用语是仅是通过示出状态而确定出物体的构造或者物体的特性的用语。
另外,根据以上所记载的实施方式,功率半导体装置具备将绝缘基板3、半导体元件1A以及一部分的端子7B覆盖而形成的封装材料8。根据上述的结构,还能够通过封装材料8而确保绝缘性能。因此,能够提高功率半导体装置的可靠性。
另外,根据以上所记载的实施方式,功率半导体装置具备散热板4,该散热板4经由接合材料2而与绝缘基板3的下表面连接。并且,散热板4的下表面从封装材料8露出。根据上述的结构,通过散热板4而确保热容量,并且散热板4从封装材料8露出而向外部散热,由此半导体元件1A以及半导体元件1B能够得到损耗小的所希望的通断功能。
另外,根据以上所记载的实施方式,形成多个熔融部11。根据上述的结构,通过在端子7B与电路面3b之间的接合部位设置多个熔融部11,从而能够使端子7B与电路面3b之间的接合面积更大。此外,光纤激光的照射范围例如大于或等于几μm且小于或等于几百μm,是较窄的范围,因此通过在1个接合部位形成多个熔融部11,从而使接合面积变大是有效的。因此,能够使接合的稳定性提高,实现可靠性高的配线连接,进而,实现功率半导体装置的长寿命化。另外,即使在发生了光纤激光的输出异常或者热量输入异常等的情况下,也可以通过形成多个熔融部11,从而抑制接合变得不稳定。
另外,根据以上所记载的实施方式,功率半导体装置具备金属板、半导体元件1A以及端子7B。在此,金属板例如是与导电性金属板10B对应的金属板。半导体元件1A经由接合材料2而配置于导电性金属板10B的上表面。端子7B与导电性金属板10B的上表面接合。导电性金属板10B的上表面与端子7B的下表面经由导电材料而接触。在此,导电材料例如是与金属性导电材料9对应的材料。在导电性金属板10B的上表面与端子7B的下表面接触的部位的至少一部分形成导电性金属板10B、端子7B和金属性导电材料9的熔融部11A。金属性导电材料9的厚度小于或等于300μm。并且,导电性金属板10B以及端子7B均为铜或者铜合金。
根据上述的结构,通过熔融部11A,从而夹在导电性金属板10B的上表面与端子7B之间的金属性导电材料9确保接合强度,因此能够抑制接合强度的波动。因此,能够提高功率半导体装置的可靠性。另外,在导电性金属板10B是薄板,且在电路上成为悬臂梁形状的情况下,导电性金属板10B的上表面与端子7B之间的定位(特别地,在导电性金属板10B挠曲的方向上的端子7B的定位)变得困难,但只要在导电性金属板10B的上表面与端子7B之间预先设置金属性导电材料9,则通过使用光纤激光而将导电性金属板10B的上表面与端子7B经由金属性导电材料9接合,从而使得定位变得容易。
此外,能够适当省略除上述结构以外的本申请说明书所例示的其它结构。即,只要至少具备上述结构,则能够产生以上所记载的效果。
但是,即使在向以上所记载的结构适当追加了本申请说明书所例示的其它结构中的至少1个的情况下、即适当追加了没有作为以上所记载的结构而提及的本申请说明书所例示的其它结构的情况下,也能够产生同样的效果。
另外,根据以上所记载的实施方式,功率半导体装置具备将导电性金属板10B、半导体元件1A、半导体元件1B、以及一部分的端子7B覆盖而形成的封装材料8。根据上述的结构,还能够通过封装材料8而确保绝缘性能。因此,能够提高功率半导体装置的可靠性。
另外,根据以上所记载的实施方式,金属性导电材料9在俯视观察时,超过导电性金属板10B与端子7B重叠的范围而形成。根据上述的结构,通过向在将导电性金属板10B的上表面与端子7B接合时所产生的间隙埋入金属性导电材料9,从而不会产生间隙,能够形成稳定性高的接合。
另外,根据以上所记载的实施方式,形成多个熔融部11A。根据上述的结构,通过在端子7B与导电性金属板10B之间的接合部位设置多个熔融部11A,从而能够使端子7B与导电性金属板10B之间的接合面积更大。此外,光纤激光的照射范围例如大于或等于几μm且小于或等于μm,是较窄的范围,因此通过在1个接合部位形成多个熔融部11A从而使接合面积变大是有效的。因此,能够使接合的稳定性提高,实现可靠性高的配线连接,进而实现功率半导体装置的长寿命化。另外,即使在发生了光纤激光的输出异常或者热量输入异常等的情况下,也可以通过形成多个熔融部11A,从而抑制接合变得不稳定。
另外,根据以上所记载的实施方式,电力变换装置具备:变换电路201,其具有上述的功率半导体装置,且变换电路201将被输入进来的电力进行变换而输出;驱动电路202,其将用于对功率半导体装置进行驱动的驱动信号向功率半导体装置输出;以及控制电路203,其将用于对驱动电路202进行控制的控制信号向驱动电路202输出。根据上述的结构,通过熔融部,从而在被接合材料与外部端子之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。因此,能够提高电力变换装置的可靠性。
根据以上所记载的实施方式,在功率半导体装置的制造方法中,准备绝缘基板3,该绝缘基板3至少在上表面形成电路面3b。并且,在电路面3b的上表面经由接合材料2而配置半导体元件1A。并且,在电路面3b的上表面配置端子7B,然后,对端子7B的上表面照射光纤激光,从而将端子7B的下表面与电路面3b的上表面接合。并且,电路面3b的上表面与端子7B的下表面的一部分接触而接合。并且,在电路面3b的上表面与端子7B的下表面接触的部位的至少一部分形成电路面3b和端子7B的熔融部11。并且,在电路面3b的上表面与端子7B的下表面之间产生的间隙的尺寸小于或等于20μm。
根据上述的结构,通过使用光纤激光而形成熔融部11,从而在电路面3b与端子7B之间产生的间隙的尺寸小于或等于20μm,因此能够抑制接合强度的波动。因此,能够提高功率半导体装置的可靠性。光纤激光是基波波长,但能够期待高能量密度以及高功率输出。因此,能够通过使用光纤激光而形成具有期望的焊入深度以及接合面积的熔融部11。由此,能够形成具有充分的接合强度的可靠性高的接合。另外,光纤激光能够期待高能量密度以及高功率输出,因此能够将用于形成接合的激光的照射时间设为例如大于或等于几十ms且小于或等于几百ms的较短的时间。由此,能够提高功率半导体装置的制造效率,抑制制造成本。另外,在功率半导体装置内的端子的接合部位的周围分散存在有半导体元件、绝缘基板或者由树脂构成的壳体等如果通过光纤激光而直接照射光则由于激光热而被破坏的结构要素。因此,通过仅对具有期望的热容量的端子直接照射光纤激光,从而能够向端子赋予充分的热量而形成期望的接合形状(特别地,具有期望的焊入深度的接合形状),并且抑制对分散存在于端子的接合部位的周围处的结构要素的损伤。
此外,能够适当省略除上述结构以外的本申请说明书所例示的其它结构。即,只要至少具备上述结构,则能够产生以上所记载的效果。
但是,即使在向以上所记载的结构适当追加了本申请说明书所例示的其它结构中的至少1个的情况下、即适当追加了没有作为以上所记载的结构而提及的本申请说明书所例示的其它结构的情况下,也能够产生同样的效果。
另外,在没有特别的限制的情况下,能够变更进行各处理的顺序。
另外,根据以上所记载的实施方式,通过对端子7B的上表面照射波长大于或等于500nm且小于或等于1200nm的光纤激光,从而将端子7B与电路面3b的上表面接合。根据上述的结构,在端子7B为将铜作为主要成分的结构的情况下,能够有效地提高端子7B的热量的吸收率,而不需要使用用于提高热量的吸收率的Ni镀层等。因此,能够抑制制造成本,且还能够缩短激光照射工序的所需时间(例如,小于或等于1s左右)。
另外,根据以上所记载的实施方式,在功率半导体装置的制造方法中,准备导电性金属板10B。并且,在导电性金属板10B的上表面经由接合材料2而配置半导体元件1A。并且,在导电性金属板10B的上表面经由金属性导电材料9而配置端子7B,然后对端子7B的上表面照射光纤激光,从而将端子7B的下表面经由金属性导电材料9而与导电性金属板10B的上表面接合。并且,导电性金属板10B的上表面与端子7B的下表面经由金属性导电材料9而接触。并且,在导电性金属板10B的上表面与端子7B的下表面接触的部位的至少一部分形成导电性金属板10B、端子7B和金属性导电材料9的熔融部11A。并且,金属性导电材料9的厚度小于或等于300μm。
根据上述的结构,通过使用光纤激光形成熔融部11A,从而夹在导电性金属板10B的上表面与端子7B之间的金属性导电材料9确保接合强度,因此能够抑制接合强度的波动。因此,能够提高功率半导体装置的可靠性。光纤激光是基波波长,但能够期待高能量密度以及高功率输出。因此,能够通过使用光纤激光而形成具有期望的焊入深度以及接合面积的熔融部11A。由此,能够形成具有充分的接合强度的可靠性高的接合。
此外,能够适当省略除上述结构以外的本申请说明书所例示的其它结构。即,只要至少具备上述结构,则能够产生以上所记载的效果。
但是,即使在向以上所记载的结构适当追加了本申请说明书所例示的其它结构中的至少1个的情况下、即适当追加了没有作为以上所记载的结构而提及的本申请说明书所例示的其它结构的情况下,也能够产生同样的效果。
另外,在没有特别的限制的情况下,能够变更进行各处理的顺序。
另外,根据以上所记载的实施方式,通过对端子7B的上表面照射波长大于或等于500nm且小于或等于1200nm的光纤激光,从而将端子7B的下表面经由金属性导电材料9而与导电性金属板10B的上表面接合。根据这样的结构,在端子7B为将铜作为主要成分的结构的情况下,能够有效地提高端子7B的热量的吸收率,而不需要使用用于提高热量的吸收率的Ni镀层等。
另外,根据以上所记载的实施方式,在电力变换装置的制造方法中,设置变换电路201,变换电路201具有通过上述的制造方法制造的功率半导体装置,且变换电路201将被输入进来的电力进行变换而输出。并且,设置驱动电路202,该驱动电路202将用于对功率半导体装置进行驱动的驱动信号向功率半导体装置输出。并且,设置控制电路203,该控制电路203将用于对驱动电路202进行控制的控制信号向驱动电路202输出。根据上述的结构,能够通过熔融部而抑制接合强度的波动。因此,能够提高电力变换装置的可靠性。
<关于以上所记载的实施方式的变形例>
在以上所记载的实施方式中,有时还记载了各个结构要素的材质、材料、尺寸、形状、相对配置关系或者实施条件等,但这些在所有方面都为1个例子,并不限定于本申请说明书所记载的内容。
因此,在本申请说明书所公开的技术的范围内,可想到未例示的无数变形例以及等价物。例如,包含对至少1个结构要素进行变形的情况、进行追加的情况或者进行省略的情况、以及将至少1个实施方式中的至少1个结构要素提取而与其它实施方式的结构要素进行组合的情况。
另外,在不出现矛盾的情况下,在以上所记载的实施方式中,作为具备“1个”而记载的结构要素也可以是具备“大于或等于1个”。
并且,以上所记载的实施方式中的各个结构要素是概念性单位,在本申请说明书所公开的技术的范围内,包含1个结构要素由多个构造物构成的情况、1个结构要素对应于某个构造物的一部分的情况、以及多个结构要素包含于1个构造物的情况。
另外,就以上所记载的实施方式中的各个结构要素而言,只要发挥相同的功能,就包含具有其它构造或形状的构造物。
另外,本申请说明书中的说明是用于实现本技术涉及的所有目的而参照的,均不能认为是现有技术。
另外,在以上所记载的实施方式中,在记载了材料名称等但没有特别指定的情况下,只要不出现矛盾,则包括该材料中包含其它添加物的例如合金等。

Claims (16)

1.一种半导体装置,其具备:
绝缘基板,其至少在上表面形成电路面;
半导体元件,其经由接合材料而配置于所述电路面的上表面;以及
外部端子,其与所述电路面的上表面接合,
所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,
在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,
在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm,
所述电路面以及所述外部端子均为铜或者铜合金。
2.根据权利要求1所述的半导体装置,其中,
还具备将所述绝缘基板、所述半导体元件以及一部分的所述外部端子覆盖而形成的封装材料。
3.根据权利要求2所述的半导体装置,其中,
还具备散热板,该散热板经由接合材料而与所述绝缘基板的下表面连接,
所述散热板的下表面从所述封装材料露出。
4.根据权利要求1至3中任一项所述的半导体装置,其中,
形成多个所述熔融部。
5.一种电力变换装置,其具备:
变换电路,其具有权利要求1至4中任一项所述的半导体装置,且该变换电路将被输入进来的电力进行变换而输出;
驱动电路,其将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出;以及
控制电路,其将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
6.一种半导体装置,其具备:
金属板;
半导体元件,其经由接合材料而配置于所述金属板的上表面;以及
外部端子,其与所述金属板的上表面接合,
所述金属板的上表面与所述外部端子的下表面经由导电材料而接触,
在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部,
所述金属板以及所述外部端子均为铜或者铜合金。
7.根据权利要求6所述的半导体装置,其中,
还具备将所述金属板、所述半导体元件以及一部分的所述外部端子覆盖而形成的封装材料。
8.根据权利要求6或7所述的半导体装置,其中,
所述导电材料在俯视观察时超过所述金属板与所述外部端子重叠的范围而形成。
9.根据权利要求6至8中任一项所述的半导体装置,其中,
形成多个所述熔融部。
10.一种电力变换装置,其具备:
变换电路,其具有权利要求6至9中任一项所述的半导体装置,且该变换电路将被输入进来的电力进行变换而输出;
驱动电路,其将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出;以及
控制电路,其将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
11.一种半导体装置的制造方法,其中,
准备绝缘基板,该绝缘基板至少在上表面形成电路面,
经由接合材料而将半导体元件配置于所述电路面的上表面,
在所述电路面的上表面配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面与所述电路面的上表面接合,
所述电路面的上表面与所述外部端子的下表面的一部分接触而接合,
在所述电路面的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述电路面和所述外部端子的熔融部,
在所述电路面的上表面与所述外部端子的下表面之间产生的间隙的尺寸小于或等于20μm。
12.根据权利要求11所述的半导体装置的制造方法,其中,
通过对所述外部端子的上表面照射波长大于或等于500nm且小于或等于1200nm的光纤激光,从而将所述外部端子的下表面与所述电路面的上表面接合。
13.一种电力变换装置的制造方法,其中,
设置变换电路,该变换电路具有通过权利要求11或12所述的制造方法制造的半导体装置,且该变换电路将被输入进来的电力进行变换而输出,
设置驱动电路,该驱动电路将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出,
设置控制电路,该控制电路将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
14.一种半导体装置的制造方法,其中,
准备金属板,
经由接合材料而将半导体元件配置于所述电路面的上表面,
在所述金属板的上表面经由导电材料而配置外部端子,然后对所述外部端子的上表面照射光纤激光,从而将所述外部端子的下表面经由所述导电材料而与所述金属板的上表面接合,
所述金属板的上表面与所述外部端子的下表面经由所述导电材料而接触,
在所述金属板的上表面与所述外部端子的下表面接触的部位的至少一部分形成所述金属板、所述外部端子和所述导电材料的熔融部。
15.根据权利要求14所述的半导体装置的制造方法,其中,
通过对所述外部端子的上表面照射波长大于或等于500nm且小于或等于1200nm的光纤激光,从而将所述外部端子的下表面经由所述导电材料而与所述金属板的上表面接合。
16.一种电力变换装置的制造方法,其中,
设置变换电路,该变换电路具有通过权利要求14或15所述的制造方法制造的半导体装置,且该变换电路将被输入进来的电力进行变换而输出,
设置驱动电路,该驱动电路将用于对所述半导体装置进行驱动的驱动信号向所述半导体装置输出,
设置控制电路,该控制电路将用于对所述驱动电路进行控制的控制信号向所述驱动电路输出。
CN201910650002.8A 2018-07-23 2019-07-18 半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法 Pending CN110828409A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018137588A JP7005449B2 (ja) 2018-07-23 2018-07-23 半導体装置、電力変換装置、半導体装置の製造方法、および、電力変換装置の製造方法
JP2018-137588 2018-07-23

Publications (1)

Publication Number Publication Date
CN110828409A true CN110828409A (zh) 2020-02-21

Family

ID=69148034

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910650002.8A Pending CN110828409A (zh) 2018-07-23 2019-07-18 半导体装置、电力变换装置、半导体装置的制造方法及电力变换装置的制造方法

Country Status (4)

Country Link
US (2) US11183457B2 (zh)
JP (1) JP7005449B2 (zh)
CN (1) CN110828409A (zh)
DE (1) DE102019210172A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11025031B2 (en) 2016-11-29 2021-06-01 Leonardo Electronics Us Inc. Dual junction fiber-coupled laser diode and related methods
WO2020036998A1 (en) * 2018-08-13 2020-02-20 Lasertel, Inc. Use of metal-core printed circuit board (pcb) for generation of ultra-narrow, high-current pulse driver
DE102019121924A1 (de) 2018-08-14 2020-02-20 Lasertel, Inc. Laserbaugruppe und zugehörige verfahren
US11296481B2 (en) 2019-01-09 2022-04-05 Leonardo Electronics Us Inc. Divergence reshaping array
US11752571B1 (en) 2019-06-07 2023-09-12 Leonardo Electronics Us Inc. Coherent beam coupler
US20210043466A1 (en) * 2019-08-06 2021-02-11 Texas Instruments Incorporated Universal semiconductor package molds
EP3958305B1 (en) * 2020-08-17 2023-09-27 Infineon Technologies AG Power semiconductor module arrangement and method for producing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11185838A (ja) * 1997-12-24 1999-07-09 Harness Syst Tech Res Ltd レーザ溶接構造
JP2008205058A (ja) * 2007-02-19 2008-09-04 Fuji Electric Device Technology Co Ltd 半導体装置
JP2009147124A (ja) * 2007-12-14 2009-07-02 Mitsubishi Cable Ind Ltd 溶接構造及びその製造方法、並びにそれを備えた電子回路基板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4765853B2 (ja) * 2006-09-08 2011-09-07 富士電機株式会社 半導体装置の製造方法
US20120001336A1 (en) * 2010-07-02 2012-01-05 Texas Instruments Incorporated Corrosion-resistant copper-to-aluminum bonds
EP2962799B8 (de) * 2014-07-04 2016-10-12 ABB Schweiz AG Halbleitermodul mit Ultraschall geschweißten Anschlüssen
JP6537815B2 (ja) * 2014-12-11 2019-07-03 株式会社ジェイデバイス 半導体パッケージ及びその製造方法
WO2017195625A1 (ja) 2016-05-11 2017-11-16 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2018061000A (ja) * 2016-09-30 2018-04-12 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子及び撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11185838A (ja) * 1997-12-24 1999-07-09 Harness Syst Tech Res Ltd レーザ溶接構造
JP2008205058A (ja) * 2007-02-19 2008-09-04 Fuji Electric Device Technology Co Ltd 半導体装置
JP2009147124A (ja) * 2007-12-14 2009-07-02 Mitsubishi Cable Ind Ltd 溶接構造及びその製造方法、並びにそれを備えた電子回路基板

Also Published As

Publication number Publication date
JP2020017562A (ja) 2020-01-30
US11183457B2 (en) 2021-11-23
JP7005449B2 (ja) 2022-01-21
US20220028794A1 (en) 2022-01-27
DE102019210172A1 (de) 2020-01-23
US20200027839A1 (en) 2020-01-23

Similar Documents

Publication Publication Date Title
JP7005449B2 (ja) 半導体装置、電力変換装置、半導体装置の製造方法、および、電力変換装置の製造方法
JP6881238B2 (ja) 半導体モジュール、その製造方法及び電力変換装置
JP7026451B2 (ja) パワー半導体モジュール及びその製造方法並びに電力変換装置
CN109698179B (zh) 半导体装置及半导体装置的制造方法
JP6987031B2 (ja) 電力用半導体装置及びその製造方法、並びに、電力変換装置
JP5899952B2 (ja) 半導体モジュール
JP6575739B1 (ja) 半導体装置、半導体装置の製造方法および電力変換装置
WO2019043950A1 (ja) 半導体モジュール及び電力変換装置
WO2020245880A1 (ja) 半導体モジュールおよび電力変換装置
JP2018067611A (ja) 半導体装置および電力変換装置
JP2020092223A (ja) 半導体装置および電力変換装置
JP2012222000A (ja) 半導体モジュール及びその製造方法
US11887903B2 (en) Power semiconductor device, method for manufacturing power semiconductor device, and power conversion apparatus
WO2022049660A1 (ja) 半導体装置、電力変換装置、および移動体
JP6885522B1 (ja) 半導体装置、電力変換装置および半導体装置の製造方法
JP5659171B2 (ja) 半導体装置およびそれを用いたインバータ装置
WO2021100199A1 (ja) 半導体装置およびその製造方法ならびに電力変換装置
JP2023173556A (ja) 半導体モジュールの製造方法、電力変換装置の製造方法、半導体モジュール、電力変換装置
WO2019171684A1 (ja) 半導体装置及び電力変換装置
JP2021190653A (ja) 半導体装置及び電力変換装置
CN117438404A (zh) 半导体装置、半导体装置的制造方法以及电力变换装置
CN117438386A (zh) 半导体装置、半导体装置的制造方法及电力转换装置
CN116031226A (zh) 半导体装置及电力转换装置
JP2022059117A (ja) 半導体装置、半導体装置の製造方法及び電力変換装置
CN117769761A (zh) 功率模块以及电力转换装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination