CN110783412A - 基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管及制备方法 - Google Patents

基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管及制备方法 Download PDF

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CN110783412A
CN110783412A CN201910999810.5A CN201910999810A CN110783412A CN 110783412 A CN110783412 A CN 110783412A CN 201910999810 A CN201910999810 A CN 201910999810A CN 110783412 A CN110783412 A CN 110783412A
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宁洪龙
刘贤哲
姚日晖
袁炜健
张旭
张观广
梁志豪
梁宏富
邱斌
彭俊彪
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South China University of Technology SCUT
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Abstract

本发明属于薄膜晶体管技术领域,涉及一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管,包括依次设置的:衬底、栅极、栅极绝缘层、有源层和源漏电极,其中:栅极绝缘层是由等离子体增强原子层沉积制备的氧化铝薄膜,有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜。本发明的氧化锡基薄膜晶体管采用等离子体增强原子层沉积法制备高介电常数的氧化铝作为栅极绝缘层,并且使用非晶硅掺杂氧化锡半导体材料作为有源层材料,降低了有源层/栅极绝缘层界面缺陷态和器件的开启电压,显著地提高了器件迁移率和稳定性。本发明还提供一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法。

Description

基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶 体管及制备方法
技术领域
本发明属于薄膜晶体管技术领域,涉及一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管及制备方法。
背景技术
目前,平板显示技术发展迅速,大尺寸、高分辨、高刷新率显示器成为主流。其中,平板显示行业的核心技术为薄膜晶体管(TFT)背板技术,提高TFT的性能和降低生产成本至关重要。传统的TFT中,氧化硅或者氮化硅作为栅极绝缘层。由于它们的介电常数低(约3.9)、电容小,通常导致器件迁移率小和“开态”电流低。高介电常数的绝缘层材料具有高介电常数、相对低的漏电流和宽带隙等优点,能够降低器件的工作电压,显著地提高器件性能。
发明内容
针对现有技术的不足,本发明提供一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管。
本发明还提供一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法。
本发明采用如下技术方案实现:
基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管,包括依次设置的:衬底、栅极、栅极绝缘层、有源层和源漏电极,其中:栅极绝缘层是由等离子体增强原子层沉积制备的氧化铝薄膜,有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜。
进一步地,所述栅极绝缘层的材料为氧化铝材料,铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃。
进一步地,所述有源层的半导体材料为硅掺杂氧化锡SiSnO,SiO2掺杂重量为3~5wt%;有源层厚度为5~10nm。
优选地,有源层制备工艺为溅射功率为50~110W,工作压强为2~5mtorr,溅射气体为氩气和氧气混合。
优选地,所述衬底包括:玻璃衬底或柔性衬底;所述柔性衬底包括PI、PEN或PET。
优选地,源漏电极材料包括:Al、Mo、Cu或ITO。
基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法,包括步骤:
S1、在室温下,通过直流磁控溅射在衬底上制备导电薄膜并图形化,作为栅极;
S2、在栅极上,通过等离子体增强原子层沉积技术生长绝缘薄膜,作为栅极绝缘层;
S3、将衬底在热台上进行热处理;
S4、在所述栅极绝缘层上,通过射频磁控溅射制备非晶SiSnO薄膜并图形化,作为有源层;
S5、在所述有源层上,通过直流磁控溅射沉积制备导电薄膜并图形化,作为源/漏电极,得到基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管。
进一步地,步骤S2中栅极绝缘层的材料为氧化铝材料,铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃。
优选地,步骤S3中热处理条件为在空气中,加热温度为150~250℃,退火时间为30~60min。
进一步地,步骤S4中有源层制备工艺为溅射功率为50~110W,工作压强为2~5mtorr,溅射气体为氩气和氧气混合;有源层制备完成后,进行热处理,退火温度在250~350℃,退火时间为30~60min。
本发明的制备方法和所得到的薄膜晶体管具有如下优点及有益效果:
(1)采用等离子体增强原子层沉积法制备高介电常数的氧化铝作为栅极绝缘层,并且使用非晶硅掺杂氧化锡半导体材料作为有源层材料,降低了有源层/栅极绝缘层界面缺陷态和器件的开启电压,显著地提高器件迁移率和稳定性。
(2)采用低成本环保型硅掺杂氧化锡半导体材料作为有源层材料,高介电常数的氧化铝作为栅极绝缘层,制备工艺简单,成本低,获得高性能薄膜晶体管,有利于实现薄膜晶体管柔性制备。
附图说明
图1为本发明一个实施例中的金属-绝缘层-金属结构示意图。其中,11为Al,12为AlOx,13为Al。
图2为本发明一个实施例中不同厚度的氧化铝的电容-频率曲线。其中,样品经过350℃,30min退火;曲线21,22和23分别对应氧化铝厚度为50,100和200nm;频率变化从1k~1MHz。
图3为本发明一个实施例中不同厚度的氧化铝的电流-电压曲线。其中,样品经过350℃,30min退火;曲线31,32和33分别对应氧化铝厚度为50,100和200nm;电压变化从0~-50V。
图4为本发明一个实施例中为SiSnO-TFT的转移特性曲线。其中SiO2掺杂重量为5wt%;曲线41和42分别为100和200nm的原子层沉积的氧化铝;有源层的材料为SiSnO且厚度为5nm;测试条件为源/漏电压VDS=30.1V,栅极扫描电压VGS=-30~30V。
图5为本发明一个实施例中为SiSnO-TFT的偏压稳定性。其中,氧化铝厚度为100nm;有源层的材料为SiSnO,厚度为5nm;曲线51、52、53、54和55分别对应偏压时间为0、900、1800,2700和3600s;施加偏压条件为VGS=10V,VDS=0V;测试条件为源/漏电压VDS=30.1V,栅极扫描电压VGS=-30~30V。
具体实施方式
下面结合实施例及附图对本发明作进一步详细的描述,但本发明的实施方式不限于此。
一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管,包括依次设置的:衬底、栅极、栅极绝缘层、有源层和源漏电极,其中:栅极绝缘层是由等离子体增强原子层沉积制备的氧化铝薄膜,有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜。
本发明引入高质量的氧化铝作为栅极绝缘层,改善了栅极绝缘层/有源层界面质量,有效地提高器件迁移率和稳定性。通过原子层沉积制备氧化铝薄膜,栅极绝缘层的材料为氧化铝材料,其中铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃,薄膜(栅极绝缘层)厚度为50~200nm。
现有的原子层沉积工艺通常需要高温加热提供反应能量,同时高反应温度又会造成反应物(金属有机化合物)分解或者脱附,从而造成反应不充分,且沉积薄膜中杂质含量高。本发明制作栅极绝缘层的工艺利用等离子提供反应能量,无需高温加热,有效地避免反应物的分解和脱附,保证薄膜沉积顺利进行。本工艺的优点在于沉积温度低,能够充分的去除多余的反应物和生成物,薄膜均匀性好,杂质含量低。
本发明的有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜,有源层的半导体材料为硅掺杂氧化锡(SiSnO),其中SiO2掺杂重量为3~5wt%;有源层厚度为5~10nm。
由于本发明的有源层材料不含铟(In)元素,因此该材料具有成本低廉、无毒、无污染、环境友好等优点。同时,该材料具有很强的抗酸特性,无需刻蚀阻挡层的保护,能够有效地降低生产成本。
衬底包括:玻璃衬底或者柔性衬底;所述柔性衬底包括PI、PEN或者PET。
源漏电极材料包括:Al、Mo、Cu或者ITO。
一种基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法,包括如下步骤:
S1、在室温下,通过直流磁控溅射在衬底上制备导电薄膜并图形化,作为栅极;
S2、在栅极上,通过等离子体增强原子层沉积技术生长绝缘薄膜,作为栅极绝缘层;
栅极绝缘层的材料为氧化铝材料,其中铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃,薄膜厚度为50~200nm。
S3、将衬底在热台上进行热处理;
热处理条件为在空气中,加热温度为150~250℃,退火时间为30~60min。
S4、在所述栅极绝缘层上,通过射频磁控溅射制备非晶SiSnO薄膜并图形化,作为有源层;
有源层制备工艺为溅射功率为50~110W,工作压强为2~5mtorr,溅射气体为氩气和氧气混合。
有源层制备完成后,进行热处理,退火温度在250~350℃,退火时间为30~60min。
S5、在所述有源层上,通过直流磁控溅射沉积制备导电薄膜并图形化,作为源/漏电极,得到基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管。
下面结合附图对本发明作进一步详细说明。
图1为金属-绝缘层-金属示意图,用来表征绝缘层的特性,测试绝缘层的电容大小、介电常数、击穿电压、漏电流。图2和3分别为电容-频率和电流-电压曲线。其中绝缘层厚度分别为50、100和200nm。
由以上结果可以看出,不同厚度下的氧化铝都具有较高的电容频率响应,可以很好地避免电信号的延迟或失真。50、100和200nm的氧化铝的电容分别为206.37、94.11和48.41nF/cm2。50、100和200nm的氧化铝的介电常数分别为11.66、10.63和10.94。原子层沉积的氧化铝的耐击穿电压大于50V且漏电流低于10-9A。
图4为硅掺杂氧化锡薄膜晶体管的转移特性曲线。其中100和200nm氧化铝的电容大小分别为94.11和56.48nF/cm2。100nm氧化铝栅极绝缘层器件的开启电压为-5V,“开态”电流为1.8×10-4A,器件迁移率为9.75cm2/Vs,亚阈值摆幅为0.71V/decade;200nm氧化铝栅极绝缘层器件的开启电压为-10V,“开态”电流为5.05×10-5A,器件迁移率为2.81cm2/Vs,亚阈值摆幅为1.27V/decade。
由以上结果可以看出,栅极绝缘层厚度为100nm的器件具有较高的器件性能:开启电压小、“开态”电流大、迁移率高及亚阈值摆幅小,说明在低栅极电压条件下,半导体和绝缘层界面处能够积累更多的载流子,形成导电沟道,可以有效地降低能耗;同时,栅极绝缘层与有源层形成较好的接触界面,降低载流子在界面出散射,获得较大的“开态”电流和器件迁移率。
图5为硅掺杂氧化锡薄膜晶体管在偏压稳定性下的转移特性曲线。其中施加偏压条件为VGS=10V,VDS=0V;转移曲线几乎没有移动,开启电压仅正向移动0.05V。
由以上结果可以看出,等离子体增强原子层沉积的氧化铝作为栅极绝缘层能很好的提高薄膜晶体管的稳定性。
上述实施例为本发明较佳的实施方式,但本发明的实施方式并不受上述实施例的限制,其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本发明的保护范围之内。

Claims (10)

1.基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管,其特征在于,包括依次设置的:衬底、栅极、栅极绝缘层、有源层和源漏电极,其中:栅极绝缘层是由等离子体增强原子层沉积制备的氧化铝薄膜,有源层是通过磁控溅射沉积制备的硅掺杂氧化锡薄膜。
2.根据权利要求1所述的氧化锡基薄膜晶体管,其特征在于,所述栅极绝缘层的材料为氧化铝材料,铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃。
3.根据权利要求1所述的氧化锡基薄膜晶体管,其特征在于,所述有源层的半导体材料为硅掺杂氧化锡SiSnO,SiO2掺杂重量为3~5wt%;有源层厚度为5~10nm。
4.根据权利要求1所述的氧化锡基薄膜晶体管,其特征在于,有源层制备工艺为溅射功率为50~110W,工作压强为2~5mtorr,溅射气体为氩气和氧气混合。
5.根据权利要求1所述的氧化锡基薄膜晶体管,其特征在于,所述衬底包括:玻璃衬底或柔性衬底;所述柔性衬底包括PI、PEN或PET。
6.根据权利要求1所述的氧化锡基薄膜晶体管,其特征在于,源漏电极材料包括:Al、Mo、Cu或ITO。
7.基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管制备方法,其特征在于,包括步骤:
S1、在室温下,通过直流磁控溅射在衬底上制备导电薄膜并图形化,作为栅极;
S2、在栅极上,通过等离子体增强原子层沉积技术生长绝缘薄膜,作为栅极绝缘层;
S3、将衬底在热台上进行热处理;
S4、在所述栅极绝缘层上,通过射频磁控溅射制备非晶SiSnO薄膜并图形化,作为有源层;
S5、在所述有源层上,通过直流磁控溅射沉积制备导电薄膜并图形化,作为源/漏电极,得到基于等离子体增强原子层沉积栅极绝缘层的氧化锡基薄膜晶体管。
8.根据权利要求7所述的制备方法,其特征在于,步骤S2中栅极绝缘层的材料为氧化铝材料,铝料是三甲基铝,反应气体为氧气,反应温度为80~100℃。
9.根据权利要求7所述的制备方法,其特征在于,步骤S3中热处理条件为在空气中,加热温度为150~250℃,退火时间为30~60min。
10.根据权利要求7所述的制备方法,其特征在于,步骤S4中有源层制备工艺为溅射功率为50~110W,工作压强为2~5mtorr,溅射气体为氩气和氧气混合;有源层制备完成后,进行热处理,退火温度在250~350℃,退火时间为30~60min。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111218658A (zh) * 2020-02-26 2020-06-02 北京工业大学 一种高电导率Mo金属薄膜结构及其制备方法和应用

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030218221A1 (en) * 2002-05-21 2003-11-27 the State of Oregon acting by and through the behalf of Oregon State University Transistor structures and methods for making the same
CN107464848A (zh) * 2017-06-21 2017-12-12 北京大学深圳研究生院 底栅氧化物半导体薄膜晶体管及其制备方法
CN107731930A (zh) * 2017-10-12 2018-02-23 华南理工大学 一种氧化锡基半导体薄膜晶体管及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030218221A1 (en) * 2002-05-21 2003-11-27 the State of Oregon acting by and through the behalf of Oregon State University Transistor structures and methods for making the same
CN107464848A (zh) * 2017-06-21 2017-12-12 北京大学深圳研究生院 底栅氧化物半导体薄膜晶体管及其制备方法
CN107731930A (zh) * 2017-10-12 2018-02-23 华南理工大学 一种氧化锡基半导体薄膜晶体管及其制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JAE BON KOO ETAL: "Pentacene thin-film transistors and inverters with plasma-enhanced atomic-layer-deposited Al2O3 gate dielectric", 《THIN SOLID FILMS》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111218658A (zh) * 2020-02-26 2020-06-02 北京工业大学 一种高电导率Mo金属薄膜结构及其制备方法和应用
CN111218658B (zh) * 2020-02-26 2022-02-01 北京工业大学 一种高电导率Mo金属薄膜结构及其制备方法和应用

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