CN110781106A - Universal flash memory host end chip device and equipment - Google Patents
Universal flash memory host end chip device and equipment Download PDFInfo
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- CN110781106A CN110781106A CN201910838674.1A CN201910838674A CN110781106A CN 110781106 A CN110781106 A CN 110781106A CN 201910838674 A CN201910838674 A CN 201910838674A CN 110781106 A CN110781106 A CN 110781106A
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- flash memory
- universal flash
- digital circuit
- circuit module
- physical layer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1684—Details of memory controller using multiple buses
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
Abstract
The invention discloses a universal flash memory host end chip device and equipment. The device comprises a digital circuit module for analyzing the protocol of the universal flash memory and at least two universal flash memory physical layer modules for processing high-speed signals, wherein the number of the at least two universal flash memory physical layer modules is n, so that the highest supported capacity is the sum of the capacities of 1 × n universal flash memory UFS slave devices or 2 × n universal flash memory UFS slave devices, the highest achievable performance is the parallel read-write performance of 2-path interfaces, the highest supported capacity can be improved, and the read-write performance is improved.
Description
Technical Field
The present invention relates to the field of storage technologies, and in particular, to a host-side chip device and an apparatus for a universal flash memory.
Background
The UFS (Universal Flash Storage) host chip device refers to all chips capable of reading and writing a Universal Flash Storage, and includes an interface conversion chip for converting a UFS interface into another interface, such as a UFS card reader.
The conventional UFS host chip device generally includes a digital circuit module responsible for UFS protocol parsing and an analog circuit module responsible for high-speed signal processing, i.e., a UFS physical layer (PHY) module. The two MODULEs of the digital circuit MODULE and the UFS physical layer analog circuit MODULE are connected through RMMI (Reference M-PHY MODULE Interface), and the UFS physical layer analog circuit MODULE provides a high-speed differential signal Interface for connecting to a UFS memory.
Both UFS hosts and UFS slaves defined by the existing UFS standard specification can support 1-way or 2-way UFS communication interfaces, so that one UFS host can connect to at most 2 UFS slaves supporting 1-way interfaces, and the highest supported capacity is the total capacity of 2 UFS slaves. In order to achieve the highest performance, one UFS host may be connected to one UFS slave device supporting a 2-way interface, where the highest performance is the parallel read-write performance of the 2-way interface.
However, the inventors found that at least the following problems exist in the prior art:
the existing universal flash memory UFS host end chip device only supports and connects one or two universal flash memories, and the supported highest capacity is limited.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a host-side chip device and an apparatus for a universal flash memory, which can improve the supported maximum capacity and improve the read/write performance.
According to one aspect of the invention, a universal flash memory host side chip device is provided, which comprises a digital circuit module for universal flash memory protocol parsing and at least two universal flash memory physical layer modules for processing high-speed signals.
The digital circuit module is connected with the at least two universal flash memory physical layer modules in series.
The host chip device of the universal flash memory further comprises:
a multiplexer;
the reference M-PHY module interfaces of the at least two universal flash memory physical layer modules are connected to the reference M-PHY module interface of the digital circuit module after passing through the multiplexer.
The chip device at the host end of the universal flash memory further comprises at least one digital circuit module used for protocol analysis of the universal flash memory, the at least one digital circuit module and the digital circuit module are the same circuit module, the sum of the at least one digital circuit module and the digital circuit module is the same as the number of the at least two physical layer modules of the universal flash memory, the at least one digital circuit module is connected with the at least two physical layer modules of the universal flash memory in a one-to-one mode, and the digital circuit module is connected with the at least two physical layer modules of the universal flash memory in a one-to-one mode.
The at least one digital circuit module is connected with the at least two universal flash memory physical layer modules in a one-to-one parallel connection mode, and the digital circuit module is connected with the at least two universal flash memory physical layer modules in a one-to-one parallel connection mode.
The universal flash memory host end chip device also comprises at least one digital circuit module for analyzing the universal flash memory protocol, wherein at least one digital circuit module is provided with at least one universal flash memory physical layer module which is connected through a multiplexer, and at least one universal flash memory physical layer module is connected through a multiplexer.
The digital circuit module is connected with at least one universal flash memory physical layer module in a mixed connection mode of combining parallel connection and series connection, and the digital circuit module is connected with at least one universal flash memory physical layer module in a mixed connection mode of combining parallel connection and series connection.
The number of the universal flash memory physical layer modules connected with the digital circuit module is the same as that of the universal flash memory physical layer modules connected with each digital circuit module in the at least one digital circuit module.
According to another aspect of the present invention, there is provided a universal flash memory host-side chip device, comprising the universal flash memory host-side chip apparatus as described in any one of the above.
It can be found that, in the above solution, the host-side chip device of the universal flash memory may include a digital circuit module for analyzing the protocol of the universal flash memory and at least two physical layer modules of the universal flash memory for processing high-speed signals, and assuming that the number of the at least two physical layer modules of the universal flash memory is n, the highest supported capacity is the sum of the capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, and the highest achievable performance is the parallel read-write performance of the 2-way interface, which can achieve the highest supported capacity.
Furthermore, in the above solution, the host-side chip device of the universal flash memory may further include at least one digital circuit module for protocol resolution of the universal flash memory, the at least one digital circuit module is the same circuit module as the one digital circuit module, the sum of the at least one digital circuit module and the one digital circuit module is the same as the number of the at least two universal flash memory physical layer modules, the digital circuit module is connected with the universal flash memory physical layer module in a one-to-one way, and the number of the at least two universal flash memory physical layer modules is assumed to be n, the highest performance that can be achieved in this way is the parallel read-write performance of the 2 × n interfaces, and the highest supported capacity is the sum of the capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, so that the highest supported capacity can be improved, and the read-write performance is improved at the same time.
Further, in the above solution, the host-side chip device of the universal flash memory may further include at least one digital circuit module for analyzing the protocol of the universal flash memory, where each of the at least one digital circuit module has at least one physical layer module of the universal flash memory connected via a multiplexer, and each of the at least one physical layer module of the universal flash memory connected via a multiplexer, and assuming that n digital circuit modules are provided in the host-side chip device of the universal flash memory, each of the at least one digital circuit module has m physical layer modules of UFS connected via a multiplexer, so that the highest performance that can be achieved is that 2 × n interfaces are parallel, and the highest capacity that can be supported is the sum of capacities of 1 × m n slave devices of UFS or 2 × m slave devices of UFS, and the highest capacity that can be supported can be improved, and simultaneously, the read-write performance is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a host-side chip device of a universal flash memory according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of another embodiment of a host-side chip device of a universal flash memory according to the present invention;
FIG. 3 is a block diagram of a host-side chip device of a universal flash memory according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
The invention provides a chip device at a host end of a universal flash memory, which can improve the highest supported capacity.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a host-side chip device of a universal flash memory according to an embodiment of the invention. In this embodiment, the host-side chip device 10 of the universal flash memory includes a digital circuit module 11 for protocol parsing of the universal flash memory and at least two physical layer modules 12 of the universal flash memory for processing high-speed signals.
Optionally, the digital circuit module 11 is connected in series with the at least two universal flash memory physical layer modules 12.
Optionally, the universal flash memory host-side chip apparatus 10 may further include:
a multiplexer (not shown);
the reference M-PHY module interfaces of the at least two universal flash memory physical layer modules 12 are connected to the reference M-PHY module interfaces of the digital circuit modules after passing through the multiplexer.
In this embodiment, in order to increase the supported maximum capacity, the host-side chip device 10 of the universal flash memory may adopt a serial connection manner, the host-side chip device 10 of the universal flash memory needs to be designed accordingly, and the host-side chip device 10 of the universal flash memory may include a digital circuit module 11 responsible for UFS protocol parsing and a plurality of physical layer modules 12 of the universal flash memory responsible for high-speed signal processing. The RMMI interfaces of the plurality of flash memory phy blocks 12 responsible for high-speed signal processing may be connected to the RMMI interface of the digital circuit block 11 after passing through the multiplexer. Because the RMMI is a digital signal interface and is much lower in frequency than the high-speed differential signal, the multiplexer is relatively easy to implement. It is assumed that the number of the at least two general flash memory physical layer modules 12 is n, so that the highest supported capacity is the sum of the capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, and the highest achievable performance is the read-write performance of the 2-channel interface parallel, which can improve the supported maximum capacity and improve the read-write performance.
It can be found that, in this embodiment, the host-side chip device of the universal flash memory may include a digital circuit module for analyzing the protocol of the universal flash memory and at least two physical layer modules of the universal flash memory for processing high-speed signals, and it is assumed that the number of the at least two physical layer modules of the universal flash memory is n, so that the highest supported capacity is the sum of the capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, and the highest achievable performance is the parallel read-write performance of the 2-way interface, which can achieve the highest supported capacity and improve the read-write performance at the same time.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a host chip device of a universal flash memory according to the present invention. Different from the previous embodiment, the host-side chip device 20 of the universal flash memory according to this embodiment further includes at least one digital circuit module 21 for analyzing the protocol of the universal flash memory, the at least one digital circuit module 21 and the one digital circuit module 11 are the same circuit modules, the sum of the at least one digital circuit module 21 and the one digital circuit module 11 is equal to the number of the at least two physical layer modules 12 of the universal flash memory, the at least one digital circuit module 21 and the at least two physical layer modules 12 of the universal flash memory are connected in a one-to-one manner, and the one digital circuit module 11 and the at least two physical layer modules 12 of the universal flash memory are connected in a one-to-one manner.
Optionally, the at least one digital circuit module 21 is connected in parallel with the at least two universal flash memory physical layer modules 12 in a one-to-one manner, and the one digital circuit module 11 is connected in parallel with the at least two universal flash memory physical layer modules 12 in a one-to-one manner.
In this embodiment, in order to increase the supported maximum capacity, the host-side chip device 20 of the universal flash memory may be connected in parallel, the at least one digital circuit module 21 and the one digital circuit module 11 are the same circuit modules, the sum of the at least one digital circuit module 21 and the one digital circuit module 11 is equal to the number of the at least two physical layer modules 12 of the universal flash memory, the at least one digital circuit module 21 and the at least two physical layer modules 12 of the universal flash memory are connected in a one-to-one manner, the one digital circuit module 11 and the at least two physical layer modules 12 of the universal flash memory are connected in a one-to-one manner, assuming that the number of the at least two physical layer modules 12 of the universal flash memory is n, the highest performance that can be achieved is the read-write performance of parallel 2 n interfaces, the supported maximum capacity is the sum of 1 n UFS slave devices or 2 n s slave devices, the highest capacity supported can be improved, and the read-write performance is improved.
It can be found that, in this embodiment, the universal flash memory host-side chip device may further include at least one digital circuit module for universal flash memory protocol parsing, where the at least one digital circuit module is the same circuit module as the digital circuit module, the sum of the at least one digital circuit module and the one digital circuit module is the same as the number of the at least two universal flash memory physical layer modules, the at least one digital circuit module is connected to the at least two universal flash memory physical layer modules in a one-to-one manner, the one digital circuit module is connected to the at least two universal flash memory physical layer modules in a one-to-one manner, and assuming that the number of the at least two universal flash memory physical layer modules is n, the highest performance that can be achieved is the parallel read-write performance of 2 × n interfaces, the highest supported capacity is the sum of 1 × n UFS slave devices or 2 × n UFS slave devices, the highest capacity supported can be improved, and the read-write performance is improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a host chip device of a universal flash memory according to another embodiment of the invention. Different from the corresponding embodiment of fig. 1, the host-side chip device 30 of the flash memory according to this embodiment further includes at least one digital circuit module 31 for protocol resolution of the flash memory, where each of the at least one digital circuit module 31 has at least one physical layer module 12 of the flash memory connected through a multiplexer, and each of the at least one digital circuit module 11 has at least one physical layer module 12 of the flash memory connected through a multiplexer.
Optionally, the digital circuit module 11 is connected to the at least one universal flash memory physical layer module 12 in a hybrid connection manner of parallel connection and series connection, and the at least one digital circuit module 31 is connected to the at least one universal flash memory physical layer module 12 in a hybrid connection manner of parallel connection and series connection.
Optionally, the number of the universal flash memory physical layer modules 12 connected to the one digital circuit module 11 is equal to the number of the universal flash memory physical layer modules 12 connected to each of the at least one digital circuit modules 31.
In this embodiment, in order to increase the maximum supported capacity, the usb host-side chip device 30 may further include at least one digital circuit module 31 for parsing the usb, where each of the at least one digital circuit module 31 has at least one usb physical layer module 12 connected via a multiplexer, and each of the at least one digital circuit module 11 has at least one usb physical layer module 12 connected via a multiplexer, and assuming that there are n digital circuit modules in the usb host-side chip device 30, each of the n digital circuit modules has m UFS physical layer modules connected via a multiplexer, so that the maximum supported capacity is the sum of capacities of 2 × n slave devices and 1 × m UFS slave devices, the highest capacity supported can be improved, and the read-write performance is improved.
It can be found that, in this embodiment, the host-side chip device of the universal flash memory may further include at least one digital circuit module for analyzing the protocol of the universal flash memory, each of the at least one digital circuit module has at least one physical layer module of the universal flash memory connected through a multiplexer, each of the at least one physical layer module of the universal flash memory is connected through a multiplexer, assuming that there are n digital circuit modules in the host-side chip device of the universal flash memory, each of the n digital circuit modules has m physical layer modules of the UFS connected through a multiplexer, so that the highest performance that can be achieved is the sum of 2 × n interfaces in parallel, and the highest capacity that can be supported is the sum of the capacities of 1 × m UFS slave devices or 2 × m UFS slave devices, the highest capacity supported can be improved, and the read-write performance is improved.
The invention further provides a universal flash memory host-side chip device, which includes a universal flash memory host-side chip device, where the universal flash memory host-side chip device is the universal flash memory host-side chip device in the above embodiment, and each function module of the universal flash memory host-side chip device can respectively execute the function, connection relationship, and the like of each function module of the corresponding universal flash memory host-side chip device in the above embodiment, so that the function modules of the universal flash memory host-side chip device are not described herein again, and please refer to the corresponding description above in detail.
It can be found that, in the above scheme, the host-side chip device of the universal flash memory may include a digital circuit module for analyzing a protocol of the universal flash memory and at least two physical layer modules of the universal flash memory for processing a high-speed signal, and it is assumed that the number of the at least two physical layer modules of the universal flash memory is n, so that the highest supported capacity is the sum of capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, and the highest achievable performance is parallel read-write performance of 2-way interfaces, which can improve the highest supported capacity and improve the read-write performance at the same time.
Further, in the above solution, the host-side chip device of the universal flash memory may further include at least one digital circuit module for protocol resolution of the universal flash memory, the at least one digital circuit module and the digital circuit module are the same circuit module, the sum of the at least one digital circuit module and the digital circuit module is the same as the number of the at least two physical layer modules of the universal flash memory, the at least one digital circuit module and the at least two physical layer modules of the universal flash memory are connected in a one-to-one manner, the digital circuit module and the at least two physical layer modules of the universal flash memory are connected in a one-to-one manner, assuming that the number of the at least two physical layer modules of the universal flash memory is n, the highest performance that can be achieved is the parallel read-write performance of 2 × n interfaces, and the highest supported capacity is the sum of the capacities of 1 × n UFS slave devices or 2 × n UFS slave devices, the highest capacity supported can be improved, and the read-write performance is improved.
Further, in the above solution, the host-side chip device of the universal flash memory may further include at least one digital circuit module for analyzing the protocol of the universal flash memory, where each of the at least one digital circuit module has at least one physical layer module of the universal flash memory connected via a multiplexer, and each of the at least one physical layer module of the universal flash memory connected via a multiplexer, and assuming that n digital circuit modules are provided in the host-side chip device of the universal flash memory, each of the at least one digital circuit module has m physical layer modules of UFS connected via a multiplexer, so that the highest performance that can be achieved is that 2 × n interfaces are parallel, and the highest capacity that can be supported is the sum of capacities of 1 × m n slave devices of UFS or 2 × m slave devices of UFS, and the highest capacity that can be supported can be improved, and simultaneously, the read-write performance is improved.
In the several embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a module or a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be substantially or partially implemented in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, a network device, or the like) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only a part of the embodiments of the present invention, and not intended to limit the scope of the present invention, and all equivalent devices or equivalent processes performed by the present invention through the contents of the specification and the drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (9)
1. A chip device at host end of universal flash memory is featured as using digital circuit module for analyzing protocol of universal flash memory and using at least two physical layer modules of universal flash memory to process high-speed signal.
2. The universal flash memory host-side chip apparatus of claim 1 wherein said digital circuit module is connected in series with said at least two universal flash memory physical layer modules.
3. The universal flash memory host-side chip apparatus according to claim 1, wherein the universal flash memory host-side chip apparatus further comprises:
a multiplexer;
the reference M-PHY module interfaces of the at least two universal flash memory physical layer modules are connected to the reference M-PHY module interface of the digital circuit module after passing through the multiplexer.
4. The universal flash memory host-side chip apparatus according to claim 1, wherein the universal flash memory host-side chip apparatus further comprises at least one digital circuit module for universal flash memory protocol resolution, the at least one digital circuit module is the same circuit module as the one digital circuit module, the sum of the at least one digital circuit module and the one digital circuit module is the same as the number of the at least two universal flash memory physical layer modules, the at least one digital circuit module is connected to the at least two universal flash memory physical layer modules in a one-to-one manner, and the one digital circuit module is connected to the at least two universal flash memory physical layer modules in a one-to-one manner.
5. The universal flash memory host side chip apparatus of claim 4 wherein said at least one digital circuit module is connected in one-to-one parallel with said at least two universal flash memory physical layer modules, and wherein said one digital circuit module is connected in one-to-one parallel with said at least two universal flash memory physical layer modules.
6. The universal flash memory host-side chip apparatus according to claim 1, wherein the universal flash memory host-side chip apparatus further comprises at least one digital circuit module for universal flash memory protocol parsing, wherein each of the at least one digital circuit modules has at least one universal flash memory physical layer module connected via a multiplexer, and wherein each of the at least one digital circuit modules has at least one universal flash memory physical layer module connected via a multiplexer.
7. The universal flash memory host-side chip apparatus of claim 6 wherein the digital circuit module is connected to the at least one universal flash memory physical layer module in a hybrid combination of parallel and serial connections, and wherein the at least one digital circuit module is connected to the at least one universal flash memory physical layer module in a hybrid combination of parallel and serial connections.
8. The universal flash memory host side chip apparatus of claim 6 wherein the number of universal flash memory physical layer modules connected to said one digital circuit module is the same as the number of universal flash memory physical layer modules connected to each of said at least one digital circuit module.
9. A universal flash memory host-side chip apparatus comprising the universal flash memory host-side chip device according to any one of claims 1 to 8.
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Address after: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant after: Shenzhen deminli Technology Co.,Ltd. Address before: 518000 Intelligence Valley Innovation Park 701, 707, No. 1010 Bulong Road, Xinniu Community, Minzhi Street, Longhua District, Shenzhen City, Guangdong Province Applicant before: SHENZHEN DEMINGLI ELECTRONICS Co.,Ltd. |
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Address after: 2501, 2401, block a, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen, Guangdong 518000 Applicant after: Shenzhen deminli Technology Co.,Ltd. Address before: 701, 707, wisdom Valley Innovation Park, 1010 Bulong Road, Xinniu community, Minzhi street, Longhua District, Shenzhen, Guangdong 518000 Applicant before: Shenzhen deminli Technology Co.,Ltd. |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200211 |