CN209168746U - A kind of Common Flash Memory test macro based on FPGA - Google Patents
A kind of Common Flash Memory test macro based on FPGA Download PDFInfo
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- CN209168746U CN209168746U CN201822087549.5U CN201822087549U CN209168746U CN 209168746 U CN209168746 U CN 209168746U CN 201822087549 U CN201822087549 U CN 201822087549U CN 209168746 U CN209168746 U CN 209168746U
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Abstract
The Common Flash Memory test macro based on FPGA that the utility model discloses a kind of, including UFS main controller, UniPro and M-PHY, it is characterized in that, the UFS main controller, UniPro and M-PHY are sequentially connected and connect, a Common Flash Memory test cell is collectively formed and is mounted on FPGA core core, each M-PHY is correspondingly connected with a Common Flash Memory to be measured；The Common Flash Memory test cell tests corresponding Common Flash Memory to be measured under the driving of FPGA.The situation that technical solutions of the utility model are few for current Common Flash Memory (UFS) test equipment, method follows the beaten track, testing efficiency is low, multiple Common Flash Memory test cells are managed by FPGA, multiple Common Flash Memories (DUT) to be measured can be tested simultaneously, be tested without Common Flash Memory test cell chip is separately encapsulated for DUT.
Description
Technical field
The utility model belongs to the testing field of Common Flash Memory (UFS), and in particular to a kind of Common Flash Memory based on FPGA
Test macro.
Background technique
UFS (Universal Flash Storage Common Flash Memory), is by Joint Electronic Device Engineering Council
(JEDEC) flash memory system for high data transmission bauds and low-power consumption that standard defines.Unified Protocol (Tong ー
Agreement), be it is a kind of for using high speed serialization link chip to chip (chip-to-chip) application.UniPro is defined
For puppy parc, which solves the problems, such as such as error handle, flow control, routing or the general interconnection of arbitration.UniPro branch
M-PHY link is held, M-PHY provides two kinds of transmission mode, that is, low speed and high speed, and each pattern supports multi-speed transmission
(multiplespeed gears), and M-PHY also supports a variety of power down modes: STALL, is used for high-speed mode；SLEEP is used
In low-speed mode；And HIBERN8.STALL and SLEEP is optimized for fast wake-up in their corresponding transmission modes, and
HIBERN8 is the extremely low power mode with longer wakeup time.M-PHY is different from other existing height used in interconnection line
The PHY (physical layer) of speed, clock-embedded, for example, commonly known as PHY those of defined in the standard of PCIe, because of M-PHY
It is optimized for low-power.Although PCIe also has power down mode, they only have a You ー kind transmission mode, this and M-PHY
On the contrary, M-PHY has high speed (and higher-wattage) transmission mode and low speed (and lower-wattage) transmission mode.This controls M-PHY
Make it is more complex, since it is desired that management support two kinds of transmission modes needed for institute it is stateful.
UFS is joined using MIPI (Mobile Industry Processor Interface mobile industrial processor interface)
The M-PHY physical layer of alliance's exploitation, possesses the speed of the every thread of 2.9Gbps to the every thread of 5.8Gbps.UFS realizes one complete pair
The LVDS serial ports of work possesses broader bandwidth for the eMMC compared with 8 parallel threads.It is not both simultaneously that it is maximum, which to compare eMMC, by UFS
Row signal has been changed to more advanced serial signal, so as to improve frequency rapidly；Half-duplex simultaneously is changed to full duplex；UFS
Based on SCSI (Small Computer System Interface small computer system interface) structural model and support
SCSI mark instructions sequence；Linux kernel has supported UFS format.
The specification obtains the support of several consumer electrical product market leaders, including Nokia, Sony's mobile communication,
Texas Instrument, STMicw Electronics, Samsung, Micron Technology, SK Hynix etc..UFS is contained used in existing mobile terminal device
EMMC (Embedded Multimedia Card embedded multi-media card), Tiny SSD (Tiny Solid-State Drive
Miniaturized solid-state hard disk) the advantages of, UFS is very suitable to the mobile terminal for requiring high performance demands to combine with low-power consumption demand (such as
Mobile phone, portable computer, handheld device, tablet computer etc.) it applies, UFS is considered the substituent of eMMC and SD card.
UFS test equipment currently on the market is seldom, and test method is mostly based on ASIC (Application-specific
Integrated circuit specific integrated circuit), cardinal principle is, according to demand by Common Flash Memory (Device to be measured
Under Test, measured device DUT) test circuit (including software) be packaged into chip, driving chip tests DUT.
Its shortcoming is that the limited expansibility of this test form, the DUT limited amount tested every time, test it is inefficient.
Utility model content
Aiming at the above defects or improvement requirements of the prior art, the utility model provides a kind of general sudden strain of a muscle based on FPGA
Test macro is deposited, at least can partially be solved the above problems.Technical solutions of the utility model are directed to current Common Flash Memory
(UFS) situation that test equipment is few, method follows the beaten track, testing efficiency is low, by FPGA to multiple Common Flash Memory test cells
It is managed, multiple Common Flash Memories (DUT) to be measured can be tested simultaneously, separately encapsulate Common Flash Memory without for DUT
Test cell chip is tested.
To achieve the above object, according to the one aspect of the utility model, a kind of Common Flash Memory based on FPGA is provided
Test macro, including UFS main controller, UniPro, M-PHY and FPGA, which is characterized in that the UFS main controller, UniPro and
M-PHY, which is sequentially connected, to be connect, and a Common Flash Memory test cell is collectively formed and is arranged in FPGA, and the M-PHY leads to be measured
It is correspondingly connected with flash memory；The FPGA carries out programming in logic to Common Flash Memory test cell, and then drives UFS main controller to corresponding
Common Flash Memory to be measured be tested for the property.
One as technical solutions of the utility model is preferred, includes two M-PHY in Common Flash Memory test cell, each
M-PHY correspondence is connected with a Common Flash Memory to be measured.
One as technical solutions of the utility model is preferred, and physical switch, FPGA are provided on M-PHY external circuit
It controls physical switch realization according to link state to be turned on or off, to complete the test of Common Flash Memory to be measured.
One as technical solutions of the utility model is preferred, and it is single that 1~4 Common Flash Memory test is provided in each FPGA
Member.
One as technical solutions of the utility model is preferred, and 2 Common Flash Memory test cells are provided in each FPGA.
One as technical solutions of the utility model is preferred, preferably passes through aging between M-PHY and Common Flash Memory to be measured
Interface board connector is connected.
One as technical solutions of the utility model is preferred, and FPGA core core and the Common Flash Memory to be measured preferably use
The integrated arrangement of the mode of positive and negative installation, to carry out integrated test to multiple Common Flash Memories to be measured.
One as technical solutions of the utility model is preferred, and FPGA core core is preferably sequentially arranged according to array format,
At least one Common Flash Memory test cell is provided on each FPGA core core, for be measured to being correspondingly arranged on the veneer
Common Flash Memory is tested.
One as technical solutions of the utility model is preferred, and there are many layer protocols for setting in M-PHY, for realizing difference
Information transmitting between data Layer.
In general, have the above technical solutions conceived by the present invention are compared with the prior art, with following
Beneficial effect:
1) the Common Flash Memory test cell of UFS is arranged on FPGA core core, passes through by technical solutions of the utility model
FPGA driving Common Flash Memory test cell tests DUT, and each Common Flash Memory test cell need not be especially arranged (without spy
Not Feng Zhuan) corresponding DUT can be tested, FPGA can at any time be adjusted test content, preferably be tested
Effect.
2) technical solutions of the utility model, due to using FPGA drive form, with good scalability, each
It can integrate at least one Common Flash Memory test cell on FPGA, each Common Flash Memory test cell can carry out two DUT
Test, under the unified driving of FPGA, can test multiple DUT while improving scalability, improve the survey of DUT
Try efficiency.
Detailed description of the invention
Fig. 1 is the frame signal of the Common Flash Memory test macro in the embodiment of technical solutions of the utility model based on FPGA
Figure；
Fig. 2 is the block schematic illustration of UFS main controller module in the embodiment of technical solutions of the utility model；
Fig. 3 is the block schematic illustration of UniPro module in the embodiment of technical solutions of the utility model.
Specific embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only used to explain
The utility model is not used to limit the utility model.In addition, institute in the various embodiments of the present invention described below
The technical characteristic being related to can be combined with each other as long as they do not conflict with each other.With reference to embodiment to this
Utility model is further described.
It is the Common Flash Memory test system framework schematic diagram of technical solutions of the utility model embodiment as shown in Figure 1, wherein
Test cell FPGA core core (FPGA Core Board) and DUT (UFS Device) are preferably positioned at same in this programme
On veneer, by the way of positive and negative installation, UFS master controller, UniPro, M-PHY are realized inside FPGA, and each UFS connects
Mouth preferably up to supports 2 Lane, each FPGA preferably to support 1~4 UFS, is 2 in the present embodiment.In the present embodiment, often
The veneer seen has pcb board etc., as the primary structure of carrying FPGA core core and Common Flash Memory test cell, has convenient for upper
State device installing and dismounting the advantages that.
Meanwhile the Common Flash Memory test cell of the compositions such as UFS master controller, UniPro and M-PHY is driven using FPGA, this
It allows for that Common Flash Memory test cell need not be packaged, does not also need to provide additional driving source, it is whole with stronger
Scalability.Since FPGA is programmable, so that additional encapsulation need not be carried out to Common Flash Memory test cell, can be directed to
Different demands are adjusted the test process of Common Flash Memory test cell.
As shown in Figure 1, FPGA core core is mounted on veneer in the present embodiment, be provided in FPGA UFS main controller,
The structures such as UniPro and M-PHY, specifically, above-mentioned UFS main controller, UniPro and M-PHY are sequentially connected with, on each UniPro
It can connect more than one M-PHY, in the present embodiment, be connected using a UFS main controller with a UniPro, so
The corresponding test form being connected with two M-PHY of each UniPro afterwards.That is, a Common Flash Memory is surveyed in this implementation
Examination unit is preferably provided with two M-PHY, the i.e. test assignment that a Common Flash Memory test cell undertakes two Common Flash Memories to be measured.
Further, in this embodiment each M-PHY is by BIB Connector (Burn-in Interface
Board connector, aging Interface board connector) be connected with corresponding DUT, each M-PHY is connect by aging
Oralia connector is correspondingly connected with a DUT.
In the present embodiment, it is additionally provided with physical switch on M-PHY external circuit, the physical switch is for realizing to M-PHY
External circuit switches between high-speed mode, low-speed mode and low-power consumption mode, and said external circuit can be further
Common Flash Memory test cell is assisted to complete the performance detection of DUT.And above-mentioned physical switch preferably passes through FPGA and is directly controlled
System.
As the further preferred of the present embodiment, above-mentioned UFS main controller, UniPro and M-PHY are sequentially connected and connect, common shape
At a Common Flash Memory test cell, and it can integrate on each FPGA core core and multiple Common Flash Memory test cells be installed,
A Common Flash Memory test structure is formed, can should be carried out according to demand further based on the Common Flash Memory test structure of FPGA
Extension forms Common Flash Memory hot-wire array.It is as shown in Figure 1 a kind of tool of preferred Common Flash Memory hot-wire array in this implementation
The body form of expression.
UFS memory and its it may include multiple layers with the interface of host to support each group of Common Flash Memory test cell
At standard required for part.Host may include host controller interface defined in JEDEC standard (HCI) and UFS transmission
Agreement (UTP), and the object of UniPro (Unified Protocol uniform protocol) and referred to as M-PHY defined by MIPI alliance
Manage interface.Inside host, UniPro and M-PHY are designed to be communicated by interface or bus, this interface or bus
Referred to as RMMI (refers to M-PHY module interface), which also defines in MIPI standard.
UFS storage system with main-machine communication can also include respective layer, UTP, UniPro and M-PHY.Each M-PHY
Support a certain amount of position or pin, i.e., as unit of Lane.It is realized according to specific, UFS equipment can support one
Or multiple Lane.Embedded UFS is usually list Lane equipment, but the demand to the embedded UFS equipment of double Lane is supported is more next
It is bigger.UFS cartoon is often moveable equipment, and the storage of single Lane is supported to communicate.
As the further preferred of the present embodiment, in Common Flash Memory test cell, preferred 2.1 Host of UFS of UFS main controller
The preferred MIPI M- of Controller Interface (HCI), UniPro preferred MIPI UniPro version 1.6, M-PHY
PHY version 3.1。
Specifically, the principle framework of UFS main controller employed in the present embodiment is as shown in Fig. 2, including UFS
Master register, UFS control unit interface, UFS transmission protocol layer and system bus interface unit etc..The function of each section is as follows:
1) UFS master register: UFS master register (UFS Host Registers) is used to control the behaviour of host controller
Make, and from host controller reading state and interrupting information.It can be used as memory mapped I/O space (MMIO) realization.
2) UFS control unit interface: the communication between host software and UFS equipment is used direct by UFS Host Controler Interface
Memory access (DMA) Lai Guanli.
3) UFS transmission protocol layer: UFS host sends order, task sum number with UFS protocol information element (UPIU) format
According to.UTP (UFS Transport Protocol, UFS transport protocol) block is responsible for the order of UPIU format construction, task sum number
According to.
4) system bus interface unit: UniPro uses AXI as system bus interface.AXI uses 32 digits from interface
Register read/write operation is carried out according to transmission width.AXI main interface is used for DMA using 32/64 data transfer widths
(Direct Memory Access direct memory access) operation.
One as the present embodiment is specific preferred, and the schematic diagram of UniPro module is as shown in figure 3, including DMA
Register, dma controller, equipment management entity, transport layer, network layer, data link layer, physical adapter layer etc., Mei Gemo
The concrete function of block is as follows:
1) DMA register: DMA register is used to control the operation of dma controller, and reading state and interrupting information, this
It is to be realized as the space MMIO (Memory Mapped IO memory mapping IO).
2) dma controller: dma controller is a kind of powerful direct memory access based on scatter-gather, tool
There are three descriptor threads, have programmable burst sizes, provide lower cpu busy percentage.DMA can at 32 or
It works under 64 data-transmission modes.Transmission size in AXI bus can also change accordingly.
DMA is transferred data to or from the data buffer zone in fifo interface and mainframe memory.Host is resided in deposit
Descriptor in reservoir serves as the pointer for being directed toward these buffer areas.DMA support is independent to send and receive operation, and is posted by one group
Storage (referred to as DMA register) control.
3) equipment management entity: equipment management entity is configured and is controlled using UFS interconnection layer (UIC) command register single
Member, as link initialization, electric source modes change, Hibernate (the most deep low power consumpting state for not losing configuration information) entrance/
It exits, endpoint resetting, to be arranged/obtain any attribute all at the local or reciprocity end UniPro be to use UIC command register by software
What device was completed.
4) transport layer: transport layer is the highest protocol layer of unipro covering.Transport layer is supported multiple between endpoint device
It is bi-directionally connected.UniPro guarantees that the data by individually connecting transmission are reached with identical transmission sequence.By individually connecting hair
All data sent communication class-mark (TC0) all having the same.The protocol Data Unit (PDU) of transport layer is known as section.
5) network layer: the purpose of network layer is to allow to route data to destination appropriate in a network environment.Source is set
It is standby to be responsible for providing its address for wanting the target device communicated.
6) data link layer: the function of data link layer includes that flow control mechanism, AFC frame transmission/reception, CRC are raw
At/check, and L2 frame head and trailer information are added in transport layer/network layer section, and is sent by physics orchestration layer；
With L2 frame head and trailer information are deleted from the frame that physics adaptation layer receives, and sent across transport layer/network layer.
7) physical adapter layer: including a) link initialization, power management, suspend mode, the processing of PACP frame to obtain/be arranged this
Any function on ground or reciprocity end；B) with M-PHY (TYPE-I) interface, pass through physical channel transmission/receiving frame；C) symbol is skipped
Number insertion to reduce the protocol payloads bandwidth of transmitter, with compensate rapid fire and it is slow receive between mark space it is public
Difference；D) HS-G3 is supported, for supporting the Lane under 1 Lane and 2 Lane operating modes and 2 Lane operating modes to manage.
As it will be easily appreciated by one skilled in the art that the above is only the preferred embodiment of the utility model only, not
To limit the utility model, any modification made within the spirit and principle of the present invention, equivalent replacement and change
Into etc., it should be included within the scope of protection of this utility model.
Claims (9)
1. a kind of Common Flash Memory test macro based on FPGA, including UFS main controller, UniPro, M-PHY and FPGA, feature
It is, the UFS main controller, UniPro and M-PHY are sequentially connected and connect, and a Common Flash Memory test cell is collectively formed and is arranged
In FPGA, the M-PHY is correspondingly connected with Common Flash Memory to be measured, to realize using FPGA to Common Flash Memory progressive to be measured
It can test.
2. a kind of Common Flash Memory test macro based on FPGA according to claim 1, wherein the Common Flash Memory test
It include two M-PHY in unit, each M-PHY correspondence is connected with a Common Flash Memory to be measured.
3. according to claim 1 or a kind of Common Flash Memory test macro based on FPGA described in 2, wherein outside the M-PHY
Be provided with physical switch on portion's circuit, FPGA controls physical switch realization according to link state and is turned on or off, with complete to
Survey the test of Common Flash Memory.
4. a kind of Common Flash Memory test macro based on FPGA according to claim 1 or 2, wherein set in each FPGA
It is equipped with 1~4 Common Flash Memory test cell.
5. a kind of Common Flash Memory test macro based on FPGA according to claim 1 or 2, wherein set in each FPGA
It is equipped with 2 Common Flash Memory test cells.
6. a kind of Common Flash Memory test macro based on FPGA according to claim 1 or 2, wherein the M-PHY with to
It surveys between Common Flash Memory and is connected by aging Interface board connector.
7. a kind of Common Flash Memory test macro based on FPGA according to claim 1 or 2, wherein the core board of FPGA
Arrangement is integrated by the way of positive and negative installation with the Common Flash Memory to be measured, to carry out concentration survey to multiple Common Flash Memories to be measured
Examination.
8. a kind of Common Flash Memory test macro based on FPGA according to claim 7, wherein FPGA core core is according to battle array
Column form is sequentially arranged, at least one Common Flash Memory test cell is provided on each FPGA core core, for being correspondingly arranged
Common Flash Memory to be measured tested.
9. a kind of Common Flash Memory test macro based on FPGA according to claim 1 or 2, wherein set in the M-PHY
A variety of layer protocols are equipped with, for realizing the information transmitting between different data layer.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411007A (en) * | 2018-12-11 | 2019-03-01 | 武汉精鸿电子技术有限公司 | A kind of Common Flash Memory test macro based on FPGA |
| CN110781106A (en) * | 2019-09-05 | 2020-02-11 | 深圳市德名利电子有限公司 | Universal flash memory host end chip device and equipment |
| CN112667561A (en) * | 2020-12-29 | 2021-04-16 | 成都旋极历通信息技术有限公司 | Implementation mode for realizing UFS array controller in FPGA |
| CN113608936A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Multi-channel interface test system and method |
| CN116543828A (en) * | 2023-07-06 | 2023-08-04 | 成都佰维存储科技有限公司 | UFS protocol testing method and device, readable storage medium and electronic equipment |
-
2018
- 2018-12-11 CN CN201822087549.5U patent/CN209168746U/en not_active Withdrawn - After Issue
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109411007A (en) * | 2018-12-11 | 2019-03-01 | 武汉精鸿电子技术有限公司 | A kind of Common Flash Memory test macro based on FPGA |
| CN109411007B (en) * | 2018-12-11 | 2024-02-20 | 武汉精鸿电子技术有限公司 | Universal flash memory test system based on FPGA |
| CN110781106A (en) * | 2019-09-05 | 2020-02-11 | 深圳市德名利电子有限公司 | Universal flash memory host end chip device and equipment |
| CN112667561A (en) * | 2020-12-29 | 2021-04-16 | 成都旋极历通信息技术有限公司 | Implementation mode for realizing UFS array controller in FPGA |
| CN112667561B (en) * | 2020-12-29 | 2024-05-31 | 成都旋极历通信息技术有限公司 | Method for realizing UFS array controller in FPGA |
| CN113608936A (en) * | 2021-06-25 | 2021-11-05 | 天津津航计算技术研究所 | Multi-channel interface test system and method |
| CN113608936B (en) * | 2021-06-25 | 2024-04-19 | 天津津航计算技术研究所 | Multi-path interface test system and method |
| CN116543828A (en) * | 2023-07-06 | 2023-08-04 | 成都佰维存储科技有限公司 | UFS protocol testing method and device, readable storage medium and electronic equipment |
| CN116543828B (en) * | 2023-07-06 | 2023-09-19 | 成都佰维存储科技有限公司 | UFS protocol testing method and device, readable storage medium and electronic equipment |
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