CN110720126A - 传输数据掩码的方法、内存控制器、内存芯片和计算机系统 - Google Patents
传输数据掩码的方法、内存控制器、内存芯片和计算机系统 Download PDFInfo
- Publication number
- CN110720126A CN110720126A CN201780091809.1A CN201780091809A CN110720126A CN 110720126 A CN110720126 A CN 110720126A CN 201780091809 A CN201780091809 A CN 201780091809A CN 110720126 A CN110720126 A CN 110720126A
- Authority
- CN
- China
- Prior art keywords
- data blocks
- data
- block
- written
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
本申请提供了一种传输数据掩码的方法、内存控制器、内存芯片和计算机系统,该方法包括内存控制器向内存芯片发送第一写命令,该第一写命令中包含有第一指示信息,该第一指示信息用于指示待写入的数据块中具有掩码数据块,该待写入的数据块的个数为N,N为大于或等于2的整数;该内存控制器根据该第一写命令向该内存芯片发送N个数据块,其中,该N个数据块中的一个数据块为第一DM信息块,该第一DM信息块用于指示该待写入的数据块中的掩码数据块的位置,该N个数据块包括该待写入的数据块中的非掩码数据块。本申请实施例实现了在不增加管脚的情况DM的传输。
Description
PCT国内申请,说明书已公开。
Claims (25)
- PCT国内申请,权利要求书已公开。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2017/091331 WO2019000456A1 (zh) | 2017-06-30 | 2017-06-30 | 传输数据掩码的方法、内存控制器、内存芯片和计算机系统 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN110720126A true CN110720126A (zh) | 2020-01-21 |
CN110720126B CN110720126B (zh) | 2021-08-13 |
Family
ID=64742791
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201780091809.1A Active CN110720126B (zh) | 2017-06-30 | 2017-06-30 | 传输数据掩码的方法、内存控制器、内存芯片和计算机系统 |
Country Status (2)
Country | Link |
---|---|
CN (1) | CN110720126B (zh) |
WO (1) | WO2019000456A1 (zh) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112115077A (zh) * | 2020-08-31 | 2020-12-22 | 瑞芯微电子股份有限公司 | 一种dram内存驱动优化方法和装置 |
CN116844624A (zh) * | 2022-03-25 | 2023-10-03 | 长鑫存储技术有限公司 | 一种控制方法、半导体存储器和电子设备 |
CN116844624B (zh) * | 2022-03-25 | 2024-06-07 | 长鑫存储技术有限公司 | 一种控制方法、半导体存储器和电子设备 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2023115319A1 (zh) * | 2021-12-21 | 2023-06-29 | 华为技术有限公司 | 一种数据存储方法、存储装置及设备 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010042143A1 (en) * | 2000-05-12 | 2001-11-15 | Fujitsu Limited | Memory access system in which processor generates operation request, and memory interface accesses memory, and performs operation on data |
US20020172065A1 (en) * | 2001-05-18 | 2002-11-21 | Yuichi Uzawa | Associative memory apparatus and routing apparatus |
US20050055491A1 (en) * | 2002-02-08 | 2005-03-10 | Joseph Macri | Method and apparatus for data inversion in memory device |
CN1653434A (zh) * | 2002-03-22 | 2005-08-10 | 英特尔公司 | 获得数据掩码映射信息 |
US20060132822A1 (en) * | 2004-05-27 | 2006-06-22 | Silverbrook Research Pty Ltd | Storage of program code in arbitrary locations in memory |
CN102543162A (zh) * | 2004-11-29 | 2012-07-04 | 拉姆伯斯公司 | 微线程存储器 |
US20120173810A1 (en) * | 1997-10-10 | 2012-07-05 | Barth Richard M | Method and Apparatus for Indicating Mask Information |
CN103902469A (zh) * | 2012-12-25 | 2014-07-02 | 华为技术有限公司 | 一种数据预取的方法和系统 |
CN104094238A (zh) * | 2011-11-18 | 2014-10-08 | 美光科技公司 | 用于存储有效性掩码及操作设备的设备及方法 |
CN106354656A (zh) * | 2015-07-13 | 2017-01-25 | 三星电子株式会社 | 用于存储管理的方法和系统 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9262326B2 (en) * | 2006-08-14 | 2016-02-16 | Qualcomm Incorporated | Method and apparatus to enable the cooperative signaling of a shared bus interrupt in a multi-rank memory subsystem |
US7921263B2 (en) * | 2006-12-22 | 2011-04-05 | Broadcom Corporation | System and method for performing masked store operations in a processor |
US8006033B2 (en) * | 2008-09-09 | 2011-08-23 | Intel Corporation | Systems, methods, and apparatuses for in-band data mask bit transmission |
US9984741B2 (en) * | 2015-11-05 | 2018-05-29 | Dell Products, Lp | System and method of transferring data over available pins |
-
2017
- 2017-06-30 WO PCT/CN2017/091331 patent/WO2019000456A1/zh active Application Filing
- 2017-06-30 CN CN201780091809.1A patent/CN110720126B/zh active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120173810A1 (en) * | 1997-10-10 | 2012-07-05 | Barth Richard M | Method and Apparatus for Indicating Mask Information |
US20010042143A1 (en) * | 2000-05-12 | 2001-11-15 | Fujitsu Limited | Memory access system in which processor generates operation request, and memory interface accesses memory, and performs operation on data |
US20020172065A1 (en) * | 2001-05-18 | 2002-11-21 | Yuichi Uzawa | Associative memory apparatus and routing apparatus |
US20050055491A1 (en) * | 2002-02-08 | 2005-03-10 | Joseph Macri | Method and apparatus for data inversion in memory device |
CN1653434A (zh) * | 2002-03-22 | 2005-08-10 | 英特尔公司 | 获得数据掩码映射信息 |
US20060132822A1 (en) * | 2004-05-27 | 2006-06-22 | Silverbrook Research Pty Ltd | Storage of program code in arbitrary locations in memory |
CN102543162A (zh) * | 2004-11-29 | 2012-07-04 | 拉姆伯斯公司 | 微线程存储器 |
CN104094238A (zh) * | 2011-11-18 | 2014-10-08 | 美光科技公司 | 用于存储有效性掩码及操作设备的设备及方法 |
CN103902469A (zh) * | 2012-12-25 | 2014-07-02 | 华为技术有限公司 | 一种数据预取的方法和系统 |
CN106354656A (zh) * | 2015-07-13 | 2017-01-25 | 三星电子株式会社 | 用于存储管理的方法和系统 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112115077A (zh) * | 2020-08-31 | 2020-12-22 | 瑞芯微电子股份有限公司 | 一种dram内存驱动优化方法和装置 |
CN112115077B (zh) * | 2020-08-31 | 2022-04-19 | 瑞芯微电子股份有限公司 | 一种dram内存驱动优化方法和装置 |
CN116844624A (zh) * | 2022-03-25 | 2023-10-03 | 长鑫存储技术有限公司 | 一种控制方法、半导体存储器和电子设备 |
CN116844624B (zh) * | 2022-03-25 | 2024-06-07 | 长鑫存储技术有限公司 | 一种控制方法、半导体存储器和电子设备 |
Also Published As
Publication number | Publication date |
---|---|
WO2019000456A1 (zh) | 2019-01-03 |
CN110720126B (zh) | 2021-08-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10824499B2 (en) | Memory system architectures using a separate system control path or channel for processing error information | |
EP3704591B1 (en) | Write credits management for non-volatile memory | |
US8677211B2 (en) | Data bus inversion using spare error correction bits | |
US10120590B2 (en) | Method for providing read data flow control or error reporting using a read data strobe | |
TW200935233A (en) | System and method for data read of a synchronous serial interface NAND | |
US10866736B2 (en) | Memory controller and data processing circuit with improved system efficiency | |
CN105373345B (zh) | 存储器设备和模块 | |
US10089250B2 (en) | State change in systems having devices coupled in a chained configuration | |
US20190205047A1 (en) | Memory addressing methods and associated controller, memory device and host | |
JP2008009817A (ja) | 半導体装置及びデータ転送方法 | |
CN110720126B (zh) | 传输数据掩码的方法、内存控制器、内存芯片和计算机系统 | |
US20180018104A1 (en) | Dynamic write latency for memory controller using data pattern extraction | |
TWI512475B (zh) | 有助於在記憶體模組和中央處理器之間進行通信的方法及相關機器可讀儲存媒體 | |
CN108139993B (zh) | 内存装置、内存控制器、数据缓存装置及计算机系统 | |
CN112513824A (zh) | 一种内存交织方法及装置 | |
JP2021520555A (ja) | 階層デコーダを使用したエラー訂正 | |
CN106940684B (zh) | 一种按比特写数据的方法及装置 | |
EP3610379B1 (en) | Transaction identification | |
US20190042364A1 (en) | Technologies for maintaining data integrity during data transmissions | |
US8006029B2 (en) | DDR flash implementation with direct register access to legacy flash functions | |
US20200348999A1 (en) | Transaction metadata | |
US20180276068A1 (en) | Error correction code in memory | |
US11119676B2 (en) | Using spare bits in memory systems | |
US11983443B2 (en) | Multi-access memory modules | |
CN114153402B (zh) | 存储器及其数据读写方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |