WO2023115319A1 - 一种数据存储方法、存储装置及设备 - Google Patents

一种数据存储方法、存储装置及设备 Download PDF

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Publication number
WO2023115319A1
WO2023115319A1 PCT/CN2021/140009 CN2021140009W WO2023115319A1 WO 2023115319 A1 WO2023115319 A1 WO 2023115319A1 CN 2021140009 W CN2021140009 W CN 2021140009W WO 2023115319 A1 WO2023115319 A1 WO 2023115319A1
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data
memory
memory controller
burst length
burst
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PCT/CN2021/140009
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English (en)
French (fr)
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梁传增
郭冬玉
刘振军
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华为技术有限公司
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Priority to PCT/CN2021/140009 priority Critical patent/WO2023115319A1/zh
Priority to CN202180098716.8A priority patent/CN117396857A/zh
Publication of WO2023115319A1 publication Critical patent/WO2023115319A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Definitions

  • the present application relates to the technical field of data processing, and in particular to a data storage method, storage device and equipment.
  • Memory also known as internal memory, is an important part of the computer, used to temporarily store the calculation data of the central processing unit (central processing unit, CPU), and exchange data with external memory such as hard disk.
  • the development speed of the processor is much faster than the development of the memory.
  • the annual growth rate of the calculation core (core) in the computer processor can reach 50%.
  • the bandwidth (bandwidth) and delay (latency) of the memory interface are reduced. Small ones are much slower. Therefore, memory has become a key factor restricting computer data processing capabilities.
  • IT information technology
  • Embodiments of the present application provide a data storage method, storage device, and equipment, which can improve the utilization rate of memory interface bandwidth.
  • a data storage method can be applied to a storage device, and the storage device includes a memory controller and a first memory, and the first memory includes at least one storage space.
  • the method includes: the memory controller determines the first burst length for transmitting the first data from various burst lengths according to the data amount of the first data; the memory controller sends the first burst length to the first memory The first instruction information of the length, and send the first data to the first memory according to the first burst length; the first memory receives the first data according to the first instruction information and according to the first burst length; the first memory will The first data is stored in the first storage space of the at least one storage space.
  • the burst length refers to the required data transmission times when the memory controller sends the first data to the first memory. For example, when the burst length is 2, the memory controller sends the first data to the first memory through two data transmissions. For another example, when the burst length is 4, the memory controller sends the first data to the first memory through 4 data transmissions. Since the amount of data transmitted in each data transmission is the same, different burst lengths can transmit different amounts of data, in other words, different amounts of data correspond to different burst lengths. Moreover, the larger the burst length, the larger the amount of data that can be transmitted. In other words, a larger amount of data corresponds to a larger burst length.
  • the burst length supported by the memory controller and the memory is fixed.
  • the data needs to be compressed to a data volume corresponding to the fixed burst length. In this way, the compressed data can be transmitted to the memory.
  • the data cannot be compressed to the corresponding fixed-length data volume, the data cannot be compressed (the compressed data volume cannot correspond to the burst length and cannot be transmitted), resulting in many types of data that cannot be compressed. Bandwidth utilization is low.
  • the memory controller and the first memory support multiple burst lengths, that is, data transmission can be performed according to multiple burst lengths.
  • the first burst length matching the data amount of the first data can be selected from various burst lengths according to the data amount of the first data, and the first burst length can be selected according to the first burst length.
  • the length sends the first data to be sent to the first memory. Therefore, when compressing the original data of the first data into the first data, there is no need to consider too much that the compressed data does not correspond to the burst length, so that the first data can be compressed more freely, and further Improve the utilization of memory interface bandwidth.
  • the memory controller may notify the first memory of the first burst length used to transmit the first data, so that the first memory knows that the memory controller sends the first data according to the first burst length, so that When the burst length between the controller and the first memory is variable, the first data is correctly received, so as to complete the storage of the first data.
  • the first indication information includes a first compression rate
  • the first data is obtained by compressing the original data with a preset size according to the first compression rate, and the first compression rate corresponds to the first compression rate. burst length; or, the first indication information includes identification information representing the first burst length.
  • the corresponding relationship between the compression rate and the burst length can be established, and then the notification of the burst length can be realized by notifying the compression rate to the first memory; or, the burst length can be directly The identification information is notified to the first memory, so as to realize the notification of the burst length.
  • the memory controller determines the first time interval for sending the read command according to the second burst length; wherein, the second burst length is the smallest among various burst lengths; the memory controller According to the first time interval, N read commands are sequentially sent to the first memory, where N is an integer greater than or equal to 1.
  • a read command can trigger the first memory to perform a burst transfer. It can be understood that the shorter the burst length is used for burst transmission (that is, the fewer the number of data transmissions in the burst transmission), the shorter the time interval between two burst transmissions.
  • the memory controller sends the read command for the first time, it does not know how much burst length the first memory will use to send data to the memory controller. If the time for the memory controller to send the read command to the first memory is longer than the time interval between two adjacent burst transfers of the first memory, then the first memory needs to wait for the arrival of the read command when the previous burst transfer is completed. to perform the next burst transfer. In this way, the efficiency of data reading is reduced.
  • the memory controller may determine the time interval for the memory controller to send the read command to the first memory according to the minimum burst length among various burst lengths (that is, the memory controller assumes that the first memory uses the minimum burst length Burst transmission of burst length, send data to the memory controller, and determine the time interval for sending the read command accordingly) so as to reduce or avoid the discontinuous data sending caused by the first memory waiting for the read command, thereby improving the memory interface. Utilization in the read direction.
  • the first time interval is not greater than the sending time interval of the read command with the second burst length.
  • the second burst length is the minimum burst length among multiple burst lengths, and the duration of burst transmission using the second burst length is relatively short. If the first memory sends data to the memory controller according to the second burst length (that is, the first memory returns data according to the second burst length), the memory controller needs to send read commands according to a shorter time interval to ensure that the first memory A memory can obtain read commands in time, and then respond to the read commands, and send data to the memory controller, so as to realize continuous sending of data.
  • the time interval for the memory controller to send the read command to the first memory is not greater than the time interval for sending the read command when returning data according to the second burst length, so that the first memory is sent according to the second burst length.
  • the burst length sends data to the memory controller, it can ensure that the first memory obtains the read command in time, thereby avoiding the situation caused by waiting for the read command when the first memory sends data to the memory controller according to the second burst length.
  • the data transmission is discontinuous, thereby improving the utilization rate of the memory interface in the read direction.
  • the memory controller receives the second indication information of the third burst length sent by the first memory, where the first memory sends the second data to the memory controller according to the third burst length, and the second The second data corresponds to the first read command in the N read commands; when the third burst length is different from the second burst length, the memory controller determines to use the second time interval according to the third burst length; the memory controller According to the second time interval, multiple second read commands are sequentially sent to the first memory, and the multiple second read commands are read commands sent by the memory controller after sending the N read commands.
  • the first memory can notify the memory controller of the burst length it uses to return data to the memory controller, and the memory controller can adjust the data sent to the first memory according to the burst length.
  • the time interval when sending the read command again improves the consistency between the sending time interval of the read command and the execution time interval of the read command, so that while ensuring that the first memory seamlessly sends data to the memory controller, it is not necessary to always follow the smaller
  • the time interval for sending read commands is to send read commands to the first memory, which avoids sending too many read commands to the first memory in a short period of time, causing the read commands to be executed too late, causing the problem of excessive pressure on the first memory cache read commands .
  • the first data is obtained by compressing the original data
  • the data volume of the original data is not greater than the data volume that can be transmitted in one fourth burst length
  • the fourth burst length is in multiple The largest burst length.
  • the data volume of the first data before being compressed is not greater than the data volume that can be transmitted by the largest burst transmission among various burst lengths, which ensures that the data volume of the first data is not greater than the maximum
  • the amount of data that can be transmitted by the burst length ensures that the memory controller can completely send the first data to the first memory through one burst transmission, which minimizes the delay of the memory interface in the write direction and improves The utilization of the memory interface is improved.
  • the memory controller sending the first indication information of the first burst length to the first memory includes: the memory controller sending a first write command to the first memory, the first write command carrying the first Instructions.
  • the memory controller can carry the indication information of the burst length in the write command, and when sending the write command to the first memory, it can also send the indication of the burst length to the first memory. information, which further saves the bandwidth of the memory interface and improves the utilization rate of the bandwidth of the memory interface.
  • the method further includes: the memory controller determines the time interval between the sending moment of the first write command and the sending moment of the second write command according to the first burst length; wherein, the first The write command is used to indicate the address of the first storage space; the second write command is used to indicate the address of the second storage space in at least one storage space; wherein, the second storage space is used to store the third data, and the third data is the memory After the first data is sent, the controller then sends the data to the first memory.
  • the memory controller can determine the sending time of the next write command according to the burst length used in this data transmission, so that when the burst length of this data transmission is small or the current When the time occupied by a data transmission is short, the next write command is sent to the first memory as soon as possible, so that the next data transmission can be triggered as soon as possible, ensuring seamless data transmission and improving the utilization rate of the memory interface.
  • the memory controller sends a third read command to the first memory, where the third read command includes a first address, and the first address is a partial address among multiple addresses corresponding to the third storage space;
  • the controller first sends data corresponding to the first address to the memory controller, and then sends data corresponding to other addresses among the multiple addresses to the memory controller.
  • the data corresponding to the address in the read command may be the data that is preferentially required by the initiator of the read command (such as a processor).
  • the first memory can preferentially send the data corresponding to the address in the read command to the memory controller, so that the memory controller can preferentially send the data to the initiator of the read command, so that the data can be sent as soon as possible to the initiator of the read command, improving the performance of the storage device.
  • the first storage space is also used to store the first indication information; the method further includes: the memory controller sends a fourth read command to the first memory, and the fourth read command includes the information of the first storage space. address; the first memory reads the first data and the first instruction information according to the address of the first storage space; the first memory sends the first instruction information to the memory controller, and sends the first instruction information to the memory controller according to the first burst length A data; the memory controller receives the first data according to the first indication information and according to the first burst length.
  • the first memory can store the first indication information and the first data in the same storage space, thus, when the first memory reads the first data from the storage space in response to the read command , the first indication information can also be read, so that the first burst length can be determined as soon as possible according to the first indication information, and then the first data can be returned to the memory controller according to the first burst length, which improves the data return efficiency and memory interface utilization.
  • the first memory may send the first indication information to the memory controller, so that the memory controller knows that the first memory sends the first data according to the first burst length, so that the memory controller and the first memory can communicate In the case where the burst length is variable, the first data is correctly received, and then the reading of the first data can be completed.
  • the method further includes: the memory controller decompresses the first data according to the first indication information.
  • the memory controller may determine, according to the first indication information, that the first memory sends the first data according to the first burst length, and then, according to the first burst length, determine the compression rate corresponding to the first data, and The first data is decompressed.
  • the first data is obtained by compressing the original data of a preset size according to a first compression rate; wherein, the first compression rate is obtained by compressing the original data into the A data compression algorithm is determined.
  • the first data may be compressed according to the compression rate determined by the data type of the original data and the compression algorithm without being limited to a fixed burst length.
  • a data storage device including a memory controller and a first memory, where the first memory includes at least one storage space, wherein the memory controller is used to select from multiple burst lengths according to the data amount of the first data Determine the first burst length used to transmit the first data; the memory controller is used to send the first indication information of the first burst length to the first memory, and send the first data to the first memory according to the first burst length ; The first memory is used to receive the first data according to the first indication information according to the first burst length; the first memory is used to store the first data in the first storage space of the at least one storage space.
  • the first indication information includes a first compression rate
  • the first data is obtained by compressing the original data with a preset size according to the first compression rate, and the first compression rate corresponds to the first compression rate. burst length; or, the first indication information includes identification information representing the first burst length.
  • the memory controller is further configured to determine the first time interval for sending the read command according to the second burst length; wherein, the second burst length is the smallest among various burst lengths; The memory controller is further configured to sequentially send N read commands to the first memory according to the first time interval, where N is an integer greater than or equal to 1.
  • the first time interval is not greater than the sending time interval of the read command with the second burst length.
  • the memory controller is further configured to receive the second indication information of the third burst length sent by the first memory, where the first memory sends the second instruction information to the memory controller according to the third burst length.
  • data the second data corresponds to the first read command in the N read commands; when the third burst length is different from the second burst length, the memory controller is also used to determine the second time according to the third burst length interval; the memory controller is further configured to sequentially send a plurality of second read commands to the first memory according to a second time interval, and the plurality of second read commands are read commands sent by the memory controller after sending N read commands.
  • the first data is obtained by compressing the original data
  • the data volume of the original data is not greater than the data volume that can be transmitted in one fourth burst length
  • the fourth burst length is in multiple The largest burst length.
  • the memory controller is further configured to send a first write command to the first memory, where the first write command carries first indication information.
  • the memory controller is further configured to determine the time interval between the sending moment of the first write command and the sending moment of the second write command according to the first burst length; wherein, the first write command Used to indicate the address of the first storage space; the second write command is used to indicate the address of the second storage space in at least one storage space; wherein, the second storage space is used to store third data, and the third data is a memory controller After the first data is sent, the data sent to the first memory is followed.
  • the memory controller is further configured to send a third read command to the first memory, where the third read command includes a first address, and the first address is a part of multiple addresses corresponding to the third storage space address; the memory controller is further configured to, in response to the third read command, first send data corresponding to the first address to the memory controller, and then send data corresponding to other addresses among the multiple addresses to the memory controller.
  • the first storage space is also used to store the first indication information; the memory controller is also used to send a fourth read command to the first memory, where the fourth read command includes an address of the first storage space;
  • the first memory is also used to read the first data and the first indication information according to the address of the first storage space; the first memory is also used to send the first indication information to the memory controller, and send the first indication information to the memory according to the first burst length
  • the controller sends the first data; the memory controller is further configured to receive the first data according to the first burst length according to the first indication information.
  • a computing device including: a processor and the storage device provided in the first aspect.
  • the memory controller when the memory controller needs to send data to the memory, it can select a burst length that matches the data amount from a variety of burst lengths according to the data amount, and according to the The burst length sends the data to memory to be sent. Therefore, when compressing the data, it is not necessary to stick to a fixed burst length, and the data can be compressed more freely, thereby improving the utilization rate of the bandwidth of the memory interface. Moreover, the memory controller can notify the memory of the burst length used to transmit the data, so that the memory knows that the memory controller sends data according to the burst length, so that the burst length between the memory controller and the memory can be controlled. In the event of a change, the data is received correctly to complete the storage of the data.
  • FIG. 1 is a schematic diagram of an applicable architecture of the data storage solution provided by the embodiment of the present application.
  • Fig. 2 is a flow chart of the data storage scheme provided by the embodiment of the present application.
  • Fig. 3 is the schematic diagram that the embodiment of the present application improves memory interface utilization
  • FIG. 4 is a schematic diagram of improving memory interface utilization in an embodiment of the present application.
  • FIG. 5 is a flow chart of a data storage method provided by an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of a storage device provided by an embodiment of the present application.
  • Fig. 7 is a schematic block diagram of a computing device provided by an embodiment of the present application.
  • the memory interface is the channel through which data enters and exits memory.
  • the memory controller memory controller, MC
  • MC memory controller
  • MC memory controller
  • MC memory controller
  • the memory controller can send the data to the memory through a memory interface.
  • the processor needs to read data stored in the memory
  • the memory can send the data to the memory controller through the memory interface, and then the memory controller sends the data to the processor. Therefore, the bandwidth of the memory interface is critical to the speed at which the processor can access data.
  • Burst transmission refers to the way in which adjacent storage units in the same row perform data transmission continuously.
  • one burst transmission may include multiple consecutive data transmissions, and the specific times of the multiple data transmissions may be referred to as burst lengths (burst lengths, BL).
  • burst lengths burst lengths, BL.
  • the burst length of a burst transfer can be set to be 8, that is, BL is 8 (may be referred to as BL8 for short), then the burst transfer includes 8 data transfers, and the 8 data transfers can be performed continuously, namely During the execution of 8 data transfers, there is no need to provide column addresses for each data transfer.
  • the memory when using burst transfer for data transfer, after specifying the row address of the storage unit in the memory array, as long as you specify the starting column address and burst length of the storage unit, the memory will automatically transfer the corresponding number of Read/write operations are performed on memory cells without the need for the memory controller to continuously provide column addresses.
  • the memory interface supports a burst length of 8 (BL8), that is, a burst transmission is performed between the memory controller and the memory through BL8, and each burst transmission includes 8 cycles of continuous transmission.
  • BL8 can transmit a data volume of up to 64 bytes (byte, B).
  • the granularity of 128B is used for data compression, that is, the original data is divided according to the size of 128B, and then the original data with a data volume of 128 is compressed. Since the memory interface of this solution only supports BL8, the supported compression ratio is 2:1. It can be understood that the compression rate is jointly determined by the original data and the compression algorithm adopted.
  • the original data when the compression ratio determined by the original data and the compression algorithm is exactly 2:1, the original data can be compressed. If the determined compression ratio is not 2:1, but a compression ratio of other sizes (for example, 3:1), the original data is considered to be incompressible, and the original data is not compressed. In short, in scheme A, 128B of raw data can be compressed at most 2:1, or not compressed (eg, when). Therefore, solution A has a limited improvement in memory interface bandwidth utilization.
  • the embodiment of the present application provides a data storage solution.
  • the memory interface can support multiple burst lengths.
  • the memory controller can select from multiple burst lengths according to the amount of data to be sent. Select a burst length in , and use the selected burst length to send the data to be sent to the memory, and send the indication information of the selected burst length to the memory.
  • the memory can receive the data sent by the memory controller according to the burst length indicated by the instruction information, so as to realize correct data reception.
  • the corresponding burst length can be selected according to the data volume of the data to be sent, thus, when the data to be sent is compressed, the burst length is not limited, and the burst length can be selected according to the data volume to be sent.
  • the data type of the data to be sent and the compression ratio determined by the compression algorithm are used to compress the data to be sent, so as to reduce the data volume of the compressed data.
  • the compressed data can then be sent using a burst length that matches the compressed data. Thereby, the bandwidth utilization rate of the memory interface can be improved to the greatest extent.
  • FIG. 1 shows an applicable architecture of the data storage solution provided by the embodiment of the present application, and the architecture includes a storage device 100 and a processor 200 .
  • the storage device 100 may include a memory controller 110 and a memory 120 .
  • the memory 120 may be an independent memory, or may be a memory cluster composed of multiple memories.
  • the memory 120 can be random access memory (random access memory, RAM) or other main memory (main memory).
  • RAM random access memory
  • main memory main memory
  • the memory 120 exchanges data with the processor 200 .
  • the memory 120 can be used to store data, and the processor 200 can write data into the memory 120 , and the data stored in the memory 120 can be read or called by the processor 200 .
  • the memory controller 100 can be used to manage data exchange between the memory 120 and the processor 200 .
  • the processor 200 can first send the data and the write command to the memory controller 110, and then the memory controller 110 sends the data and the write command to the memory 120 .
  • the memory 120 may store the data in a corresponding storage space in response to the write command.
  • the processor 200 can send the read command to the memory controller 110 , and then the memory controller 110 can send the read command to the memory 120 .
  • the memory 120 may respond to the read command and send corresponding data to the memory controller 110 , and then the memory controller 110 sends the data to the processor 200 .
  • the data exchange between the memory controller 110 and the memory 120 will be specifically introduced below, and will not be repeated here.
  • the memory controller 110 may be a conventional memory controller. Traditional memory controllers can be located inside the Northbridge chip in the motherboard chipset. In some embodiments, the memory controller 110 may be an integrated memory controller. Wherein, the integrated memory controller can be integrated into the processor. In other words, the memory controller 110 can be integrated into the processor 200 .
  • the memory controller 110 and the memory 120 may support multiple burst transfers, wherein the burst lengths of different burst transfers are different, that is, the number of cycles of continuous transfer in different types of burst transfers is different.
  • the memory controller 110 and the memory 120 can support multiple burst lengths, and can select any burst length from the multiple burst lengths for burst transmission. Therefore, when compressing data, it is not necessary to stick to a fixed burst length, and the data can be compressed according to different compression ratios, thereby improving the utilization rate of the bandwidth of the memory interface.
  • the specific functions of the memory controller 110 and the memory 120 will be introduced below, and will not be repeated here.
  • the processor 200 may be a central processing unit. In some embodiments, the processor 200 may be a graphics processing unit (graphics processing unit, GPU). In some embodiments, the processor 200 may be an application specific integrated circuit (ASIC). In some embodiments, the processor 200 may be a neural-network processing unit (neural-network processing unit, NPU). In some embodiments, the processor 200 may also be other forms of devices with data processing capabilities. The present application does not specifically limit the implementation form of the processor 200 .
  • the storage device 100 and the processor 200 may be deployed in the same computing device.
  • the computing device may be a server, a mobile terminal (such as a mobile phone, a tablet computer, a notebook computer), or a vehicle-mounted terminal.
  • the embodiment of the present application does not specifically limit the implementation form of the computing device where the storage device 100 and the processor 200 are located.
  • the storage device 100 and the processor 200 may also be respectively deployed in different computing devices.
  • FIG. 2 shows the flow of the data storage solution provided by the embodiment of the present application.
  • the processor 200 when the processor 200 needs to store data in the memory, it may execute step 200 to send the write command WC1 and the data D1 to the memory controller 110 .
  • the memory controller can receive the write command WC1 and the data D1.
  • the data D1 belongs to write data, which is data that needs to be stored or written into the memory 120 .
  • the memory controller 110 may include a command buffer for buffering write commands received from the processor, such as the write command WC1 .
  • the command cache can be CMD que.
  • the memory controller 110 may also include a write data cache module, configured to cache data received from the processor, such as data D1.
  • the write data cache can be Wdata que.
  • the memory controller 110 may respond to the write command WC1 and execute step 202 to determine the burst length D11 from various burst lengths according to the data amount of the data D1 .
  • the various burst lengths are various burst lengths supported by the memory controller 110 and the memory 120 mentioned above.
  • the memory controller 110 may include a burst length determination module, which may be used to execute step 202 .
  • Step 202 may specifically be implemented in the following manner.
  • Data compression may be performed on the data D1, and then, in step 202, the memory controller 110 may determine the burst length D11 from various burst lengths according to the data volume of the compressed data D1. Next, a specific description will be given.
  • the data compression performed on the data D1 may be performed by the memory controller 110 .
  • the memory controller 110 may include a compression module for performing data compression on write data.
  • the data compression module can perform data compression on the data D1 to obtain compressed data D1.
  • the memory controller may include a compression module, which may be used to compress data received by the memory controller 110 .
  • data compression on data D1 may be performed by processor 200 .
  • the data compression of the data D1 may be performed by any device B1 having data processing capabilities on the data path, and the data path is the path for data interaction between the processor 200 and the memory controller 100 .
  • the data D1 may be compressed by using a preset compression algorithm (for example, a fixed-point continuation algorithm (fixed-point continuation, FPC)).
  • a preset compression algorithm for example, a fixed-point continuation algorithm (fixed-point continuation, FPC)
  • the data D1 may be compressed according to the data type of the data D1 and the compression rate determined by the compression algorithm.
  • the data D1 can be compressed at a compression rate determined by the data type of the data D1 and the compression algorithm without being limited to a fixed burst length.
  • the compression ratio determined by the data type of the data D1 and the compression algorithm is 3:1
  • the data D1 can be compressed to one third of its original size.
  • the data type of the data D1 and the compression algorithm determine a compression ratio of 4:1
  • the data D1 can be compressed to a quarter of its original size.
  • the compression rate refers to the ratio between the amount of data before data compression and the amount of data after data compression, wherein the compression rate can be greater than 1 or equal to 1 (ie When the data is determined to be incompressible according to the data type and compression algorithm of the data before compression, it can be considered that the compression rate determined according to the data type and compression algorithm of the data before compression is 1).
  • data before compression may be referred to as original data
  • data after compression may be referred to as compressed data.
  • the data volume of the original data of the data D1 is not greater than the data volume threshold.
  • the data volume threshold is the maximum data volume that can be transmitted in one burst transmission between the memory controller 110 and the memory 120 .
  • the memory controller 110 and the memory 120 can perform burst transmission with any burst length among various burst lengths. It can be understood that when the burst transmission is performed with the maximum burst length among the various burst lengths, the amount of data that can be transmitted in one burst transmission between the memory controller 110 and the memory 120 is the largest.
  • the data volume threshold is the data volume that can be transmitted by the maximum burst length among the various burst lengths supported by the memory controller 110 and the memory 120 .
  • the memory controller 110 and memory 120 support BL8 (that is, a burst transfer includes 8 cycles of continuous transfer), BL6 (that is, a burst transfer includes 6 cycles of continuous transfer), BL4 (that is, a burst transfer includes 6 cycles of continuous transfer), BL4 (that is, a burst Send transmission includes 4 cycles of continuous transmission).
  • BL8 is the largest.
  • the data amount threshold is the value when the memory controller 110 and memory 120 use BL8 for burst transmission. The amount of data that can be transferred.
  • the data when the compression of the data D1 is performed by the memory controller 110, if the data volume of the data received by the memory controller from the processor 200 is not greater than the data volume threshold, the data can be As the data D1, data compression processing is performed on the data D1. If the data volume of the data received by the memory controller from the processor 200 is greater than the data volume threshold, data D1 with a data volume not greater than the data volume threshold can be selected from the data, and the data D1 is compressed to obtain compressed data. D1.
  • the processor 200 or the device D1 may select from the data to be written, the data whose data size is not greater than the data size threshold data, and perform data compression to obtain compressed data D1.
  • the compressed data D1 can be obtained.
  • the burst length D11 is determined from various burst lengths according to the data volume of the compressed data D1.
  • the memory controller 110 and the memory 120 can use any burst length among various burst lengths to perform burst transmission, and the data volume corresponding to each burst length among the various burst lengths can be preset.
  • the amount of data corresponding to each burst length is not greater than the amount of data that can be transmitted by the burst length.
  • the amount of data that can be transmitted with the burst length refers to the amount of data that can be transmitted when the burst length is used for burst transmission.
  • a burst length corresponding to the data volume may be determined from various burst lengths, and the determined burst length may be used as the burst length D11.
  • the data size of the original data (that is, the data before compression) is consistent, for example, they are all the above-mentioned data size threshold.
  • the compression ratio used during data compression corresponds to the data volume of the compressed data in a one-to-one correspondence.
  • the compression ratio used during data compression may represent the data volume of the compressed data. Therefore, the preset data amount corresponding to each burst length among the multiple burst lengths may be specifically, preset the compression rate corresponding to each burst length among the multiple burst lengths. Therefore, in step 202, the burst length D11 can be determined from various burst lengths specifically according to the compression rate corresponding to the data D1 (that is, the compression rate used when performing data compression on the data D1).
  • the memory controller 110 when the compression of the data D1 is performed by the memory controller 110, the memory controller 110 can perceive the compression rate corresponding to the data D1, thus, in step 202, the memory control The processor 110 may determine the burst length D11 according to the compression rate corresponding to the data D1.
  • the processor 200 or the device B1 may send the compression rate corresponding to the data D1 to the memory controller 110, so that The memory controller 110 may determine the burst length D11 in step 202 according to the compression rate corresponding to the data D1.
  • the memory controller 110 may determine the data volume of the compressed data D1, and directly select the data volume that can carry the compressed data in various burst lengths according to the data volume of the compressed data D1.
  • the minimum burst length of the data D1 is determined as the burst length D11.
  • the memory controller 110 can determine the burst length D11 in step 202 .
  • the determined burst length D11 is used for sending the data D1 or the compressed data D1 to the memory 120 in a subsequent step. That is, the memory controller 110 will send the data D1 to the memory 120 according to the burst length D11. Since the burst length D11 is determined by the memory controller 110 from various burst lengths, rather than a fixed burst length, the memory controller 110 needs to notify the memory 120 of the burst length D11, so that the memory 120 can The data D1 or the compressed data D1 is received according to the burst length D11 to realize correct data reception.
  • the memory controller 110 may execute step 203 to send the indication information of the burst length D11 to the memory 120 .
  • the indication information of the burst length D11 refers to information that may identify or represent the burst length D11, and may also refer to information corresponding to the burst length D11.
  • the burst length D11 may be determined.
  • the indication information of the burst length D11 may be a compression rate corresponding to the data D1.
  • the memory controller 110 can perceive the compression rate corresponding to the data D1, thus, in step 203, the compression rate corresponding to the data D1 can be used as the burst length D11
  • the instruction information is sent to the memory 120 .
  • the processor 200 or the device B1 can send the compression rate corresponding to the data D1 to the memory controller 110, so that the memory controller 110 can in step 203, the data
  • the compression rate corresponding to D1 is sent to the memory 120 as the indication information of the burst length D11.
  • the indication information of the burst length D11 may be identification or identification information representing the burst length.
  • the identification information may be set for various burst lengths supported by the memory controller 110 and the memory 120, wherein the identification information of different burst lengths is different.
  • the identification information may be a set number, and the number may consist of numbers and/or letters.
  • the identification information may be a string. The embodiment of the present application does not specifically limit the form of the identification information.
  • the memory controller 110 determines the burst length D11 from various burst lengths, it can obtain the identification information of the burst length D11 , and then in step 203 , send the identification information of the burst length D11 to the memory 120 .
  • the memory controller 110 needs to send data to the memory 120 through burst transfer and instruct the memory 120 to store the data, that is, when the memory controller 110 performs a write operation through burst transfer, the memory controller 110 needs to send
  • the write command is sent to the memory 120, wherein the write command includes address information.
  • the memory 120 may store data received through the burst transfer into a storage space indicated by the address information.
  • the address information may be a starting address, that is, the memory 120 may use the address information in the write command as the starting address of the storage space, and determine the storage space for storing data according to the preset storage space length.
  • the memory controller 110 needs to send the write command WC1 to the memory 120.
  • the memory controller 110 may send a write command WC1 to the memory controller 110 through a control channel.
  • the control channel may specifically be an address command (address command, AC) channel.
  • the memory controller 120 may carry the indication information of the burst length D11 into the write command WC1, and in step 203, send the write command WC1 to the memory 120, so that the indication information of the burst length D1 sent to memory 120.
  • the write command WC1 is cached in the command cache, and the memory controller 120 may write the indication information of the burst length D11 into the write command WC1.
  • the memory controller 110 may write the compression ratio corresponding to the data D1 into the write command WC1 when obtaining the compression ratio corresponding to the data D1.
  • the indication information of the burst length D11 is the identification information of the burst length
  • the identification information of the burst length D11 can be Write to write command WC1.
  • the memory controller 110 may send the write command WC1 to the memory 120 in step 203 .
  • the memory controller 110 may execute step 204 to send data D1 to the memory 120 according to the burst length D11 .
  • the data D1 here refers to the data used to determine the burst length D11 in step 202 . That is, in step 202 , the memory controller 110 determines the burst length D11 according to the data volume of the data D1 to be sent in step 204 .
  • the data D1 here may also be referred to as compressed data D1.
  • the data D1 mentioned below refers to or is equivalent to the data D1 sent by the memory controller 110 in step 204 .
  • the data D1 may be stored in the write data cache.
  • the write data cache may specifically be Wdata que.
  • the memory controller 110 may take out the data D1 from the write data cache, and through step 204, send the data D1 to the memory 120 according to the burst length D11.
  • the memory controller 110 may send the data D1 to the memory 120 through the data channel.
  • the data channel may include a bidirectional data bus (Bi-directional data bus, DQ) channel.
  • the data channel may include a DQ channel and a data mask (data mask, DM) channel.
  • the memory controller 110 may need to send multiple data including the data D1 to the memory 120 .
  • the cache of the command cache module in the memory controller 110 can cache multiple write commands, and the multiple write commands can be in one-to-one correspondence with the multiple data. It can be understood that when different burst lengths are used to transmit data, the occupied time lengths are different. A larger burst length occupies a larger duration, and a smaller burst length occupies a shorter duration.
  • the memory controller 110 determines from a variety of burst lengths for sending When or after the burst length D11 of the data D1, the memory controller 110 may determine the time interval T1 between the sending moment of the write command WC1 and the sending moment of the next write command according to the burst length D11.
  • the sending time of the write command WC1 refers to the time when the memory controller 110 sends the write command WC1 to the memory 120 .
  • the sending of the write command WC1 indicates that the memory controller 110 starts or immediately sends the data D1 to the memory 120 .
  • the write command WC1 includes address information, and the address information is used to indicate to the memory 120 the address of the storage space for storing the data D1, so that the memory 120 can store the data D1 in the storage space indicated by the address information.
  • the next write command refers to the write command sent by the memory controller 110 to the memory 120 after sending the write command WC1 .
  • the sending of the next write command indicates that the memory controller 110 starts or immediately sends the data D2 to the memory 120 .
  • the data D2 is data sent to the memory 120 after the memory controller 110 sends the data D1 to the memory 120 .
  • the next write command includes address information, and the address information is used to indicate to the memory 120 the address of the storage space for storing the data D2, so that the memory 120 can store the data D2 in the storage space indicated by the address information.
  • the size of the time interval T1 determined according to the burst length D11 is proportional to the size of the burst length. That is, the larger the burst length D11, the larger the determined time interval; the smaller the burst length D11, the smaller the determined time interval.
  • the time interval T1 is equal to the transmission duration of the burst length D11, wherein the transmission duration of the burst length D11 refers to the time occupied by the burst transmission when the burst transmission is performed with the burst length D1.
  • the memory controller 110 can send the next data immediately after sending one piece of data, while ensuring the orderly transmission of data , It also ensures the seamless transmission of data and improves the efficiency of data transmission.
  • FIG. 3 shows the data transmission efficiency of the above solution A and the solution of the embodiment of the present application.
  • the memory controller uses the fixed burst length of BL8 to send data to the memory, wherein the sending time of adjacent write commands is also fixed. The time occupied by BL8 is longer, therefore, the data transmission efficiency of solution A is lower.
  • the data can be compressed without being limited to a fixed burst length, so that the data can be compressed into data with a small amount of data.
  • the determined burst length is also relatively small, for example, BL6 and BL4 shown in FIG. 3 .
  • the data that needs to be transmitted by BL8 in BL6 or BL4 transmission scheme A can be adopted, and the size of the sending time interval according to the write command is proportional to the size of the burst length (for example, the write command 31 and the time interval between the write command 32 is determined by BL6, and the time interval between the write command 32 and the write command 33 is determined by BL4), when a smaller burst length is used to transmit data, the next write can also be sent as soon as possible command, so that the subsequent data transmission can be carried out as soon as possible. Therefore, compared with solution A, in the solution provided by the embodiment of the present application, the data transmission efficiency of the memory controller to the memory is higher, and the utilization rate of the bandwidth of the memory interface between the memory controller and the memory is higher.
  • the memory 120 may execute step 205 to receive data D1 according to the burst length D11 according to the indication information of the burst length D11 .
  • the memory 120 may determine that the memory controller 110 uses the burst length D11 according to the indication information of the burst length D11.
  • the data D1 is sent, thus, the memory 120 can receive the data sent by the memory controller 110 according to the burst length D11, so as to realize the correct reception of the data D1.
  • the memory 120 may determine the data sent by the memory controller 110 received according to the burst length D11 as the data D1.
  • the memory 120 may cache the received data D1 in the data path, and then, when step 206 is executed, take the data D1 out of the data path and store it in a designated storage space.
  • the memory 120 includes at least one storage space.
  • the memory 120 needs to determine the storage space D12 for storing the data D1 from the at least one storage space when or before executing step 206 .
  • the write command WC1 includes address information indicating a storage space.
  • the memory 120 may determine the storage space indicated by the address information as the storage space D12 for storing the data D1.
  • the memory 120 may store the data D1 into the storage space D12.
  • the address information in the write command WC1 specifically indicates the starting address of the storage space D12, and the memory 120 can use the address indicated by the address information as the starting address, and extend backward a preset number of addresses to obtain the storage space D12. For example, if the address information in the write command WC1 indicates the address C0, then the addresses represented by the address C0 and the address C1, address C2, address C3, address C4, address C5, address C6, and address C7 can be stored Space is used as storage space D12.
  • the data D1 received by the burst length D11 may be sequentially stored in the storage space D12 according to the data receiving sequence.
  • the burst length D1 can be set as BL4, that is, when the memory 120 receives the data D1 according to the burst length D11, the number of received continuous transmissions is 4. It can also be set that the storage space D12 includes address C0, address C1, address C2, address C3, address C4, address C5, address C6, and address C7.
  • the memory 120 can store the data transmitted in the first cycle in the continuous transmission with the cycle number of 4 to the address C0, and store the data transmitted in the second cycle in the continuous transmission with the cycle number of 4 in the address C1 , the data transmitted in the third cycle in the continuous transmission with the cycle number of 4 is stored in the address C2, and the data transmitted in the fourth cycle in the continuous transmission with the cycle number of 4 is stored in the address C3.
  • the data D1 received by the memory 120 from the memory controller 100 is compressed data D1.
  • the memory 120 may not decompress the received data D1, but directly store it in the storage space D12, thereby saving storage resources.
  • the memory 120 can also save the indication information of the burst length D11, so that when the memory 120 returns the data D1 to the memory controller 110 (for example, the processor 200 reads the data D1), it can use the indication information of the burst length D11 again to determine the use of Burst length D11 transmits data D1.
  • the memory 120 may also store the indication information of the burst length D11 together with the data D1.
  • the memory 120 can store the indication information of the burst length D11 and the data D1 in the same storage space, that is, can store the indication information of the burst length D11 in the storage space D12.
  • the burst length D11 is not the maximum burst length among the various burst lengths, it means that the compression rate corresponding to the data D1 is greater than 1.
  • the memory 120 may add a compression mark to the data D1 to identify the data D1 as compressed data with a compression rate greater than 1. If the burst length D11 is the maximum burst length among the various burst lengths, it means that the compression rate corresponding to the data D1 is 1, and no compression mark is added to the data D1.
  • the various burst lengths are the various burst lengths supported by the memory controller 110 and the memory 120 mentioned above.
  • the above example introduces the scheme of storing data in the memory 120 .
  • the scheme of reading data from the memory 120 is introduced.
  • the processor 200 may execute step 207 to send the read command RC1 to the memory controller 110 .
  • the read command RC1 is used to read the data D1.
  • the memory controller 110 may execute step 208 to send the read command RC1 to the memory 120 to trigger the memory 120 to send the data D1 to the memory controller 110 .
  • the memory controller 110 may first cache the read command RC1 into the command cache, and when executing step 208, take the read command RC1 out of the command cache, and then pass through step 208, Send the read command RC1 to the memory 120 .
  • the memory controller 110 may send the read command RC1 to the memory 120 through a control channel.
  • the memory 120 may respond to the read command RC1 and execute step 209 to read the data D1.
  • the memory 120 may first cache the received read command RC1 into the command cache.
  • the read command RC1 has been arbitrated and can be executed, the read command RC1 is taken out from the command cache, and step 209 is executed.
  • the read command RC1 may include address information indicating the address of the storage space D12 in which the data D1 is stored.
  • the memory 120 determines that the data D1 is stored in the storage space D12 according to the address information, and then the memory 120 can read the data D1 from the storage space D12.
  • the storage space D12 also stores the indication information of the burst length D11, and the memory 120 can also read the indication information of the burst length D11 while reading the data D1.
  • the memory 120 After the memory 120 reads the indication information of the burst length D11, it can execute step 210 to send the indication information of the burst length D11 to the memory controller 110, so that the memory controller 110 can, in subsequent steps, perform the burst length D11 according to the burst length D11. receiving the data D1 sent by the memory 120 .
  • the memory 120 may send the indication information of the burst length D11 to the memory 110 through a DM channel.
  • the memory 120 can determine the burst length D11 according to the indication information of the burst length D11, and execute step 211 to send the data D1 to the memory controller 110 according to the burst length D11.
  • the memory controller 110 may receive the data D1 sent by the memory 120 according to the burst length D11 according to the indication information of the burst length D11 received in step 210 .
  • the memory controller 110 may determine the burst length D11 according to the indication information of the burst length D1, and receive the data D1 sent by the memory 120 according to the burst length D11.
  • the data path of the memory 120 can read the data D1 and send the data D1 to the memory controller 110 through the data channel.
  • the memory 120 can also send the compression flag of the data D1 to the memory controller 110, so that the memory controller 110 can determine whether the compression ratio corresponding to the data D1 is greater than 1 as soon as possible. If the memory controller 110 receives the compression flag of the data D1 sent by the memory, it can determine that the compression rate corresponding to the data D1 is greater than 1. In this case, the memory controller 110 can further determine the compression rate corresponding to the data D1. If the memory controller 110 does not receive the compression mark of the data D1 sent by the memory, it can be determined that the compression rate corresponding to the data D1 is equal to 1. In this case, the memory controller 110 can directly execute step 212, and the data sent by the memory 120 D1 is sent to the processor 200 .
  • the memory 120 may send the compression mark to the memory controller 110 through a DQ channel.
  • the indication information of the burst length D11 may specifically be the compression rate corresponding to the data D1.
  • the memory controller 110 can obtain the compression rate corresponding to the data D1 after receiving the indication information of the burst length D11 sent by the memory 120 .
  • the indication information of the burst length D11 may specifically be identification information of the burst length D11.
  • the memory controller 110 may determine the burst length D11 corresponding to the data D1 according to the identification information of the burst length D11, and determine the data volume of the data D1 received by the memory controller 110 from the memory 120 according to the burst length D11. Then, the compression rate corresponding to the data D1 may be determined according to the data volume of the original data corresponding to the data D1 and the data volume of the data D1 received by the memory controller 110 from the memory 120 .
  • the memory controller 110 may include a compression module.
  • the compression module can decompress the data D1 according to the compression rate corresponding to the data D1, and send the decompressed data D1 to the processor 200 through step 212 .
  • the memory controller 110 may send the compression ratio corresponding to the data D1 and the data D1 to the processor 200 or the device B1, and then the processor 200 Or the device B1 decompresses the data D1 according to the compression rate corresponding to the data D1.
  • the address information included in the read command RC1 specifically indicates an address in the storage space D12, and the address is a partial address among the multiple addresses corresponding to the storage space D12. This may indicate that, compared with data corresponding to other addresses in the storage space D12, the processor 200 needs the data corresponding to the address indicated by the address information in the read command first.
  • the address information included in the setting read command RC1 specifically indicates the address C3. Then, if the compression rate corresponding to the data D1 is 1, the data corresponding to the address C3 may be the data that the processor 200 needs first.
  • the memory 120 When the memory 120 reads the command RC1 and sends the data D1 to the memory controller, it first sends the data corresponding to the address C3 to the memory controller 110, and then sends the address C4, address C5, address C6, address C7, address Data corresponding to C0, address C1, and address C2.
  • the number of cycles corresponding to the burst length D11 is d1 for burst transmission, that is, sending data D1 according to the burst length D11 refers to sending data D1 using d1 cycles of continuous transmission.
  • sending the data corresponding to the address C3 to the memory controller 110 may specifically be that the memory 120 may use the first cycle of the d1 cycles to transmit or send the data corresponding to the address C3.
  • the data corresponding to the address C4, the address C5, the address C6, the address C7, the address C0, the address C1, and the address C2 are transmitted or sent in other cycles of the d1 cycles.
  • the processor 200 may send multiple read commands including the read command RC1 to the memory controller 110.
  • the memory controller 110 may buffer the plurality of read commands into a command cache. Because the memory controller 110 does not know the burst length corresponding to the data to be read by these read commands, in order to ensure the seamless transmission of data in the read direction and improve the data transmission efficiency in the read direction, the memory controller 110 can send commands in advance (commands issued in advance) mode, a read command is generated to the memory 120 to improve the efficiency of the read direction.
  • commands in advance commands issued in advance
  • Sending commands in advance can also be called CMD Pull-in, which refers to sending N commands in sequence according to the minimum time interval of command sending, where N is an integer greater than or equal to 1, which reduces the time for the command executor to wait for the command, thereby improving the command efficiency. effectiveness.
  • the memory controller 110 may first determine the minimum time interval T2 for sending the read command. Specifically, the memory controller 110 may determine the minimum time interval T2 according to the minimum burst length among various burst lengths. Wherein, the various burst lengths refer to the various burst lengths supported by the memory controller 110 and the memory 120 mentioned above.
  • the minimum burst length among various burst lengths can be set as the burst length E1, and the minimum time interval T2 is not greater than the sending time interval of the read command corresponding to the burst length E1.
  • the sending time interval of the read command corresponding to the burst length E1 refers to the time interval that the memory controller 110 should take to send the read command when the memory 120 sends data to the memory controller 110 according to the burst length E1.
  • the minimum time interval T2 is equal to the sending time interval of the read command corresponding to the burst length E1.
  • the burst length corresponding to the data to be read by the read command is the burst length E1, and the read command is sent accordingly.
  • the minimum time interval T2 is greater than the sending time interval of the read command corresponding to the burst length E1 and smaller than the sending time interval of the read command corresponding to the burst length E2.
  • the burst length E2 is a burst length other than the burst length E1 among the various burst lengths.
  • the minimum time interval T2 is determined in the manner described above.
  • the memory controller 110 may sequentially send N read commands to the memory 120 according to the time interval T2.
  • N may be a preset value, such as 2, 3 or 4, and so on.
  • the size of the command cache in memory 120 may be considered when setting the value of N.
  • the read commands received by the memory 120 can be cached in the command cache first, therefore, the size of the command cache determines the read commands that the memory 120 can cache. Therefore, when setting the value of N, the size of the command cache in the memory 120 may be considered to avoid loss of read commands.
  • the value of N may be determined according to the maximum number of read commands that can be cached simultaneously by the command cache in the memory 120 .
  • the command cache can cache at most M read commands at the same time, and the value of N can be determined according to the value of M.
  • the value of N can be set equal to the value of M.
  • the value of N may be set to be smaller than the value of M, and the difference between the value of N and the value of M is Q, where Q is an integer greater than or equal to 1.
  • the embodiment of the present application adopts the mechanism of sending the read command in advance, which can send at least one read command to the memory as soon as possible, reducing or avoiding the problem of low data sending efficiency caused by the memory waiting for the read command, and improving the bandwidth utilization of the memory interface Rate.
  • a fixed burst length that is, BL8
  • the memory controller can send the read command to the memory according to the sending time interval of the read command corresponding to BL8.
  • the memory receives the read command, executes the read command, and returns data to the memory controller according to BL8.
  • the minimum burst length among the various burst lengths supported by the memory controller 110 and the memory 120 can be set as BL2, and the minimum sending time interval T2 of the read command can be determined by BL2 , sending N read commands first, so that the memory 120 can obtain the read commands in time, and then execute the read commands, which ensures the seamless transmission of data and improves the bandwidth utilization rate of the memory interface.
  • the memory controller 110 may also determine the number of read commands used to send the read command again according to the indication information of the burst length received from the memory 120. Time interval T3.
  • the memory 120 can execute any read command among the at least one read command received, read corresponding data and The indication information of the corresponding burst length. Then, the memory 120 can send the indication information and data of the read burst length to the memory controller 110.
  • the memory 120 can send the indication information and data of the read burst length to the memory controller 110.
  • the memory 120 can read the data D2 and the indication information of the burst length E2 according to the read command RC2 in the received at least one read command, and send the indication information of the burst length E2 to the memory controller 110, and according to the burst length
  • the burst length E2 is used to send the data D2 to the memory controller 110 .
  • the memory controller 110 may determine the time interval T3 for sending the read command again according to the burst length E3.
  • the memory controller 110 can determine whether the burst length E3 and the burst length E1 are the same burst length, that is, determine whether the burst length E3 is one of the various burst lengths supported by the memory controller 110 and the memory 120. Minimum burst length. If the burst length E3 and the burst length E1 are the same burst length, then the memory controller 110 can take out the unsent read command from the command buffer of the memory controller 110 according to the minimum time interval T2 again, and send it to the memory 120 Send fetched read command. If the burst length E3 is different from the burst length E1, the memory controller 110 may determine the time interval T3 according to the burst length E3.
  • the time interval T3 is equal to the sending time interval of the read command corresponding to the burst length E3.
  • the sending time interval of the read command corresponding to the burst length E3 refers to the sending time interval of the read command when the burst length E3 is used for data transmission.
  • the memory controller 110 may fetch unsent read commands from the command cache of the memory controller 110 according to the time interval T3, and send the fetched read commands to the memory 120 .
  • the time interval between the time when the memory controller 110 sends the fetched read command and the last read command sent among the N read commands is the time interval T3.
  • the read data cache in the memory controller 110 may be used to cache the indication information of the burst length E3 sent by the memory 120 . Then, the burst length determining module in the memory controller 110 may fetch the indication information of the burst length E3 from the read data cache, and determine the burst length E3 according to the indication information of the burst length E3.
  • the determined burst length E3 is used to determine the time interval T3, therefore, the burst length determination module in the memory controller 110 takes out the indication information of the burst length E3 from the read data cache, and according to the indication information of the burst length E3 , the process of determining the burst length E3 can be understood or called back pressure, that is, to adjust the speed at which the memory controller sends read commands to the memory when data is sent from the memory to the memory controller.
  • the time interval for sending the read command again can be re-determined, so that the sending speed of the read command matches the execution speed of the read command, so that the While ensuring that the memory seamlessly sends data to the memory controller, there is no need to send too many read commands to the memory, reducing the pressure on memory cache read commands.
  • the data path in memory 120 may backpressure the command cache. Specifically, when the data path is executing a data reading or data writing task, it may refuse to execute the reading command or writing command in the command cache, thereby ensuring the orderly execution of the data reading or data writing operation.
  • back pressure For the specific process of back pressure, reference may be made to the introduction of the prior art, which will not be repeated here.
  • the data storage solution provided by the embodiment of the present application can improve the utilization rate of the bandwidth of the memory interface in the writing direction, and can also improve the utilization rate of the bandwidth of the memory interface in the reading direction. Among them, when the FPC algorithm is used for the simulation test, the utilization rate of the memory bandwidth can be increased by about 50%. Moreover, the data storage solution provided by the embodiment of the present application can directly store compressed data when storing data in the storage space, which saves memory storage resources.
  • an embodiment of the present application provides a data storage method applied to a storage device including a memory controller and a first memory, where the first memory includes at least one storage space. As shown in Figure 5, the method includes the following steps.
  • step 501 the memory controller determines a first burst length for transmitting the first data from various burst lengths according to the data amount of the first data. For details, reference may be made to the above introduction to step 202 in FIG. 2 .
  • Step 502 the memory controller sends the first indication information of the first burst length to the first memory, and sends the first data to the first memory according to the first burst length.
  • the memory controller sends the first indication information of the first burst length to the first memory, and sends the first data to the first memory according to the first burst length.
  • Step 503 the first memory receives the first data according to the first burst length according to the first indication information.
  • the first indication information For details, reference may be made to the above introduction to step 205 in FIG. 2 .
  • Step 504 the first memory stores the first data in a first storage space of the at least one storage space.
  • the first storage space of the at least one storage space.
  • the first indication information includes a first compression rate
  • the first data is obtained by compressing the original data of a preset size according to the first compression rate, and the first compressed The rate corresponds to the first burst length; or, the first indication information includes identification information representing the first burst length.
  • the method further includes: the memory controller determining a first time interval for sending a read command according to a second burst length; The minimum sending length; the memory controller sequentially sends N read commands to the first memory according to the first time interval, where N is an integer greater than or equal to 1.
  • the first time interval is not greater than the sending time interval of read commands of the second burst length.
  • the method further includes: the memory controller receiving the second indication information of the third burst length sent by the first memory, wherein the first memory is configured according to the third burst length Sending second data to the memory controller, the second data corresponding to the first read command in the N read commands; when the third burst length is different from the second burst length, The memory controller determines a second time interval according to the third burst length; the memory controller sequentially sends multiple second read commands to the first memory according to the second time interval, and the The interval between the sending times of multiple second read commands and the sending times of the third read commands is the second time interval, and the third read commands are sent by the memory controller after sending the N read commands the read command.
  • the first data is obtained by compressing the original data, and the data volume of the original data is not greater than the data volume that can be transmitted by a fourth burst length, and the fourth burst length The largest of the various burst lengths.
  • the memory controller sending the first indication information of the first burst length to the first memory includes: the memory controller sending a first write command to the first memory, the The first write command carries the first indication information.
  • the method further includes: the memory controller determining the time interval between the sending moment of the first write command and the sending moment of the second write command according to the first burst length; wherein, the The first write command is used to indicate the address of the first storage space; the second write command is used to indicate the address of the second storage space in the at least one storage space; wherein, the second storage space uses storing the third data, the third data is the data sent by the memory controller to the first memory after the sending of the first data is completed.
  • the method further includes: the memory controller sending a third read command to the first memory, the third read command includes a first address, and the first address corresponds to the third memory space Part of the multiple addresses of ;
  • the memory controller In response to the third read command, the memory controller first sends data corresponding to the first address to the memory controller, and then sends data corresponding to other addresses among the multiple addresses to the memory controller .
  • the first storage space is also used to store the first indication information; the method further includes: the memory controller sends a fourth read command to the first memory, and the fourth read The command includes the address of the first storage space; the first memory reads the first data and the first instruction information according to the address of the first storage space; The controller sends the first indication information, and sends the first data to the memory controller according to the first burst length; the memory controller according to the first indication information, according to the first The burst length is used to receive the first data.
  • the data storage method provided by the embodiment of the present application can improve the utilization rate of the bandwidth of the memory interface in the writing direction, and can also improve the utilization rate of the bandwidth of the memory interface in the reading direction. Among them, when the FPC algorithm is used for the simulation test, the utilization rate of the memory bandwidth can be increased by about 50%. Moreover, the data storage device provided by the embodiment of the present application can directly store compressed data when storing data in the storage space, which saves memory storage resources.
  • the embodiment of the present application also provides a data storage device 600, including a memory controller 610 and a memory 620, and the memory 620 includes at least one storage space, wherein,
  • the memory controller 610 is configured to determine a first burst length for transmitting the first data from various burst lengths according to the data amount of the first data; for details, refer to the above description of step 202 in FIG. 2 .
  • the memory controller 610 is configured to send first indication information of the first burst length to the memory 620 , and send first data to the memory 620 according to the first burst length.
  • first indication information of the first burst length to the memory 620
  • first data to the memory 620 according to the first burst length.
  • the memory 620 is configured to receive the first data according to the first burst length according to the first indication information. For details, reference may be made to the above introduction to step 205 in FIG. 2 .
  • the memory 620 is configured to store the first data in a first storage space of the at least one storage space. For details, reference may be made to the above introduction to step 206 in FIG. 2 .
  • the first indication information includes a first compression rate
  • the first data is obtained by compressing the original data of a preset size according to the first compression rate, and the first compressed The rate corresponds to the first burst length; or, the first indication information includes identification information representing the first burst length.
  • the memory controller 610 is further configured to determine the first time interval for sending the read command according to the second burst length; wherein the second burst length is among the various burst lengths Minimum; the memory controller 610 is further configured to sequentially send N read commands to the memory 620 according to the first time interval, where N is an integer greater than or equal to 1.
  • the first time interval is not greater than the sending time interval of read commands of the second burst length.
  • the memory controller 610 is further configured to receive the second indication information of the third burst length sent by the memory 620, wherein the memory 620 sends the second data to the memory controller 610 according to the third burst length , the second data corresponds to the first read command in the N read commands; when the third burst length is different from the second burst length, the memory controller 610 is further configured to The third burst length determines the second time interval; the memory controller 610 is further configured to sequentially send multiple second read commands to the memory 620 according to the second time interval.
  • the multiple second read commands are read commands sent by the memory controller after sending the N read commands.
  • the first data is obtained by compressing the original data, and the data volume of the original data is not greater than the data volume that can be transmitted by a fourth burst length, and the fourth burst length The largest of the various burst lengths.
  • the memory controller 610 is further configured to send a first write command to the memory 620, where the first write command carries the first indication information.
  • the memory controller 610 is further configured to determine the time interval between the sending moment of the first write command and the sending moment of the second write command according to the first burst length; wherein, the first The write command is used to indicate the address of the first storage space; the second write command is used to indicate the address of the second storage space in the at least one storage space; wherein, the second storage space is used to store the first Three data, the third data is the data that the memory controller 610 sends to the memory 620 after the sending of the first data is completed.
  • the memory controller 610 is further configured to send a third read command to the memory 620, the third read command includes a first address, and the first address is one of multiple addresses corresponding to the third storage space partial address;
  • the memory controller 610 is further configured to, in response to the third read command, first send data corresponding to the first address to the memory controller 610, and then send data corresponding to other addresses among the multiple addresses to the memory controller 610 .
  • the first storage space is also used to store the first indication information; the memory controller 610 is also used to send a fourth read command to the memory 620, the fourth read command includes the first The address of the storage space; the memory 620 is also used to read the first data and the first indication information according to the address of the first storage space; the memory 620 is also used to send the first data to the memory controller 610 indication information, and send the first data to the memory controller 610 according to the first burst length; the memory controller 610 is further configured to receive the first data according to the first burst length according to the first indication information Describe the first data.
  • the functions of the memory controller 610 and the memory 620 can be implemented with reference to the method embodiment shown in FIG. 2 above, and details are not repeated here.
  • the data storage device provided by the embodiment of the present application can increase the utilization rate of the bandwidth of the memory interface in the writing direction, and can also improve the utilization rate of the bandwidth of the memory interface in the reading direction. Among them, when the FPC algorithm is used for the simulation test, the utilization rate of the memory bandwidth can be increased by about 50%. Moreover, the data storage device provided by the embodiment of the present application can directly store compressed data when storing data in the storage space, which saves memory storage resources.
  • the computing device includes a processor 700 and a storage device 6500 .
  • the functions of the processor 700 may be implemented with reference to the introduction of the processor 200 above.
  • the term "and/or" is only an association relationship describing associated objects, indicating that there may be three relationships, for example, A and/or B may indicate: A exists alone, A exists alone There is B, and there are three cases of A and B at the same time.
  • the term "plurality" means two or more. For example, multiple systems refer to two or more systems, and multiple terminals refer to two or more terminals.
  • first and second are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • the terms “including”, “comprising”, “having” and variations thereof mean “including but not limited to”, unless specifically stated otherwise.

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Abstract

一种数据存储方法、存储装置及设备，涉及数据处理技术领域。其中，该方法包括：内存控制器根据第一数据的数据量，从多种突发长度中确定用于传输第一数据的第一突发长度（501）；内存控制器向第一内存发送第一突发长度的第一指示信息，以及按照第一突发长度向第一内存发送第一数据（502）；第一内存根据所述第一指示信息，按照第一突发长度，接收第一数据（503）；第一内存将第一数据存储到至少一个存储空间中的第一存储空间（504）。该方法可以提高内存接口带宽的利用率。

Description

一种数据存储方法、存储装置及设备 技术领域
本申请涉及数据处理技术领域，具体涉及一种数据存储方法、存储装置及设备。
背景技术
内存(memory，MEM)，也称为内部存储器，其是计算机的重要部件，用于暂时存放中央处理器(central processing unit，CPU)的运算数据，以及与硬盘等外部存储器交换数据。
处理器的发展速度远大于内存的发展，其中，计算机处理器中的计算核心(core)数量的年增长速率可达到50％，相对而言，内存接口的带宽(bandwidth)和延迟(latency)减小的速度慢了很多。因此，内存成为了制约计算机数据处理能力的一个关键因素。
信息技术(information technology，IT)的发展，对计算机的数据处理能力要求越来越高。特别是，在大数据分析等计算密集的场景中，需要实时处理大量的数据，对内存访问压力很大。
发明内容
本申请实施例提供了一种数据存储方法、存储装置及设备，可以提高内存接口带宽的利用率。
第一方面，提供了一种数据存储方法，该方法可应用于存储装置，该存储装置包括内存控制器和第一内存，第一内存包括至少一个存储空间。其中，该方法包括：内存控制器根据第一数据的数据量，从多种突发长度中确定用于传输第一数据的第一突发长度；内存控制器向第一内存发送第一突发长度的第一指示信息，以及按照第一突发长度向第一内存发送第一数据；第一内存根据所述第一指示信息，按照第一突发长度，接收第一数据；第一内存将第一数据存储到至少一个存储空间中的第一存储空间。
突发长度是指内存控制器向第一内存发送第一数据时，所需要的数据传输次数。例如，当突发长度为2时，那么内存控制器通过两次数据传输，将第一数据发送至第一内存。再例如，当突发长度为4时，那么内存控制器通过4次数据传输，将第一数据发送至第一内存。由于，每次数据传输所传输的数据量相同，因此，不同的突发长度可以传输不同的数据量，换言之，不同的数据量对应不同的突发长度。并且，突发长度越大，可以传输的数据量越大，换言之，越大的数据量对应越大的突发长度。
在一种方案中，内存控制器和内存支持的突发长度固定，在对数据进行压缩，需要将数据压缩到对应固定突发长度的数据量，如此，压缩后的数据才能被传输至内存。当数据不能被压缩到对应固定长度的数据量时，则该数据不可被压缩(压缩后的数据量对应不上突发长度，无法被传输)，从而导致很多类型的数据不能被压缩，内存接口带宽的利用率较低。
在本申请的提供的方法中，内存控制器和第一内存支持多种突发长度，即可以按照多种突发长度，进行数据传输。在需要向第一内存发送第一数据时，可以根据第一数据的数据量，从多种突发长度中选择与第一数据的数据量匹配的第一突发长度，并按照第一突发长度向第一内存发送待发送的第一数据。由此，在将第一数据的原始数据压缩为第一数据时，无需过多考虑压缩后的数据与突发长度对应不上的情况，从而可以更自由地对第一数据进行压缩， 进而可以提高内存接口带宽的利用率。并且，内存控制器可以将用于传输第一数据的第一突发长度通知给第一内存，使得第一内存获知内存控制器是按照第一突发长度发送第一数据的，从而可以在内存控制器和第一内存之间的突发长度可变的情况下，正确接收到第一数据，以完成第一数据的存储。
在一种可能的实现方式中，第一指示信息包括第一压缩率，第一数据是按照第一压缩率对预设大小的原始数据进行压缩后得到的，且第一压缩率对应第一突发长度；或者，第一指示信息包括用于代表第一突发长度的标识信息。
也就是说，在该实现方式中，可以建立压缩率和突发长度的对应关系，进而可以通过将压缩率通知给第一内存，实现突发长度的通知；或者，可以直接将突发长的标识信息通知给第一内存，实现突发长度的通知。
在一种可能的实现方式中，内存控制器根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，第二突发长度在多种突发长度中最小；内存控制器根据第一时间间隔，依次向第一内存发送N个读命令，N为大于或等于1的整数。
一个读命令可以触发第一内存执行一次突发传输。可以理解，采用越小的突发长度进行突发传输(即突发传输中数据传输次数越少)，那么两次突发传输之间的时间间隔越短。内存控制器在首次发送读命令时，不知第一内存将要采用多大突发长度的突发传输，向内存控制器发送数据。若内存控制器向第一内存发送读命令的时间大于第一内存进行相邻两次突发传输的时间间隔，那么第一内存在执行完前一个突发传输时，需要等待读命令的到来，才能执行后一个突发传输。如此，降低了数据读取的效率。
在该实现方式中，内存控制器可以按照多种突发长度中的最小突发长度，确定内存控制器向第一内存发送读命令的时间间隔，(即内存控制器假设了第一内存采用最小突发长度的突发传输，向内存控制器发送数据，并据此确定读命令发送时间间隔)从而可以减少或者避免第一内存因等待读命令而导致的数据发送不连续，从而提高了内存接口在读方向上的利用率。
在一种可能的实现方式中，第一时间间隔不大于第二突发长度的读命令的发送时间间隔。
如上所述，第二突发长度为多种突发长度中的最小突发长度，采用第二突发长度的突发传输持续时间较短。若第一内存按照第二突发长度向内存控制器发送数据(即第一内存按照第二突发长度返回数据)，则需要内存控制器按照较短的时间间隔来发送读命令，以保证第一内存可以及时获取读命令，进而响应读命令，向内存控制器发送数据，才能实现数据的连续发送。
在该实现方式中，内存控制器向第一内存发送读命令的时间间隔不大于按照第二突发长度返回数据时的读命令应有的读命令发送时间间隔，从而在第一内存按照第二突发长度向内存控制器发送数据时，可以保证第一内存及时获取读命令，进而可以避免在第一内存按照第二突发长度向内存控制器发送数据的情况下，因等待读命令而导致的数据发送不连续，由此，提高了内存接口在读方向上的利用率。
在一种可能的实现方式中，内存控制器接收第一内存发送的第三突发长度的第二指示信息，其中，第一内存按照第三突发长度向内存控制器发送第二数据，第二数据对应于N个读命令中的第一读命令；当第三突发长度和第二突发长度不同时，内存控制器根据第三突发长度，确定用第二时间间隔；内存控制器根据第二时间间隔，依次向第一内存发送多个第二读命令，多个第二读命令是内存控制器在发送述N个读命令之后发送的读命令。
也就是说，在该实现方式中，第一内存可以将其向内存控制器返回数据所采用的突发长度，通知给内存控制器，内存控制器可以根据该突发长度，调整向第一内存再次发送读命令 时的时间间隔，提高读命令的发送时间间隔和读命令的执行时间间隔的一致性，从而在保障第一内存无缝向内存控制器发送数据的同时，无需一直按照较小的读命令发送时间间隔，向第一内存发送读命令，避免了短时间内向第一内存发送过多的读命令，导致读命令来不及被执行，引发第一内存缓存读命令的压力过大这一问题。
在一种可能的实现方式中，第一数据是对原始数据进行压缩后得到的，原始数据的数据量不大于一次第四突发长度所能传输的数据量，第四突发长度在多种突发长度中最大。
也就是说，在该实现方式中，第一数据被压缩前的数据量不大于多种突发长度中最大突发传输所能传输的数据量，保证了第一数据的数据量不大于该最大突发长度所能传输的数据量，从而保证了内存控制器通过一次突发传输，就可以将第一数据完整的发送至第一内存，尽量减少了内存接口在写方向上的时延，提高了内存接口的利用率。
在一种可能的实现方式中，内存控制器向第一内存发送第一突发长度的第一指示信息包括：内存控制器向第一内存发送第一写命令，第一写命令携带有第一指示信息。
也就是说，在该实现方式中，内存控制器可以将突发长度的指示信息携带在写命令中，在向第一内存发送写命令的同时，也实现向第一内存发送突发长度的指示信息，进一步节省了内存接口的带宽，提高了内存接口带宽的利用率。
在一种可能的实现方式中，该方法还包括：内存控制器根据第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，第一写命令用于指示第一存储空间的地址；第二写命令用于指示至少一个存储空间中的第二存储空间的地址；其中，第二存储空间用于存储第三数据，第三数据是内存控制器在第一数据发送完成后，接着向第一内存发送的数据。
也就是说，在该实现方式中，内存控制器可以根据本次数据传输采用的突发长度，确定下一个写命令的发送时间，从而可以在本次数据传输的突发长度较小时或者说本次数据传输所占据的时间较短时，尽快将下一个写命令发送至第一内存，从而可以尽快触发下一次的数据传输，保障了数据的无缝传输，提高了内存接口的利用率。
在一种可能的实现方式中，内存控制器向第一内存发送第三读命令，第三读命令包括第一地址，第一地址是第三存储空间对应的多个地址中的部分地址；内存控制器响应于第四读命令，先向内存控制器发送第一地址对应的数据，随后向内存控制器发送多个地址中其他地址对应的数据。
可以理解，通常而言，读命令中的地址对应的数据可能是读命令的发起者(例如处理器)优先需要的数据。在该实现方式中，第一内存可以向内存控制器优先发送读命令中的地址对应的数据，进而使得内存控制器可以向读命令的发起者优先发送该数据，从而使得该数据可以尽快被发送到读命令的发起者，改善了存储装置的性能。
在一种可能的实现方式中，第一存储空间还用于存储第一指示信息；该方法还包括：内存控制器向第一内存发送第四读命令，第四读命令包括第一存储空间的地址；第一内存根据第一存储空间的地址，读取第一数据和第一指示信息；第一内存向内存控制器发送第一指示信息，以及按照第一突发长度向内存控制器发送第一数据；内存控制器根据第一指示信息，按照第一突发长度，接收第一数据。
也就是说，在该实现方式中，第一内存可以将第一指示信息和第一数据存储到同一存储空间，由此，第一内存在响应读命令，从存储空间中读取第一数据时，也可以读取到第一指示信息，从而可以根据第一指示信息，尽快确定出第一突发长度，进而可以按照第一突发长度，向内存控制器返回第一数据，提高了数据返回的效率以及内存接口利用率。并且，第一 内存可以将第一指示信息发送至内存控制器，使得内存控制器获知第一内存是按照第一突发长度发送第一数据的，从而可以在内存控制器和第一内存之间的突发长度可变的情况下，正确接收到第一数据，进而可以完成第一数据的读取。
在一种可能的实现方式中，该方法还包括：内存控制器根据第一指示信息，解压缩第一数据。具体而言，内存控制器可以根据第一指示信息，确定第一内存按照第一突发长度发送第一数据，然后，可以根据第一突发长度，确定第一数据对应的压缩率，并对第一数据进行解压缩。
在一种可能的实现方式中，第一数据是按照第一压缩率对预设大小的原始数据进行压缩后得到的；其中，第一压缩率由原始数据的数据类型和将原始数据压缩为第一数据的压缩算法确定。
也就是说，在该实现方式中，可以不必拘泥于固定的突发长度，可以按照由原始数据的数据类型和压缩算法确定的压缩率，对第一数据进行压缩。
第二方面，提供了一种数据存储装置，包括内存控制器和第一内存，第一内存包括至少一个存储空间，其中，内存控制器用于根据第一数据的数据量，从多种突发长度中确定用于传输第一数据的第一突发长度；内存控制器用于向第一内存发送第一突发长度的第一指示信息，以及按照第一突发长度向第一内存发送第一数据；第一内存用于根据第一指示信息，按照第一突发长度，接收第一数据；第一内存用于将第一数据存储到至少一个存储空间中的第一存储空间。
在一种可能的实现方式中，第一指示信息包括第一压缩率，第一数据是按照第一压缩率对预设大小的原始数据进行压缩后得到的，且第一压缩率对应第一突发长度；或者，第一指示信息包括用于代表第一突发长度的标识信息。
在一种可能的实现方式中，内存控制器还用于根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，第二突发长度在多种突发长度中最小；内存控制器还用于根据第一时间间隔，依次向第一内存发送N个读命令，N为大于或等于1的整数。
在一种可能的实现方式中，第一时间间隔不大于第二突发长度的读命令的发送时间间隔。
在一种可能的实现方式中，内存控制器还用于接收第一内存发送的第三突发长度的第二指示信息，其中，第一内存按照第三突发长度向内存控制器发送第二数据，第二数据对应于N个读命令中的第一读命令；当第三突发长度和第二突发长度不同时，内存控制器还用于根据第三突发长度，确定第二时间间隔；内存控制器还用于根据第二时间间隔，依次向第一内存发送多个第二读命令，多个第二读命令是内存控制器在发送完N个读命令之后发送的读命令。
在一种可能的实现方式中，第一数据是对原始数据进行压缩后得到的，原始数据的数据量不大于一次第四突发长度所能传输的数据量，第四突发长度在多种突发长度中最大。
在一种可能的实现方式中，内存控制器还用于向第一内存发送第一写命令，第一写命令携带有第一指示信息。
在一种可能的实现方式中，内存控制器还用于根据第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，第一写命令用于指示第一存储空间的地址；第二写命令用于指示至少一个存储空间中的第二存储空间的地址；其中，第二存储空间用于存储第三数据，第三数据是内存控制器在第一数据发送完成后，接着向第一内存发送的数据。
在一种可能的实现方式中，内存控制器还用于向第一内存发送第三读命令，第三读命令 包括第一地址，第一地址是第三存储空间对应的多个地址中的部分地址；内存控制器还用于响应于第三读命令，先向内存控制器发送第一地址对应的数据，随后向内存控制器发送多个地址中其他地址对应的数据。
在一种可能的实现方式中，第一存储空间还用于存储第一指示信息；内存控制器还用于向第一内存发送第四读命令，第四读命令包括第一存储空间的地址；第一内存还用于根据第一存储空间的地址，读取第一数据和第一指示信息；第一内存还用于向内存控制器发送第一指示信息，以及按照第一突发长度向内存控制器发送第一数据；内存控制器还用于根据第一指示信息，按照第一突发长度，接收第一数据。
第三方面，提供了一种计算设备，包括：处理器和第一方面所提供的存储装置。
在本申请实施例提供的方案中，内存控制器在需要向内存发送数据时，可以根据数据的数据量，从多种突发长度中选择与数据的数据量匹配的突发长度，并按照该突发长度向内存发送待发送该数据。由此，在对该数据进行压缩时，不必拘泥于固定的突发长度，可以更自由地对该数据进行压缩，进而可以提高内存接口带宽的利用率。并且，内存控制器可以将用于传输该数据的突发长度通知给内存，使得内存获知内存控制器是按照突发长度发送数据的，从而可以在内存控制器和内存之间的突发长度可变的情况下，正确接收到数据，以完成数据的存储。
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图1为本申请实施例提供的数据存储方案可应用的一种架构的示意图；
图2为本申请实施例提供的数据存储方案的流程图；
图3为本申请实施例提高内存接口利用率的示意图；
图4为本申请实施例提高内存接口利用率的示意图；
图5为本申请实施例提供的一种数据存储方法的流程图；
图6为本申请实施例提供的一种存储装置的示意性框图；
图7为本申请实施例提供的一种计算设备的示意性框图。
具体实施方式
下面将结合附图，对本发明实施例中的技术方案进行描述。显然，所描述的实施例仅是本说明书一部分实施例，而不是全部的实施例。
内存接口是数据进出内存的通道。内存控制器(memory controller,MC)可以用于管理进出内存的数据。具体而言，当处理器(例如CPU)需要将数据存储到内存中时，内存控制器可以通过内存接口，将该数据发送至内存。当处理器需要读取内存中存储的数据时，内存可以将数据通过内存接口发送至内存控制器，再由内存控制器将数据发送至处理器。因此，内存接口的带宽对处理器调用数据的速度至关重要。
内存控制器和内存之间可以通过突发(burst)传输，进行数据传输。突发传输是指：在同一行中相邻的存储单元连续进行数据传输的方式。其中，一次突发传输中可以包括连续进行的多次数据传输，其中，该多次数据传输的具体次数可以称为突发长度(burst lengths，BL)。举例而言，可以设定一个突发传输的突发长度为8，即BL为8(可以简称为BL8)，那么该突发传输包括8次数据传输，该8次数据传输可以连续进行，即在8次数据传输的执行期间，无需在为每次的数据传输提供列地址。具体而言，采用突发传输进行数据传输时，在指定存储列阵中存储单元的行地址后，只要指定存储单元的起始列地址与突发长度，内存就会依次地自动对后面相应数量的存储单元进行读/写操作，而无需内存控制器连续地提供列地址。
在一种方案A中，内存接口支持的突发长度为8(BL8)，即内存控制器和内存之间通过BL8进行突发传输，每一次的突发传输包括8个周期的连续传输。一般而言，BL8最多可以传输64字节(byte，B)的数据量。并且在方案A中，采用128B的粒度，进行数据压缩，即将原始数据按照128B的大小进行划分，然后，对数据量为128的原始数据进行压缩。由于该方案的内存接口仅支持BL8，所以支持的压缩率为2：1。可以理解，压缩率是由原始数据和采用的压缩算法共同确定。在该方案中，当原始数据和压缩算法确定的压缩率刚好是2：1时，则可以对该原始数据进行压缩。若确定的压缩率不是2：1，而是其他大小的压缩率(例如3：1)，则认为该原始数据不可压缩，进而不对该原始数据进行原始压缩。简而言之，在方案A中，128B的原始数据最多可被压缩为2：1，或者不被压缩(例如，当)。因此，方案A对内存接口带宽的利用率提升有限。
本申请实施例提供了一种数据存储方案，内存接口可以支持多种突发长度，内存控制器在向内存发送数据时，内存控制器可以根据待发送数据的数据量，从多种突发长度中选择突发长度，并使用选择的突发长度向内存发送该待发送数据，以及将选择的突发长度的指示信息发送至内存。内存可以按照该指示信息指示的突发长度，接收内存控制器发送的数据，以实现数据的正确接收。
在本申请实施例提供的数据存储方案中，可以根据待发送数据的数据量选择相应的突发长度，由此，在对待发送数据进行压缩时，不受限于突发长度，可以根据由待发送数据的数据类型和压缩算法所确定的压缩率，对待发送数据进行压缩，以降低压缩后数据的数据量。然后，可以使用与压缩后数据匹配的突发长度，发送压缩后数据。从而可以最大限度的提高内存接口带宽利用率。
接下来，对本申请实施例提供的数据存储方案进行说明。
图1示出了本申请实施例提供的数据存储方案可应用的一种架构，该架构包括存储装置100和处理器200。其中，存储装置100可以包括内存控制器110和内存120。
内存120可以为一个独立的存储器，也可以为多个存储器构成的存储器集群。在一个例子中，内存120可以为随机存取存储器(random access memory，RAM)或者其他主存储器(main memory)。本申请实施例对内存120的实现形式不做具体限定。
内存120和处理器200进行数据交换。具体而言，内存120可以用于存储数据，可使得处理器200将数据写入到内存120中，以及内存120中存储的数据可供处理器200读取或者说调用。
内存控制器100可以用于管理内存120和处理器200之间数据交换。具体而言，当处理器200需要将数据存储到内存中时，处理器200可以先将该数据和写命令发送至内存控制器110，然后内存控制器110将该数据和写命令发送至内存120。内存120可以响应该写命令，将该数据存储到相应的存储空间中。当处理器200需要读取内存120中存储的数据时，处理器200可以将读命令发送至内存控制器110，然后，内存控制器110可以将该读命令发送至内存120。内存120可以响应该读命令，将相应数据发送至内存控制器110，再由内存控制器110将数据发送至处理器200。其中，内存控制器110和内存120之间的数据交换将在下文进行具体介绍，在此不再赘述。
在一些实施例中，内存控制器110可以为传统型内存控制器。传统型内存控制器可以位于主板芯片组中的北桥芯片内部。在一些实施例中，内存控制器110可以为集成型内存控制器。其中，集成型内存控制器可以集成到处理器中。换言之，内存控制器110可以集成到处理器200中。
内存控制器110和内存120可以支持多种突发传输，其中，不同的突发传输的突发长度不同，即不同种的突发传输中的连续传输的周期数不同。换而言之，内存控制器110和内存120可以支持多种突发长度，并可以从该多种突发长度中选择任意的突发长度进行突发传输。由此，在对数据进行压缩时，不必拘泥于固定的突发长度，可以按照不同的压缩率对数据进行压缩，从而可以提高内存接口带宽的利用率。内存控制器110和内存120的具体功能将在下文进行介绍，在此不再赘述。
在一些实施例中，处理器200可以为中央处理器。在一些实施例中，处理器200可以为图形处理器(graphics processing unit，GPU)。在一些实施例中，处理器200可以为专用集成电路(application specific integrated circuit，ASIC)。在一些实施例中，处理器200可以为神经网络处理单元(neural-network processing unit，NPU)。在一些实施例中，处理器200还可以为其他形式的具有数据处理能力的装置。本申请不对处理器200的实现形式做具体限定。
在一些实施例中，存储装置100和处理器200可以部署到同一计算设备中。该计算设备可以为服务器、移动终端(例如手机、平板电脑、笔记本电脑)或车载终端等。本申请实施例不对存储装置100和处理器200所在的计算设备的实现形式做具体限定。
在一些实施例中，存储装置100和处理器200也可以分别部署到不同的计算设备中。
上文示例介绍了本申请实施例提供的数据存储方案可应用的架构。接下来，示例介绍该数据存储方案的流程。
图2示出了本申请实施例提供的数据存储方案的流程。如图2所示，处理器200在需要向内存中存储数据时，可以执行步骤200，向内存控制器110发送写命令WC1以及数据D1。内存控制器可以接收写命令WC1以及数据D1。其中，数据D1属于写数据，是需要存储到或者说写入到内存120中的数据。
其中，回到图1，内存控制器110可以包括命令缓存，用于缓存从处理器接收到的写命令，例如写命令WC1。在一个例子中，命令缓存可以为CMD que。内存控制器110也可以包括写数据缓存模块，用于缓存从处理器接收到的数据，例如数据D1。在一个例子中，写数据缓存可以为Wdata que。
继续参阅图2，内存控制器110可以响应写命令WC1，执行步骤202，根据数据D1的数据量，从多种突发长度中确定突发长度D11。其中，该多种突发长度为上文所述的内存控制器110和内存120可支持的多种突发长度。示例性的，回到图1，内存控制器110可包括突发长度确定模块，可以用于执行步骤202。
步骤202具体可以通过如下方式实现。
可以对数据D1进行数据压缩，然后，在步骤202中，内存控制器110可以根据压缩后的数据D1的数据量，从多种突发长度中确定突发长度D11。接下来，进行具体说明。
其中，在一个说明性示例中，对数据D1进行的数据压缩可以由内存控制器110执行。如图1所示，内存控制器110可以包括压缩模块，用于对写数据进行数据压缩。数据压缩模块可以对数据D1，进行数据压缩，得到压缩后的数据D1。具体可以如图1所示，内存控制器可以包括压缩模块，可以用于对内存控制器110接收到的数据进行压缩。在另一个说明性示例中，对数据D1进行的数据压缩可以由处理器200执行。在又一个说明性示例中，对数据D1的数据压缩可以由数据通路上的任意具有数据处理能力的装置B1执行，该数据通路和为处理器200和内存控制器100之间进行数据交互的通路。
可以采用预设的压缩算法(例如，定点连续算法(fixed-point continuation，FPC))， 对数据D1进行压缩。其中，在对数据D1进行数据压缩时，可以按照数据D1的数据类型和压缩算法确定的压缩率，对数据D1进行压缩。具体而言，不必拘泥于固定的突发长度，可以数据D1的数据类型和压缩算法确定出的压缩率对数据D1进行压缩。例如，数据D1的数据类型和压缩算法确定的压缩率为3：1，则可以将数据D1压缩为原来的三分之一大小。再例如，数据D1的数据类型和压缩算法确定的压缩率为4：1，则可以将数据D1压缩为原来的四分之一大小。
其中，需要说明的是，在本申请实施例中，压缩率是指数据压缩前的数据量和数据压缩后的数据量之间的比值，其中，压缩率可以大于1，也可以等于1(即当根据压缩前数据的数据类型和压缩算法确定数据不可压缩时，可以认为根据压缩前数据的数据类型和压缩算法确定出的压缩率为1)。为了方便描述，可以将压缩前的数据可称为原始数据，压缩后的数据可称为压缩数据。其中，即使当根据原始数据的数据类型和压缩算法确定出的压缩率为1时，也可以认为该原始数据经过了1：1压缩，得到了压缩数据，即压缩数据等于原始数据。
在一些实施例中，数据D1的原始数据的数据量不大于数据量阈值。数据量阈值是内存控制器110和内存120之间一次突发传输最多能传输的数据量。具体而言，如上所述，内存控制器110和内存120可以采用的多种突发长度中的任意突发长度进行突发传输。可以理解，当采用该多种突发长度中的最大突发长度进行突发传输时，内存控制器110和内存120之间一次突发传输所能传输的数据量最多。换言之，数据量阈值是内存控制器110和内存120支持的多种突发长度中最多的突发长度所能传输的数据量。举例而言，内存控制器110和内存120支持的BL8(即一次突发传输包括8个周期的连续传输)、BL6(即一次突发传输包括6个周期的连续传输)、BL4(即一次突发传输包括4个周期的连续传输)。其中，BL8最大，当内存控制器110和内存120采用BL8进行突发传输时，所能传输的数据量最大，那么数据量阈值为当内存控制器110和内存120采用BL8进行突发传输时所能传输的数据量。
在这些实施例的一个说明性示例中，当对数据D1的压缩由内存控制器110执行时，若内存控制器从处理器200接收的数据的数据量不大于数据量阈值时，可以将该数据作为数据D1，并对数据D1进行数据压缩处理。若内存控制器从处理器200接收的数据的数据量大于数据量阈值时，可以从该数据中选择数据量不大于数据量阈值的数据D1，并对数据D1进行数据压缩，得到压缩后的数据D1。
在这些实施例的一个说明性示例中，当对数据D1的压缩由处理器200或装置B1执行时，处理器200或装置D1可以从待写入数据中，选择数据量不大于数据量阈值的数据，并进行数据压缩，得到压缩后的数据D1。
通过上述方式，可以得到压缩后的数据D1。接着，在步骤202中，根据压缩后的数据D1的数据量，从多种突发长度中确定突发长度D11。
如上所述，内存控制器110和内存120可以采用的多种突发长度中的任意突发长度，进行突发传输，可以预先设置该多种突发长度中每种突发长度对应的数据量。其中，每种突发长度对应的数据量不大于该突发长度所能传输的数据量。其中，突发长度所能传输的数据量是指采用该突发长度进行突发传输时，所能传输的数据量。
在步骤202中，可以根据压缩后的数据D1的数据量，从多种突发长度中确定对应于该数据量的突发长度，并将确定出的突发长度用作突发长度D11。
在一些实施例中，在对数据进行压缩处理时，原始数据(即压缩前的数据)的数据量大小是一致的，例如都为上述数据量阈值。那么数据压缩时所采用的压缩率和压缩后的数据的数据量是一一对应的。或者说，数据压缩时所采用的压缩率可以代表压缩后的数据的数据量。 因此，预先设置多种突发长度中每种突发长度对应的数据量具体可以为，预先设置多种突发长度中每种突发长度对应的压缩率。由此，在步骤202中，具体可以根据数据D1对应的压缩率(即对数据D1进行数据压缩时，所采用的压缩率)，从多种突发长度中确定突发长度D11。
在这些实施例的一个说明性示例中，当对数据D1的压缩由内存控制器110执行时，内存控制器110可以感知到数据D1对应的压缩率，由此，可以在步骤202中，内存控制器110可以根据数据D1对应的压缩率，确定突发长度D11。
在这些实施例的另一个说明性示例中，当对数据D1的压缩由处理器200或装置B1执行时，处理器200或装置B1可以将数据D1对应的压缩率发送至内存控制器110，使得内存控制器110可以在步骤202中，可以根据数据D1对应的压缩率，确定突发长度D11。
在一些实施例中，在步骤202中，内存控制器110可以确定压缩后的数据D1的数据量，并直接根据压缩后的数据D1的数据量，将多种突发长度中能够承载压缩后的数据D1最小突发长度，确定为突发长度D11。
通过上述方式，内存控制器110可以在步骤202中，确定出突发长度D11。其中，确定出的突发长度D11用于在后续步骤中，向内存120发送数据D1或者说压缩后的数据D1。即内存控制器110将按照突发长度D11，向内存120发送数据D1。由于突发长度D11是内存控制器110从多种突发长度中确定出的，而非固定的突发长度，因此，内存控制器110需要将突发长度D11通知给内存120，以便内存120可以按照突发长度D11接收数据D1或者说压缩后的数据D1，实现数据的正确接收。
接下来，介绍内存控制器110将突发长度D11通知给内存120的实现方式。
继续参阅图2，内存控制器110可以执行步骤203，向内存120发送突发长度D11的指示信息。其中，突发长度D11的指示信息是指可以标识或代表突发长度D11的信息，也可以是指与突发长度D11具有对应关系的信息。当内存120获得突发长度D11的指示信息后，可以确定出突发长度D11。
在一些实施例中，突发长度D11的指示信息可以为数据D1对应的压缩率。当对数据D1的压缩由内存控制器110执行时，内存控制器110可以感知到数据D1对应的压缩率，由此，可以在步骤203中，将数据D1对应的压缩率作为突发长度D11的指示信息发送至内存120。当对数据D1的压缩由处理器200或装置B1执行时，处理器200或装置B1可以将数据D1对应的压缩率发送至内存控制器110，使得内存控制器110可以在步骤203中，将数据D1对应的压缩率作为突发长度D11的指示信息发送至内存120。
在一些实施例中，突发长度D11的指示信息可以为标识或者说代表突发长度的标识信息。可以为内存控制器110和内存120支持的多种突发长度设置标识信息，其中，不同的突发长度的标识信息不同。在一个例子中，标识信息可以是设定的编号，该编号可以由数字和/或字母组成。在另一个例子中，标识信息可以为一段字符串。本申请实施例不对标识信息的形式做具体限定。当内存控制器110从多种突发长度确定出突发长度D11时，可以获得突发长度D11的标识信息，进而在步骤203中，将突发长度D11的标识信息发送至内存120。
可以理解，在内存控制器110需要通过突发传输向内存120发送数据，并指示内存120存储该数据时，即在内存控制器110在通过突发传输执行写操作时，内存控制器110需要将写命令发送至内存120，其中，写命令包括了地址信息。内存120可以将通过突发传输接收的数据存储到地址信息指示的存储空间中。其中，地址信息可以为起始地址，即内存120可以写命令中的地址信息为存储空间的起点地址，并按照预设的存储空间长度，确定用于存储数据的存储空间。因此，在内存控制器110向内存120发送数据D1之前，内存控制器110需要 向内存120发送写命令WC1。例如，如图1所示，内存控制器110可以通过控制信道，向内存控制器110发送写命令WC1。在一个例子中，控制信道具体可以为命令地址(address command，AC)通道。
在一些实施例中，内存控制器120可以将突发长度D11的指示信息携带到写命令WC1中，并在步骤203中，将写命令WC1发送至内存120，从而将突发长度D1的指示信息发送至内存120中。具体而言，如上所述，写命令WC1缓存在命令缓存中，内存控制器120可以将突发长度D11的指示信息写入到写命令WC1。示例性的，当突发长度D11的指示信息为数据D1对应的压缩率时，内存控制器110在获得数据D1对应的压缩率时，可以将数据D1对应的压缩率写入到写命令WC1。示例性的，当突发长度D11的指示信息为突发长度的标识信息时，内存控制器110在从多种突发长度中确定出突发长度D11后，可以将突发长度D11的标识信息写入到写命令WC1。
当写命令WC1被执行时，例如，按照写命令仲裁原则对写命令WC1进行仲裁后，当仲裁结果为执行写命令WC1时，内存控制器110可以在步骤203中将写命令WC1发送至内存120。
继续参阅图2，内存控制器110可以执行步骤204，按照突发长度D11，向内存120发送数据D1。其中，此处的数据D1是指在步骤202中，用于确定突发长度D11的数据。即，在步骤202，内存控制器110根据将要在步骤204中发送的数据D1的数据量，确定了突发长度D11。此处的数据D1也可以称为压缩后的数据D1。接下来，如无特殊说明，下文提到的数据D1是指或者等同于内存控制器110在步骤204中发送的数据D1。
回到图1，数据D1在被发送至内存120之前，可以存放在写数据缓存中。在一个例子中，写数据缓存具体可以为Wdata que。内存控制器110在步骤204时，可以将数据D1从写数据缓存中取出，并通过步骤204，按照突发长度D11，将数据D1发送至内存120。其中，内存控制器110可以通过数据通道将数据D1发送至内存120。在一个例子中，数据通道可以包括双向数据线(Bi-directional data bus，DQ)通道。在另一个例子中，数据通道可以包括DQ通道和数据掩码(data mask，DM)通道。
在一些实施例中，内存控制器110可以需要将包括数据D1在内的多个数据发送至内存120。内存控制器110中的命令缓存模块缓存可以缓存多个写命令，该多个写命令可以和该多个数据一一对应。可以理解，在采用不同的突发长度传输数据时，所占据的时长不同。越大的突发长度所占据的时长越大，越小的突发长度所占据的时长越小。
因此，为了保障内存控制器110向内存120发送数据的有序进行，并且为了保障内存控制器110向内存120无缝发送数据，在内存控制器110从多种突发长度中确定出用于发送数据D1的突发长度D11时或之后，内存控制器110可以根据突发长度D11确定写命令WC1的发送时刻和下一个写命令的发送时刻之间的时间间隔T1。写命令WC1的发送时刻是指内存控制器110向内存120发送写命令WC1的时刻。其中，写命令WC1的发送标志着内存控制器110开始或者紧接着要向内存120发送数据D1。写命令WC1包括地址信息，该地址信息用于向内存120指示用于存储数据D1的存储空间的地址，使得内存120可以在该地址信息指示的存储空间中存储数据D1。下一个写命令是指内存控制器110在发送了写命令WC1之后，接着向内存120发送的写命令。该下一个写命令的发送标志着内存控制器110开始或紧接着要向内存120发送数据D2。数据D2是内存控制器110向内存120发送了数据D1之后，接着向内存120发送的数据。该下一个写命令包括地址信息，该地址信息用于向内存120指示用于存储数据D2的存储空间的地址，使得内存120可以在该地址信息指示的存储空间中存储数据D2。
其中，根据突发长度D11确定出的时间间隔T1的大小和突发长度的大小成正比例。即突 发长度D11越大，确定出的时间间隔越大；突发长度D11越小，确定出的时间间隔越小。在一个例子中，时间间隔T1等于突发长度D11的传输时长，其中，突发长度D11的传输时长是指采用突发长度D1进行突发传输时，突发传输所占据时长。
由此，通过控制内存控制器110发送相邻两个写命令的发送时间间隔，使得内存控制器110每当发送完一个数据后，可以紧接着发送下一个数据，在保障数据有序传输的同时，也保障了数据的无缝传输，提供了数据传输的效率。
在本申请实施例提供的数据存储方案中，可以提高内存控制器向内存发送数据的传输效率，提高了内存控制器和内存之间的内存接口带宽的利用率。图3示出了上述方案A和本申请实施例的方案的数据传输效率。如图3所示，在上述方案A中，内存控制器采用BL8这一固定突发长度，向内存发送数据，其中，相邻写命令的发送时间也固定。BL8所占据的时长较长，因此，方案A的数据传输效率较低。而在本申请实施例提供的方案中，可以不必拘泥于固定的突发长度，对数据进行压缩，从而可以将数据压缩为数据量较少的数据。根据压缩后的数据，确定的突发长度也比较小，例如，图3所示的BL6、BL4。由此，在本申请实施例中，可以采用BL6或BL4传输方案A中需要用BL8传输的数据，并且，根据写命令的发送时间间隔的大小与突发长度的大小成正比(例如，写命令31和写命令32之间的时间间隔由BL6确定，写命令32和写命令33之间的时间间隔由BL4确定)，当采用较小的突发长度传输数据时，也可以尽快发送下一个写命令，从而也可以尽快进行后续数据的传输。因此，相对于方案A，在本申请实施例提供方案中，存控制器向内存发送数据的传输效率更高，内存控制器和内存之间的内存接口带宽的利用率更高。
上文以内存控制器110向内存120发送数据D1为例，示例介绍了内存控制器110向内存120发送数据的方案。
接下来，仍以数据D1为例，示例介绍内存120接收并存储内存控制器110发送的数据的方案。
回到图2，内存120可以执行步骤205，根据突发长度D11的指示信息，按照突发长度D11，接收数据D1。具体而言，内存120在接收到内存控制器110通过步骤203发送的突发长度D11的指示信息后，可以根据突发长度D11的指示信息，确定出内存控制器110是通过突发长度D11来发送数据D1的，由此，内存120可以按照突发长度D11来接收内存控制器110发送的数据，实现数据D1的正确接收。其中，内存120在接收到突发长度D11的指示信息后，可以将之后按照突发长度D11接收到的内存控制器110发送的数据，确定为数据D1。
继续参阅图2，内存120在接收到数据D1之后，执行步骤206，存储数据D1。其中，回到图1，内存120可以将接收到数据D1缓存到数据路径中，然后，执行步骤206时，将数据D1从数据路径中取出，并存储到指定的存储空间中。如图1所示，内存120包括了至少一个存储空间。内存120在执行步骤206时或之前，需要从该至少一个存储空间中确定用于存储数据D1的存储空间D12。如上文所述，写命令WC1包括了地址信息，该地址信息指示了存储空间。内存120可以将该地址信息指示的存储空间，确定为用于存储数据D1的存储空间D12。然后，在步骤206中，内存120可以将数据D1存储到存储空间D12中。示例性的，写命令WC1中的地址信息具体指示了存储空间D12的起始地址，内存120可以以该地址信息指示的地址为起点地址，向后延伸预设数量的地址，得到存储空间D12。举例而言，写命令WC1中的地址信息指示了地址C0，则可以将地址C0以及地址C0之后的地址C1、地址C2、地址C3、地址C4、地址C5、地址C6、地址C7所代表的存储空间用作存储空间D12。
示例性的，内存120在执行步骤206时，可以按照数据接收顺序，依次将通过突发长度 D11接收的数据D1存储到存储空间D12中。举例而言，可以设定突发长度D1为BL4，也就是说，内存120在按照突发长度D11接收数据D1时，接收到的周期数为4的连续传输。还可以设定存储空间D12包括了地址C0、地址C1、地址C2、地址C3、地址C4、地址C5、地址C6、地址C7。则在步骤206中，内存120可以将周期数为4的连续传输中第一个周期传输的数据存储到地址C0，将周期数为4的连续传输中第二个周期传输的数据存储到地址C1，周期数为4的连续传输中第三个周期传输的数据存储到地址C2，周期数为4的连续传输中第四个周期传输的数据存储到地址C3。
如上所述，内存120从内存控制器100接收到的数据D1为压缩后的数据D1。在本申请实施例中，内存120可以不对接收到的数据D1进行解压缩，而是直接存储到存储空间D12中，从而节省了存储资源。
内存120还可以保存突发长度D11的指示信息，以方便内存120在向内存控制器110返回数据D1(例如处理器200读取数据D1)时，再次利用突发长度D11的指示信息，确定使用突发长度D11传输数据D1。在一些实施例中，内存120还可以将突发长度D11的指示信息和数据D1一同存储。具体而言，可以将内存120可以将突发长度D11的指示信息和数据D1存储到同一存储空间，即可以将突发长度D11的指示信息存储到存储空间D12中。
在一些实施例中，若突发长度D11并非多种突发长度中的最大突发长度，则说明数据D1对应的压缩率大于1。此时，内存120可以为数据D1添加压缩标记，以标识数据D1为压缩率大于1的压缩数据。若突发长度D11是多种突发长度中的最大突发长度，说明数据D1对应的压缩率为1，则不为数据D1添加压缩标记。其中，该多种突发长度即上文所述的内存控制器110和内存120支持的多种突发长度。
上述示例介绍了向内存120中存储数据的方案。接下来，介绍从内存120中读取数据的方案。
回到图2，处理器200可以执行步骤207，向内存控制器110发送读命令RC1。其中，读命令RC1用于读取数据D1。内存控制器110在接收到读命令RC1后，可以执行步骤208，向内存120发送读命令RC1，以触发内存120向数据D1内存控制器110发送数据D1。具示例性的，当内存控制器110接收到读命令RC1时，可以先将读命令RC1缓存到命令缓存中，在执行步骤208时，将读命令RC1从命令缓存中取出，然后通过步骤208，将读命令RC1发送至内存120。示例性的，内存控制器110可以通过控制通道，将读命令RC1发送至内存120。
内存120接收到读命令RC1后，可以响应读命令RC1，执行步骤209，读取数据D1。示例性的，内存120可以先将接收到的读命令RC1缓存到命令缓存中。在读命令RC1得到仲裁，可以被执行时，将读命令RC1从命令缓存中取出，并执行步骤209。
具体而言，读命令RC1可以包括地址信息，该地址信息指示了存储了数据D1的存储空间D12的地址。内存120根据该地址信息，确定出数据D1存储在存储空间D12中，进而内存120可以从存储空间D12，读取数据D1。
存储空间D12还存储了突发长度D11的指示信息，内存120在读取数据D1的同时，也可以读取到突发长度D11的指示信息。
内存120在读取了突发长度D11的指示信息之后，可以执行步骤210，向内存控制器110发送突发长度D11的指示信息，使得内存控制器110在后续步骤中，可以根据突发长度D11的指示信息，接收内存120发送的数据D1。在一个例子中，内存120可以通过DM通道，向内存110发送突发长度D11的指示信息。
内存120可以根据突发长度D11的指示信息，确定出突发长度D11，并执行步骤211，按 照突发长度D11，向内存控制器110发送数据D1。至于内存控制器110，其可以根据在步骤210接收到的突发长度D11的指示信息，接收内存120按照突发长度D11发送的数据D1。具体而言，内存控制器110可以根据突发长度D1的指示信息，确定出突发长度D11，并根据突发长度D11，接收内存120发送的数据D1。
在一些实施例中，回到图1，内存120的数据路径可以读取数据D1，并通过数据通道向内存控制器110发送数据D1。
在一些实施例中，若数据D1具有压缩标记，则内存120还可以将数据D1的压缩标记发送至内存控制器110，以便内存控制器110可以尽快判断出数据D1对应的压缩率是否大于1。若内存控制器110接收到内存发送的数据D1的压缩标记，可以确定数据D1对应的压缩率大于1，在这种情况下，内存控制器110可以进一步确定数据D1对应的压缩率。若内存控制器110没有接收到内存发送的数据D1的压缩标记，可以确定数据D1对应的压缩率等于1，在这种情况下，内存控制器110可以直接执行步骤212，将内存120发送的数据D1发送至处理器200。
其中，在一些实施例中，内存120可以通过DQ通道，向内存控制器110发送压缩标记。
在一些实施例中，突发长度D11的指示信息具体可以为数据D1对应的压缩率。内存控制器110接收到内存120发送的突发长度D11的指示信息，就可以得到数据D1对应的压缩率。
在一些实施例中，突发长度D11的指示信息具体可以突发长度D11的标识信息。内存控制器110可以根据突发长度D11的标识信息，确定数据D1对应突发长度D11，并根据突发长度D11，确定内存控制器110从内存120接收到的数据D1的数据量。然后，可以根据数据D1对应的原始数据的数据量和内存控制器110从内存120接收到的数据D1的数据量，确定数据D1对应的压缩率。
在一些实施例中，回到图1，内存控制器110可以包括压缩模块。在内存控制器110确定了数据D1对应的压缩率时，压缩模块可以根据数据D1对应的压缩率，对数据D1进行解压缩，并将解压缩后的数据D1，通过步骤212发送至处理器200。
在一些实施例中，在内存控制器110确定了数据D1对应的压缩率时，内存控制器可以将数据D1对应的压缩率和数据D1发送至处理器200或装置B1，然后，由处理器200或装置B1，根据数据D1对应的压缩率，对数据D1进行解压缩。
在一些实施例中，读命令RC1包括的地址信息具体指示了存储空间D12中的某地址，该地址为存储空间D12对应的多个地址中的部分地址。这可能说明，相对于存储空间D12中其他地址对应的数据，处理器200优先需要读命令中地址信息指示的地址对应的数据。以存储空间D12包括了地址C0、地址C1、地址C2、地址C3、地址C4、地址C5、地址C6、地址C7为例，设定读命令RC1包括的地址信息具体指示了地址C3。那么在数据D1对应的压缩率为1的情况下，则地址C3对应的数据可能为处理器200优先需要的数据。那么内存120在读命令RC1，向内存控制器发送数据D1时，先向内存控制器110发送地址C3对应的数据，随后再向内存控制器110发送地址C4、地址C5、地址C6、地址C7、地址C0、地址C1、地址C2对应的数据。示例性的，可以设定，突发长度D11对应的周期数为d1为突发传输，即按照突发长度D11发送数据D1是指,采用d1个周期连续传输来数据D1的发送。那么先向内存控制器110发送地址C3对应的数据具体可以为，内存120可以使用d1个周期中的第一个周期来传输或者说发送地址C3对应的数据。然后，再使用d1个周期中的其他周期传输或者说发送地址C4、地址C5、地址C6、地址C7、地址C0、地址C1、地址C2对应的数据。
在一些实施例中，在步骤207，处理器200可以向内存控制器110发送包括读命令RC1在 内的多个读命令。内存控制器110可将该多个读命令缓存到命令缓存中。由于内存控制器110不知这些读命令所要读取的数据对应的突发长度，为了保障读方向的数据无缝传输，提高读方向的数据传输效率，内存控制器110可以采用命令提前发送(commands issued in advance)方式，向内存120发生读命令，以提高读方向的效率。接下来，进行具体介绍。
命令提前发送也可以称为CMD Pull-in，是指按照命令发送的最小时间间隔，依次发送N个命令，N为大于或等于1的整数，减少命令执行方等待命令的时间，从而提高了命令执行效率。在本实施例中，内存控制器110可以先确定读命令发送的最小时间间隔T2。具体而言，内存控制器110可以根据多种突发长度中的最小突发长度，确定最小时间间隔T2。其中，该多种突发长度是指上文所述的内存控制器110和内存120支持的多种突发长度。在一个示例性的，可以设定多种突发长度中的最小突发长度为突发长度E1，则最小时间间隔T2不大于突发长度E1对应的读命令的发送时间间隔。其中，突发长度E1对应的读命令的发送时间间隔是指，在内存120按照突发长度E1向内存控制器110发送数据时，内存控制器110应采取的发送读命令的时间间隔。在一个例子中，最小时间间隔T2等于突发长度E1对应的读命令的发送时间间隔。也就是说，在该例子中，可以假设读命令所要读取的数据对应的突发长度为突发长度E1，并据此发送读命令。在一个示例中，最小时间间隔T2大于突发长度E1对应的读命令的发送时间间隔，且小于突发长度E2对应的读命令的发送时间间隔。其中，突发长度E2是多种突发长度中除突发长度E1之外的突发长度。
通过上述方式确定除了最小时间间隔T2。内存控制器110可以按照时间间隔T2，依次向内存120发送N个读命令。在一个示例中，N可以为预设值，例如可以为2、3或4等。在一个示例中，在设置N的值时可以考虑内存120中的命令缓存的大小。由上文所述，内存120接收到的读命令可以先缓存到命令缓存中，因此，命令缓存的大小决定了内存120可以缓存的读命令。因此，在设置N的值是可以考虑内存120中的命令缓存的大小，以避免读命令的丢失。在一个例子中，可以根据内存120中的命令缓存可以同时缓存读命令的最大数量，确定N的值。换言之，可以设定命令缓存最多可以同时缓存M个读命令，可以根据M的值确定N值。在一个例子中，可以设置N的值等于M值。在一个例子中，可以设定N的值小于M的值，且N的值和M的值之间相差Q，其中，Q为大于或等于1的整数。
本申请实施例采用读命令提前发送的机制，可以尽快向内存发送至少一个读命令，减少或者说避免了因内存等待读命令，而导致的数据发送效率低的问题，提高了内存接口带宽的利用率。示例性的，可以如图4所示，在方案A的方案中，内存控制器和内存之间采用固定的突发长度，即BL8，进行数据传输。内存控制器可以按照BL8对应的读命令的发送时间间隔，向内存发送读命令。内存接收读命令，并执行读命令，然后，按照BL8，向内存控制器返回数据。在本申请实施例提供的方案中，可以设定内存控制器110和内存120支持的多种突发长度中最小的突发长度为BL2，可以按照由BL2确定出的读命令最小发送时间间隔T2，先发N个读命令，使得内存120可以及时得到读命令，进而执行读命令，保障了数据的无缝发送，提高了内存接口的带宽利用率。
在一些实施例中，在内存控制器110向内存120发送了N个读命令之后，内存控制器110还可以根据从内存120接收到的突发长度的指示信息，确定用于再次发送读命令的时间间隔T3。
具体而言，当内存120接收到内存控制器110发送的N个读命令中的至少一个读命令之后，内存120可以执行接收到的至少一个读命令中的任意读命令，读取相应的数据以及相应的突发长度的指示信息。然后，内存120可以向内存控制器110发送读取到的突发长度的指 示信息以及数据。具体过程可以参考上文对图2中步骤209、步骤210和步骤213的介绍。其中，内存120可以根据接收到的至少一个读命令中的读命令RC2，读取数据D2和突发长度E2的指示信息，并向内存控制器110发送突发长度E2的指示信息，以及按照突发突发长度E2向内存控制器110发送数据D2。其中，当内存控制器110接收到内存120发送的突发长度E3的指示信息时，内存控制器110可以根据突发长度E3，确定用于再次发送读命令的时间间隔T3。更具体地，内存控制器110可以判断突发长度E3和突发长度E1是否为同一突发长度，即判断突发长度E3是否为内存控制器110和内存120支持的多种突发长度中的最小突发长度。若突发长度E3和突发长度E1为同一突发长度，则内存控制器110可以再次按照最小时间间隔T2，从内存控制器110的命令缓存中取出还未发送的读命令，并向内存120发送取出的读命令。若突发长度E3和突发长度E1不同，内存控制器110则可以根据突发长度E3，确定时间间隔T3。在一个例子中，时间间隔T3等于突发长度E3对应的读命令的发送时间间隔。突发长度E3对应的读命令的发送时间间隔是指，在采用突发长度E3进行数据传输时，读命令的发送时间间隔。
在确定出时间间隔T3后，内存控制器110可以按照时间间隔T3，从内存控制器110的命令缓存中取还未发送的读命令，并向内存120发送取出的读命令。其中，内存控制器110发送该取出的读命令的发送时刻和N个读命令中最后发送的读命令之间的时间间隔为时间间隔T3。
在一个例子中，回到图1，内存控制器110中的读数据缓存可以用于缓存内存120发送的突发长度E3的指示信息。然后，内存控制器110中的突发长度确定模块可以从读数据缓存中取出突发长度E3的指示信息，并根据突发长度E3的指示信息，确定突发长度E3。确定出的突发长度E3用于确定时间间隔T3，因此，存控制器110中的突发长度确定模块从读数据缓存中取出突发长度E3的指示信息，并根据突发长度E3的指示信息，确定突发长度E3的过程可以理解或者称为反压，即通过内存向内存控制器发送数据的情况，调整内存控制器向内存发送读命令的速度。
本申请实施例可以根据内存向内存控制器发送数据所采用的突发长度，重新确定用于再次发送读命令的时间间隔，从而使得读命令的发送速度和读命令的执行速度相匹配，从而在保障内存无缝向内存控制器发送数据的同时，无需向内存发送过多的读命令，减少了内存缓存读命令的压力。
在一些实施例中，回到图1，内存120中的数据路径可以对命令缓存进行反压。具体而言，当数据路径正在执行数据读取或者数据写入任务时，可以拒绝执行命令缓存中的读命令或写命令，从而可以保障数据读操作或数据写操作的有序进行。其中，反压的具体过程可以参考现有技术的介绍，在此不再赘述。
本申请实施例提供的数据存储方案，可以在写方向上，提高内存接口带宽的利用率，也可以在读方向上，提高内存接口带宽的利用率。其中，在采用FPC算法进行仿真测试时，内存带宽利用率可以提高50％左右。并且，本申请实施例提供的数据存储方案在往存储空间存储数据时，可以直接存储压缩后的数据，节省了内存的存储资源。
参阅图5，本申请实施例提供了一种数据存储方法，应用于包括内存控制器和第一内存的存储装置，所述第一内存包括至少一个存储空间。如图5所示，该方法包括如下步骤。
步骤501，内存控制器根据第一数据的数据量，从多种突发长度中确定用于传输所述第一数据的第一突发长度。具体可以参考上文对图2中步骤202的介绍。
步骤502，内存控制器向所述第一内存发送所述第一突发长度的第一指示信息，以及按 照所述第一突发长度向所述第一内存发送所述第一数据。具体可以参考上述对图2中步骤203、步骤204的介绍。
步骤503，第一内存根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。具体可以参考上文对图2中步骤205的介绍。
步骤504，第一内存将所述第一数据存储到所述至少一个存储空间中的第一存储空间。具体可以参考上文对图2中步骤206的介绍。
在一些实施例中，所述第一指示信息包括第一压缩率，所述第一数据是按照所述第一压缩率对预设大小的原始数据进行压缩后得到的，且所述第一压缩率对应所述第一突发长度；或者，所述第一指示信息包括用于代表所述第一突发长度的标识信息。
在一些实施例中，该方法还包括：所述内存控制器根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，所述第二突发长度在所述多种突发长度中最小；所述内存控制器根据所述第一时间间隔，依次向所述第一内存发送N个读命令，N为大于或等于1的整数。
在一些实施例中，所述第一时间间隔不大于所述第二突发长度的读命令的发送时间间隔。
在一些实施例中，该方法还包括：所述内存控制器接收所述第一内存发送的第三突发长度的第二指示信息，其中，所述第一内存按照所述第三突发长度向所述内存控制器发送第二数据，所述第二数据对应于所述N个读命令中的第一读命令；当所述第三突发长度和所述第二突发长度不同时，所述内存控制器根据所述第三突发长度，确定第二时间间隔；所述内存控制器根据所述第二时间间隔，依次向所述第一内存发送多个第二读命令，所述多个第二读命令的发送时刻和第三读命令的发送时刻的间隔为所述第二时间间隔，所述第三读命令是所述内存控制器在发送完所述N个读命令之后发送的读命令。
在一些实施例中，所述第一数据是对原始数据进行压缩后得到的，所述原始数据的数据量不大于一次第四突发长度所能传输的数据量，所述第四突发长度在所述多种突发长度中最大。
在一些实施例中，所述内存控制器向所述第一内存发送所述第一突发长度的第一指示信息包括：所述内存控制器向所述第一内存发送第一写命令，所述第一写命令携带有所述第一指示信息。
在一些实施例中，该方法还包括：所述内存控制器根据所述第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，所述第一写命令用于指示所述第一存储空间的地址；所述第二写命令用于指示所述至少一个存储空间中的第二存储空间的地址；其中，所述第二存储空间用于存储第三数据，所述第三数据是所述内存控制器在所述第一数据发送完成后，接着向所述第一内存发送的数据。
在一些实施例中，该方法还包括：所述内存控制器向所述第一内存发送第三读命令，所述第三读命令包括第一地址，所述第一地址是第三存储空间对应的多个地址中的部分地址；
所述内存控制器响应于所述第三读命令，先向所述内存控制器发送所述第一地址对应的数据，随后向所述内存控制器发送所述多个地址中其他地址对应的数据。
在一些实施例中，所述第一存储空间还用于存储所述第一指示信息；该方法还包括：所述内存控制器向所述第一内存发送第四读命令，所述第四读命令包括所述第一存储空间的地址；所述第一内存根据所述第一存储空间的地址，读取所述第一数据和所述第一指示信息；所述第一内存向所述内存控制器发送所述第一指示信息，以及按照所述第一突发长度向所述内存控制器发送所述第一数据；所述内存控制器根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。
本申请实施例提供的数据存储方法，可以在写方向上，提高内存接口带宽的利用率，也可以在读方向上，提高内存接口带宽的利用率。其中，在采用FPC算法进行仿真测试时，内存带宽利用率可以提高50％左右。并且，本申请实施例提供的数据存储装置在往存储空间存储数据时，可以直接存储压缩后的数据，节省了内存的存储资源。
参阅图6，本申请实施例还提供了一种数据存储装置600，包括内存控制器610和内存620，内存620包括至少一个存储空间，其中，
内存控制器610用于根据第一数据的数据量，从多种突发长度中确定用于传输第一数据的第一突发长度；具体可以参考上文对图2中步骤202的介绍。
内存控制器610用于向内存620发送第一突发长度的第一指示信息，以及按照第一突发长度向内存620发送第一数据。具体可以参考上述对图2中步骤203、步骤204的介绍。
内存620用于根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。具体可以参考上文对图2中步骤205的介绍。
内存620用于将所述第一数据存储到所述至少一个存储空间中的第一存储空间。具体可以参考上文对图2中步骤206的介绍。
在一些实施例中，所述第一指示信息包括第一压缩率，所述第一数据是按照所述第一压缩率对预设大小的原始数据进行压缩后得到的，且所述第一压缩率对应所述第一突发长度；或者，所述第一指示信息包括用于代表所述第一突发长度的标识信息。
在一些实施例中，内存控制器610还用于根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，所述第二突发长度在所述多种突发长度中最小；内存控制器610还用于根据所述第一时间间隔，依次向内存620发送N个读命令，N为大于或等于1的整数。
在一些实施例中，所述第一时间间隔不大于所述第二突发长度的读命令的发送时间间隔。
在一些实施例中，内存控制器610还用于接收内存620发送的第三突发长度的第二指示信息，其中，内存620按照所述第三突发长度向内存控制器610发送第二数据，所述第二数据对应于所述N个读命令中的第一读命令；当所述第三突发长度和所述第二突发长度不同时，内存控制器610还用于根据所述第三突发长度，确定第二时间间隔；内存控制器610还用于根据所述第二时间间隔，依次向内存620发送多个第二读命令。所述多个第二读命令是所述内存控制器在发送完所述N个读命令之后发送的读命令。
在一些实施例中，所述第一数据是对原始数据进行压缩后得到的，所述原始数据的数据量不大于一次第四突发长度所能传输的数据量，所述第四突发长度在所述多种突发长度中最大。
在一些实施例中，内存控制器610还用于向内存620发送第一写命令，所述第一写命令携带有所述第一指示信息。
在一些实施例中，内存控制器610还用于根据所述第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，所述第一写命令用于指示所述第一存储空间的地址；所述第二写命令用于指示所述至少一个存储空间中的第二存储空间的地址；其中，所述第二存储空间用于存储第三数据，所述第三数据是内存控制器610在所述第一数据发送完成后，接着向内存620发送的数据。
在一些实施例中，内存控制器610还用于向内存620发送第三读命令，所述第三读命令包括第一地址，所述第一地址是第三存储空间对应的多个地址中的部分地址；
内存控制器610还用于响应于所述第三读命令，先向内存控制器610发送所述第一地址对应的数据，随后向内存控制器610发送所述多个地址中其他地址对应的数据。
在一些实施例中，所述第一存储空间还用于存储所述第一指示信息；内存控制器610还用于向内存620发送第四读命令，所述第四读命令包括所述第一存储空间的地址；内存620还用于根据所述第一存储空间的地址，读取所述第一数据和所述第一指示信息；内存620还用于向内存控制器610发送所述第一指示信息，以及按照所述第一突发长度向内存控制器610发送所述第一数据；内存控制器610还用于根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。
内存控制器610和内存620的功能具体可以参考上文对图2所示的方法实施例实现，在此不再赘述。
本申请实施例提供的数据存储装置，可以在写方向上，提高内存接口带宽的利用率，也可以在读方向上，提高内存接口带宽的利用率。其中，在采用FPC算法进行仿真测试时，内存带宽利用率可以提高50％左右。并且，本申请实施例提供的数据存储装置在往存储空间存储数据时，可以直接存储压缩后的数据，节省了内存的存储资源。
本申请实施例提供了一种计算设备。参阅图7，该计算设备包括处理器700和存储装置6500。其中，处理器700的功能可以参考上文对处理器200的介绍实现。
可以理解的是，在本申请实施例的描述中，“示例性的”、“例如”或者“举例来说”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”、“例如”或者“举例来说”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”、“例如”或者“举例来说”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，单独存在B，同时存在A和B这三种情况。另外，除非另有说明，术语“多个”的含义是指两个或两个以上。例如，多个系统是指两个或两个以上的系统，多个终端是指两个或两个以上的终端。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。术语“包括”、“包含”、“具有”及它们的变形都意味着“包括但不限于”，除非是以其他方式另外特别强调。
可以理解的是，以上实施例仅用以说明本申请的技术方案，而对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种数据存储方法，其特征在于，应用于包括内存控制器和第一内存的存储装置，所述第一内存包括至少一个存储空间，所述方法包括：
    所述内存控制器根据第一数据的数据量，从多种突发长度中确定用于传输所述第一数据的第一突发长度；
    所述内存控制器向所述第一内存发送所述第一突发长度的第一指示信息，以及按照所述第一突发长度向所述第一内存发送所述第一数据；
    所述第一内存根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据；
    所述第一内存将所述第一数据存储到所述至少一个存储空间中的第一存储空间。
  2. 根据权利要求1所述的方法，其特征在于，
    所述第一指示信息包括第一压缩率，所述第一数据是按照所述第一压缩率对预设大小的原始数据进行压缩后得到的，且所述第一压缩率对应所述第一突发长度；
    或者，
    所述第一指示信息包括用于代表所述第一突发长度的标识信息。
  3. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    所述内存控制器根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，所述第二突发长度在所述多种突发长度中最小；
    所述内存控制器根据所述第一时间间隔，依次向所述第一内存发送N个读命令，N为大于或等于1的整数。
  4. 根据权利要求3所述的方法，其特征在于，所述第一时间间隔不大于所述第二突发长度的读命令的发送时间间隔。
  5. 根据权利要求3或4所述的方法，其特征在于，所述方法还包括：
    所述内存控制器接收所述第一内存发送的第三突发长度的第二指示信息，其中，所述第一内存按照所述第三突发长度向所述内存控制器发送第二数据，所述第二数据对应于所述N个读命令中的第一读命令；
    当所述第三突发长度和所述第二突发长度不同时，所述内存控制器根据所述第三突发长度，确定第二时间间隔；
    所述内存控制器根据所述第二时间间隔，依次向所述第一内存发送多个第二读命令，所述多个第二读命令是所述内存控制器在发送完所述N个读命令之后发送的读命令。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述第一数据是对原始数据进行压缩后得到的，所述原始数据的数据量不大于一次第四突发长度所能传输的数据量，所述第四突发长度在所述多种突发长度中最大。
  7. 根据权利要求1-6任一项所述的方法，其特征在于，所述内存控制器向所述第一内存 发送所述第一突发长度的第一指示信息包括：所述内存控制器向所述第一内存发送第一写命令，所述第一写命令携带有所述第一指示信息。
  8. 根据权利要求1-7任一项所述的方法，其特征在于，所述方法还包括：
    所述内存控制器根据所述第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，所述第一写命令用于指示所述第一存储空间的地址；所述第二写命令用于指示所述至少一个存储空间中的第二存储空间的地址；其中，所述第二存储空间用于存储第三数据，所述第三数据是所述内存控制器在所述第一数据发送完成后，接着向所述第一内存发送的数据。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，所述方法还包括：
    所述内存控制器向所述第一内存发送第三读命令，所述第三读命令包括第一地址，所述第一地址是第三存储空间对应的多个地址中的部分地址；
    所述内存控制器响应于所述第三读命令，先向所述内存控制器发送所述第一地址对应的数据，随后向所述内存控制器发送所述多个地址中其他地址对应的数据。
  10. 根据权利要求1-9任一项所述的方法，其特征在于，所述第一存储空间还用于存储所述第一指示信息；所述方法还包括：
    所述内存控制器向所述第一内存发送第四读命令，所述第四读命令包括所述第一存储空间的地址；
    所述第一内存根据所述第一存储空间的地址，读取所述第一数据和所述第一指示信息；
    所述第一内存向所述内存控制器发送所述第一指示信息，以及按照所述第一突发长度向所述内存控制器发送所述第一数据；
    所述内存控制器根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。
  11. 一种数据存储装置，其特征在于，包括内存控制器和第一内存，所述第一内存包括至少一个存储空间，其中，
    所述内存控制器用于根据第一数据的数据量，从多种突发长度中确定用于传输所述第一数据的第一突发长度；
    所述内存控制器用于向所述第一内存发送所述第一突发长度的第一指示信息，以及按照所述第一突发长度向所述第一内存发送所述第一数据；
    所述第一内存用于根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据；
    所述第一内存用于将所述第一数据存储到所述至少一个存储空间中的第一存储空间。
  12. 根据权利要求11所述的装置，其特征在于，
    所述第一指示信息包括第一压缩率，所述第一数据是按照所述第一压缩率对预设大小的原始数据进行压缩后得到的，且所述第一压缩率对应所述第一突发长度；
    或者，
    所述第一指示信息包括用于代表所述第一突发长度的标识信息。
  13. 根据权利要求1所述的装置，其特征在于，
    所述内存控制器还用于根据第二突发长度，确定用于发送读命令的第一时间间隔；其中，所述第二突发长度在所述多种突发长度中最小；
    所述内存控制器还用于根据所述第一时间间隔，依次向所述第一内存发送N个读命令，N为大于或等于1的整数。
  14. 根据权利要求13所述的装置，其特征在于，所述第一时间间隔不大于所述第二突发长度的读命令的发送时间间隔。
  15. 根据权利要求13或14所述的装置，其特征在于，
    所述内存控制器还用于接收所述第一内存发送的第三突发长度的第二指示信息，其中，所述第一内存按照所述第三突发长度向所述内存控制器发送第二数据，所述第二数据对应于所述N个读命令中的第一读命令；
    当所述第三突发长度和所述第二突发长度不同时，所述内存控制器还用于根据所述第三突发长度，确定第二时间间隔；
    所述内存控制器还用于根据所述第二时间间隔，依次向所述第一内存发送多个第二读命令，所述多个第二读命令是所述内存控制器在发送完所述N个读命令之后发送的读命令。
  16. 根据权利要求11-15任一项所述的装置，其特征在于，所述第一数据是对原始数据进行压缩后得到的，所述原始数据的数据量不大于一次第四突发长度所能传输的数据量，所述第四突发长度在所述多种突发长度中最大。
  17. 根据权利要求11-16任一项所述的装置，其特征在于，所述内存控制器还用于向所述第一内存发送第一写命令，所述第一写命令携带有所述第一指示信息。
  18. 根据权利要求11-17任一项所述的装置，其特征在于，所述内存控制器还用于根据所述第一突发长度，确定第一写命令的发送时刻和第二写命令的发送时刻之间的时间间隔；其中，所述第一写命令用于指示所述第一存储空间的地址；所述第二写命令用于指示所述至少一个存储空间中的第二存储空间的地址；其中，所述第二存储空间用于存储第三数据，所述第三数据是所述内存控制器在所述第一数据发送完成后，接着向所述第一内存发送的数据。
  19. 根据权利要求11-18任一项所述的装置，其特征在于，
    所述内存控制器还用于向所述第一内存发送第三读命令，所述第三读命令包括第一地址，所述第一地址是第三存储空间对应的多个地址中的部分地址；
    所述内存控制器还用于响应于所述第三读命令，先向所述内存控制器发送所述第一地址对应的数据，随后向所述内存控制器发送所述多个地址中其他地址对应的数据。
  20. 根据权利要求11-19任一项所述的装置，其特征在于，所述第一存储空间还用于存储所述第一指示信息；
    所述内存控制器还用于向所述第一内存发送第四读命令，所述第四读命令包括所述第一存储空间的地址；
    所述第一内存还用于根据所述第一存储空间的地址，读取所述第一数据和所述第一指示 信息；
    所述第一内存还用于向所述内存控制器发送所述第一指示信息，以及按照所述第一突发长度向所述内存控制器发送所述第一数据；
    所述内存控制器还用于根据所述第一指示信息，按照所述第一突发长度，接收所述第一数据。
  21. 一种计算设备，其特征在于，包括：
    处理器；
    权利要求11-20任一项所述的存储装置。
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