CN110719670A - LED short-circuit detection circuit, driving chip and driving method - Google Patents

LED short-circuit detection circuit, driving chip and driving method Download PDF

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Publication number
CN110719670A
CN110719670A CN201911126739.6A CN201911126739A CN110719670A CN 110719670 A CN110719670 A CN 110719670A CN 201911126739 A CN201911126739 A CN 201911126739A CN 110719670 A CN110719670 A CN 110719670A
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circuit
pmos
tube
nmos tube
source
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胡渊
刘宝生
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Limited Co Of Fu Man Electronics Group Of Shenzhen
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Limited Co Of Fu Man Electronics Group Of Shenzhen
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Abstract

The invention provides an LED short circuit detection circuit, which comprises a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplification circuit, wherein the configurable voltage source is connected with the switch control circuit; the configurable voltage source generates sampling voltage and bias voltage, and transmits the sampling voltage and the bias voltage to the switch control circuit and the current amplification circuit respectively; the current amplification circuit converts the bias voltage into current for amplification, generates the driving current of the LED lamp bead, and judges whether the driving current is output or not after receiving the judgment signal; the switch control circuit outputs a judgment signal after receiving the sampling voltage, transmits the judgment signal to the current amplification circuit and transmits the judgment signal to the digital control storage circuit; and the digital control storage circuit closes the short-circuit detection branch current according to the judgment signal and the power-on reset signal. The circuit solves the defect that in the prior art, the LED lamp bead is easy to burn out due to the short circuit of the VREXT end of the LED driving chip, and achieves the VREXT short circuit detection of the LED driving chip with low power consumption and the self-recovery control function.

Description

LED short-circuit detection circuit, driving chip and driving method
Technical Field
The invention belongs to the technical field of integrated circuit chips, and particularly relates to an LED short circuit detection circuit, a driving chip and a driving method.
Background
The common LED driving chip generally adopts a constant current driving method to drive the LED lamp beads. The working current of the LED lamp bead is adjusted by the VREXT end of the LED driving chip through an external precision resistor, and the smaller the external resistor is, the larger the current flowing through the LED lamp bead is. The working current of a general LED lamp bead is less than 30mA, if the LED lamp bead flows through overlarge current, the LED lamp bead can be highlighted, long-time highlighting can lead to the LED lamp bead being burnt out, and then the display effect of the LED display screen is influenced.
In order to solve the above problem, in the conventional method, a voltage sampling is performed on a VREXT end of an LED driving chip, and after the voltage sampling is compared with a reference voltage, whether to turn off a driving circuit is determined. However, the method has the disadvantage that when the VREXT end is short-circuited, the voltage is low potential, which is easily affected by the power voltage and substrate noise, etc., resulting in misjudgment, and adversely affects the display effect of the LED display screen.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides an LED short-circuit detection circuit, a driving chip and a driving method, and solves the problem that in the prior art, an LED lamp bead is easy to burn out due to the short circuit of a VREXT end of an LED driving chip.
In a first aspect, an LED short circuit detection circuit includes a configurable voltage source, a switch control circuit, a digitally controlled storage circuit, and a current amplification circuit;
the configurable voltage source is used for generating sampling voltage and bias voltage and respectively transmitting the sampling voltage and the bias voltage to the switch control circuit and the current amplification circuit;
the current amplification circuit is used for converting the bias voltage into current and amplifying the current to generate the driving current of the LED lamp bead; the current amplifying circuit is also used for judging whether to output the driving current or not after receiving the judging signal;
the switch control circuit is used for outputting a judgment signal after receiving the sampling voltage and transmitting the judgment signal to the current amplification circuit; the switch control circuit is also used for transmitting the judgment signal to the digital control storage circuit;
and the digital control storage circuit is used for closing the short-circuit detection branch current according to the judgment signal and the power-on reset signal.
Preferably, the input end of the configurable voltage source is connected to the first reference voltage, the VREXT end of the LED driving chip, and the judgment delay output port of the switch control circuit, the bias voltage output end of the configurable voltage source is connected to the first input end of the current amplifying circuit, and the sampling voltage output end of the configurable voltage source is connected to the first input end of the switch control circuit;
the second input end of the switch control circuit is connected with the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input end of the current amplification circuit;
the judgment output port of the switch control circuit is connected with the first input end of the digital control storage circuit, the second input end of the digital control storage circuit is connected with a power-on reset signal, the third input end of the digital control storage circuit is connected with an external control signal, and the PWM output port of the digital control storage circuit is connected with the third input end of the current amplification circuit;
and the fourth input end of the current amplifying circuit is connected with the second reference voltage, and the output end of the current amplifying circuit is connected with the output end of the LED driving chip.
Preferably, the judgment delay output port of the switch control circuit is obtained by delaying and reversing the judgment output port of the switch control circuit.
Preferably, the configurable voltage source comprises an operational amplifier OP1, a PMOS transistor PM _1, an NMOS transistor NM _4 and a switch SW 2;
the first reference voltage is connected to the equidirectional input end of an operational amplifier OP1, the VREXT end of the LED driving chip is connected to the inverted input end of an operational amplifier OP1 through a series resistor RINT1, the middle node of the resistor RINT1 and the VREXT end of the LED driving chip is connected with the drain electrode of an NMOS tube NM _4, and the source electrode and the grid electrode of the NMOS tube NM _4 are grounded;
the output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM _1, the source of the PMOS tube PM _1 is connected to the high level, the drain of the PMOS tube PM _1 is connected to one contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 and is connected to the middle node of the resistor RINT1 and the VREXT end of the LED driving chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit;
the detection end of the operational amplifier OP1 is used as the sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 is used as the bias voltage output end of the configurable voltage source.
Preferably, the operational amplifier OP1 includes a PMOS transistor PM _11, a PMOS transistor PM _12, a PMOS transistor PM _13, a PMOS transistor PM _14, a PMOS transistor PM _15, an NMOS transistor NM _11, an NMOS transistor NM _12, an NMOS transistor NM _13, and an NMOS transistor NM _ 14;
the grid electrode of the PMOS tube PM _15 is connected with a reference power supply, the drain electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _11 and PM _12, the source electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _13 and PM _14, the drain electrode of the PMOS tube PM _13 is connected with the drain electrode of the NMOS tube NM _13, the drain electrode of the PMOS tube PM _14 is connected with the drain electrode of the NMOS tube NM _14, the grid electrode of the NMOS tube NM _13 is connected with the grid electrode of the NMOS tube NM _14, the source electrode of the NMOS tube NM _13 is connected with the drain electrode of the NMOS tube NM _11, the source electrode of the NMOS tube NM _14 is connected with the drain electrode of the NMOS tube NM _12, and the; the drain electrode of the PMOS tube PM _11 is connected with the drain electrode of the NMOS tube NM _11, and the drain electrode of the PMOS tube PM _12 is connected with the drain electrode of the NMOS tube NM _ 12;
a node between the drain electrode of the PMOS tube PM _14 and the drain electrode of the NMOS tube NM _14 is used as the output end of the operational amplifier; the grid electrode of the PMOS tube PM _11 is used as the homodromous input end of the operational amplifier; the grid electrode of the PMOS pipe PM _12 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _13, the grid electrode of the PMOS pipe PM _14 and the middle nodes of the drain electrode of the PMOS pipe PM _13 and the drain electrode of the NMOS pipe NM _13 are connected with each other to be used as the detection end of the operational amplifier.
Preferably, the switch control circuit comprises a PMOS tube PM _3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND 2;
the sampling voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS (P-channel metal oxide semiconductor) transistor PM _3, the source electrode of the PMOS transistor PM _3 is connected with a high level, the drain electrode of the PMOS transistor PM _3 is grounded by being connected with the current source Ib in series, the drain electrode of the PMOS transistor PM _3 is connected with the input end of a trigger SMIT1, and the output end of the trigger SMIT1 is used as the judgment output port; the output end of the flip-flop SMIT1 is connected with the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected with one input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected with the digital output reset signal, and the output end of the NAND gate NAND2 is used as a judgment delay output port.
Preferably, the current amplifying circuit includes an operational amplifier OP2, an operational amplifier OP3, a PMOS transistor PM _2, a switch SW1, an NMOS transistor NM _1, an NMOS transistor NM _2, and an NMOS transistor NM _ 3;
the bias voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS tube PM _2, the source electrode of the PMOS tube PM _2 is connected with a high level, the drain electrode of the PMOS tube PM _2 is connected with the drain electrode of an NMOS tube NM _1, the drain electrode of the PMOS tube PM _2 is also connected with the reverse input end of an operational amplifier OP2, the homodromous input end of the operational amplifier OP2 is connected with a second reference voltage, the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _1, and the source electrode of the NMOS tube NM _1 is grounded;
the drain electrode of the PMOS tube PM _2 is connected with the equidirectional input end of the operational amplifier OP3, the output end of the operational amplifier OP3 is connected with the grid electrode of the NMOS tube NM _3, the source electrode of the NMOS tube NM _3 is connected with the drain electrode of the NMOS tube NM _2, the source electrode of the NMOS tube NM _3 is connected with the reverse input end of the operational amplifier OP3, the source electrode of the NMOS tube NM _2 is grounded, and the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _ 2;
the judgment output port of the switch control circuit is connected with the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected with the output end of the operational amplifier OP 2;
the drain electrode of the NMOS tube NM _3 is connected to the output end of the LED driving chip; the enable terminal of the operational amplifier OP3 serves as the third input terminal of the current amplifying circuit.
Preferably, the operational amplifier OP3 includes an inverter INV1, a PMOS transistor PM _21, a PMOS transistor PM _22, a PMOS transistor PM _23, a PMOS transistor PM _24, a PMOS transistor PM _25, a PMOS transistor PM _26, an NMOS transistor NM _21, an NMOS transistor NM _22, an NMOS transistor NM _23, an NMOS transistor NM _24, a current source I3, and a current source I2;
the grid electrode of the PMOS pipe PM _21 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _22 is used as the homodromous input end of the operational amplifier; the source electrode of the PMOS tube PM _21 and the source electrode of the PMOS tube PM _22 are both connected to the drain electrode of the PMOS tube PM _24, the source electrode of the PMOS tube PM _24 is connected with the high level, the grid electrode of the PMOS tube PM _24 is connected with the grid electrode of the PMOS tube PM _23, the source electrode of the PMOS tube PM _23 is connected with the high level, the drain electrode of the PMOS tube PM _23 is grounded through the current source I3 in series, and the grid electrode of the PMOS tube PM _23 is connected to the drain electrode of the PMOS tube PM _ 23;
the drain electrode of the PMOS tube PM _21 is connected with the drain electrode of the NMOS tube NM _21, the source electrode of the NMOS tube NM _21 is grounded, and the drain electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 21; the drain electrode of the PMOS tube PM _22 is connected with the drain electrode of the NMOS tube NM _22, the source electrode of the NMOS tube NM _22 is grounded, and the grid electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 22;
the node between the drain of the PMOS tube PM _22 and the drain of the NMOS tube NM _22 is connected with the gate of the NMOS tube NM _23, the source of the NMOS tube NM _23 is grounded, the drain of the NMOS tube NM _23 is connected with the drain of the PMOS tube PM _26, the source of the PMOS tube PM _26 is connected with the drain of the PMOS tube PM _25, the source of the PMOS tube PM _25 is connected with the high level, the gate of the PMOS tube PM _26 is connected with the gate of the PMOS tube PM _23, the enable end of the operational amplifier OP3 is connected with the input end of the inverter INV1, the output end of the inverter INV1 is connected with the gate of the PMOS tube PM _25, the output end of the inverter INV1 is connected with the gate of the NMOS tube NM _24, the source of the NMOS tube NM _24 is grounded through the current source I2 connected in series, the drain of the NMOS tube NM _24 is connected with the drain of the NMOS.
In a second aspect, an LED driver chip,
the LED short circuit detection circuit comprises the LED short circuit detection circuit of the first aspect.
In a third aspect, an LED driving method, performed on the LED short detection circuit of the first aspect, includes the steps of:
the first reference voltage is input into a configurable voltage source, a judgment delay signal of the switch control circuit is input into the configurable voltage source through a judgment delay output port, and external voltage generated by a VREXT end of the LED driving chip is input into the configurable voltage source;
the configurable voltage source generates sampling voltage, and the sampling voltage is transmitted to the switch control circuit through the sampling voltage output end;
the configurable voltage source generates bias voltage and transmits the bias voltage to the current amplification circuit through the bias voltage output end;
the current amplification circuit converts the bias voltage into current and amplifies the current to generate driving current of the LED lamp bead;
the digital output reset signal of the digital control storage circuit is input to the switch control circuit through a digital output reset signal output port;
the switch control circuit outputs a judgment signal according to the received sampling voltage and transmits the judgment signal to the current amplification circuit through a judgment output port; the judging signal is used for controlling the current amplifying circuit to output the driving current or not;
the switch control circuit transmits a judgment signal to the digital control storage circuit, and the digital control storage circuit closes the short circuit detection branch current according to the judgment signal and the power-on reset signal.
According to the technical scheme, the LED short circuit detection circuit, the driving chip and the driving method provided by the invention solve the defect that in the prior art, an LED lamp bead is easy to burn out due to the short circuit of the VREXT end of the LED driving chip, and realize the VREXT short circuit detection of the LED driving chip with low power consumption and the self-recovery control function.
Drawings
In order to more clearly illustrate the detailed description of the invention or the technical solutions in the prior art, the drawings that are needed in the detailed description of the invention or the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
Fig. 1 is a schematic diagram of an LED short circuit detection circuit according to an embodiment of the present invention.
Fig. 2 is a circuit diagram of an LED short-circuit detection circuit according to a second embodiment of the present invention.
Fig. 3 is a circuit diagram of an operational amplifier OP1 according to a second embodiment of the present invention.
Fig. 4 is a circuit diagram of the operational amplifier OP3 according to the second embodiment of the present invention.
Fig. 5 is a flowchart of an LED driving method according to a fourth embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby. It is to be noted that, unless otherwise specified, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art to which the invention pertains.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The first embodiment is as follows:
an LED short circuit detection circuit comprises a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplification circuit;
the configurable voltage source is used for generating sampling voltage and bias voltage and respectively transmitting the sampling voltage and the bias voltage to the switch control circuit and the current amplification circuit;
the current amplification circuit is used for converting the bias voltage into current and amplifying the current to generate the driving current of the LED lamp bead; the current amplifying circuit is also used for judging whether to output the driving current or not after receiving the judging signal;
the switch control circuit is used for outputting a judgment signal after receiving the sampling voltage and transmitting the judgment signal to the current amplification circuit; the switch control circuit is also used for transmitting the judgment signal to the digital control storage circuit;
and the digital control storage circuit is used for closing the short-circuit detection branch current according to the judgment signal and the power-on reset signal.
Referring to fig. 1, an input end of the configurable voltage source is connected to a first reference voltage, a VREXT end of the LED driving chip, and a judgment delay output port of the switch control circuit, an offset voltage output end of the configurable voltage source is connected to a first input end of the current amplifying circuit, and a sampling voltage output end of the configurable voltage source is connected to a first input end of the switch control circuit;
the second input end of the switch control circuit is connected with the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input end of the current amplification circuit;
the judgment output port of the switch control circuit is connected with the first input end of the digital control storage circuit, the second input end of the digital control storage circuit is connected with a power-on reset signal, the third input end of the digital control storage circuit is connected with an external control signal, and the PWM output port of the digital control storage circuit is connected with the third input end of the current amplification circuit;
and the fourth input end of the current amplifying circuit is connected with the second reference voltage, and the output end of the current amplifying circuit is connected with the output end of the LED driving chip.
Specifically, the power-on reset signal por is generated by a por module in the LED driving chip, and the por module is a mature module in the LED driving chip. The first reference voltage Vref1 is a reference voltage for the input configurable voltage source. When the circuit is used specifically, a power supply needs to be externally connected to the VREXT end of the LED driving chip, a resistor REXT needs to be externally connected to the ground, and the voltage input value of the VREXT end is adjusted through the resistor REXT. The output end OUT of the LED driving chip is connected with the cathode of the LED lamp bead to drive the LED lamp bead.
Preferably, the judgment delay output port of the switch control circuit is obtained by delaying and reversing the judgment output port of the switch control circuit.
In the LED Short circuit detection circuit, a first reference voltage Vref1 and a delayed and reversed judgment delay signal Short _ dly _ b are input into a configurable voltage source, and a resistor REXT is connected to the ground through the outside of a VREXT end to generate VREXT voltage. The configurable voltage source outputs a sampling voltage VS to the switch control circuit, the switch control circuit outputs whether to close the NMOS tube NM _1 and NM _2 of the LED constant-current driving tube, the operational amplifier and the judgment signal Short of the digital control storage circuit, and the Short signal is input to the configurable voltage source after being delayed and reversed (namely Short _ dly _ b). When the switch control circuit detects that the VREXT pin is short-circuited, the short-circuit detection branch is closed (namely the switch SW2 is opened), and the power consumption of the LED driving chip is reduced.
The switch control circuit outputs a judgment signal Short to the digital control storage circuit, when the digital control storage circuit detects that the VREXT pin is Short-circuited, the pulse width modulation signal output by the PWM output port is pulled down, and meanwhile, the Short-circuit detection branch current is closed, so that the purpose of saving power is achieved to the maximum extent. The Por _ dig signal is a power-on reset signal Por or a soft reset signal after fixed time timing, and is used for restarting the current of the short-circuit detection branch circuit of the VREXT pin after the VREXT pin is recovered to be normally connected with the external resistor.
The configurable voltage source outputs a bias voltage VG1 to the current amplification circuit, VG1 is converted into a current I2 through PM _2, and a constant current driving current for the LED lamp bead is generated through NM _1 and NM _2 current mirror amplification.
The LED short circuit detection circuit solves the defect that in the prior art, an LED lamp bead is easy to burn out due to the short circuit of the VREXT end of an LED driving chip, and achieves the VREXT short circuit detection of the LED driving chip with low power consumption and the self-recovery control function.
Example two:
the second embodiment provides a specific circuit of the LED short circuit detection circuit based on the first embodiment.
Referring to fig. 2, the configurable voltage source includes an operational amplifier OP1, a PMOS transistor PM _1, an NMOS transistor NM _4, and a switch SW 2;
the first reference voltage is connected to the equidirectional input end of an operational amplifier OP1, the VREXT end of the LED driving chip is connected to the inverted input end of an operational amplifier OP1 through a series resistor RINT1, the middle node of the resistor RINT1 and the VREXT end of the LED driving chip is connected with the drain electrode of an NMOS tube NM _4, and the source electrode and the grid electrode of the NMOS tube NM _4 are grounded;
the output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM _1, the source of the PMOS tube PM _1 is connected to the high level, the drain of the PMOS tube PM _1 is connected to one contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 and is connected to the middle node of the resistor RINT1 and the VREXT end of the LED driving chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit;
the detection end of the operational amplifier OP1 is used as the sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 is used as the bias voltage output end of the configurable voltage source.
Specifically, the external control signal SDI is an input control signal of the LED lamp bead, and is processed by the digital control storage circuit to generate a Pulse Width Modulation (PWM) output. The Por signal is a power-on reset signal, the Short signal is a judgment signal generated by the switch control circuit, and the Por _ dig output low level is used for closing SW2 and recovering the current of the VREXT pin Short-circuit detection branch circuit.
The operational amplifier OP1, the PMOS transistor PM _1, the NMOS transistor NM _4, the resistor RINT1, the resistor RINT2 and the switch SW2 form a configurable voltage source. The pin VREXT is connected with the external resistor REXT of the chip to the ground, and generates VREXT voltage, bias voltage VG1 and sampling voltage VS. The NMOS transistor NM _4 is diode-connected and used for electrostatic protection together with the resistors RINT1 and RINT 2. To achieve a larger drive current, resistor RINT2 is typically smaller. When a VREXT pin is short-circuited, the output VG1 of the operational amplifier OP1 is driven to be close to a low potential, and the resistor RINT2 is a small resistor, so that the current flowing through the PMOS tube PM _1 is large, and after the short circuit, although the current for driving the LED lamp beads can be turned off, the inside of the LED driving chip consumes large current. Thus, normally, switch SW2 is closed; when the VREXT pin is short-circuited, the switch SW2 is switched off, so that the power consumption of the LED driving chip can be greatly reduced, and the aim of saving power to the maximum extent is fulfilled.
Referring to fig. 3, the operational amplifier OP1 includes a PMOS transistor PM _11, a PMOS transistor PM _12, a PMOS transistor PM _13, a PMOS transistor PM _14, a PMOS transistor PM _15, an NMOS transistor NM _11, an NMOS transistor NM _12, an NMOS transistor NM _13, and an NMOS transistor NM _ 14;
the grid electrode of the PMOS tube PM _15 is connected with a reference power supply, the drain electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _11 and PM _12, the source electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _13 and PM _14, the drain electrode of the PMOS tube PM _13 is connected with the drain electrode of the NMOS tube NM _13, the drain electrode of the PMOS tube PM _14 is connected with the drain electrode of the NMOS tube NM _14, the grid electrode of the NMOS tube NM _13 is connected with the grid electrode of the NMOS tube NM _14, the source electrode of the NMOS tube NM _13 is connected with the drain electrode of the NMOS tube NM _11, the source electrode of the NMOS tube NM _14 is connected with the drain electrode of the NMOS tube NM _12, and the; the drain electrode of the PMOS tube PM _11 is connected with the drain electrode of the NMOS tube NM _11, and the drain electrode of the PMOS tube PM _12 is connected with the drain electrode of the NMOS tube NM _ 12;
a node between the drain electrode of the PMOS tube PM _14 and the drain electrode of the NMOS tube NM _14 is used as the output end of the operational amplifier; the grid electrode of the PMOS tube PM _11 is used as the homodromous input end of the operational amplifier; the grid electrode of the PMOS pipe PM _12 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _13, the grid electrode of the PMOS pipe PM _14 and the middle nodes of the drain electrode of the PMOS pipe PM _13 and the drain electrode of the NMOS pipe NM _13 are connected with each other to be used as the detection end of the operational amplifier.
Specifically, in the LED short circuit detection circuit, the operational amplifier OP1, the operational amplifier OP2 and the operational amplifier OP3 all adopt the structure of fig. 3, wherein the operational amplifier OP1 leads out a detection terminal, and the operational amplifier OP2 and the operational amplifier OP3 do not lead out a detection terminal.
In FIG. 3, VBP1, VBN1, and VBN2 are bias voltages for input, In + and In-are the inverting input and inverting input of the operational amplifier, out is the output of the operational amplifier, and VS is the detection terminal of the operational amplifier. I1 and I2 are currents flowing through PMOS transistor PM _13 and PMOS transistor PM _14, respectively. Normally, according to the negative feedback principle of the operational amplifier, I1 is I2 and is a preset bias current value, when the VREXT terminal is short-circuited, the input terminal of the operational amplifier OP1 in the same direction is at a low potential, the output terminal of the operational amplifier OP1 is at a low potential, and therefore, I1 is I2 is 0, and the voltage at the VS terminal is raised to a high level. Thus, stable and reliable sampling signals can be generated based on the internal negative feedback mechanism of the operational amplifier.
In the LED short-circuit detection circuit, an internal key signal of an operational amplifier OP1 is LED out to be used as a detection end and used as a sampling signal of a VREXT pin with short circuit. The LED short circuit detection circuit is based on an operational amplifier negative feedback mechanism, and if the VREXT end is externally connected with a proper resistor to the ground, the sampling voltage is kept unchanged. When the VREXT end is short-circuited, the sampling voltage is raised, the output of a current comparator consisting of a PMOS (P-channel metal oxide semiconductor) tube PM _3 and a current source Ib is inverted, and then the constant-current driving tubes NM _1 and NM _2 are directly closed; when the VREXT end is recovered and an appropriate resistor is externally connected to the ground, the constant current driving tubes NM _1 and NM _2 are rapidly recovered and started.
Preferably, the switch control circuit comprises a PMOS tube PM _3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND 2; the key signal VS in the operational amplifier OP1 is controlled by the system loop in real time, has high sensitivity as a detection signal, and can self-restore VREXT short circuit detection branch current. The output of the switch control circuit directly controls the constant-current driving tubes NM _1 and NM _2, and the sensitivity of VREXT short circuit detection is further improved.
The sampling voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS (P-channel metal oxide semiconductor) transistor PM _3, the source electrode of the PMOS transistor PM _3 is connected with a high level, the drain electrode of the PMOS transistor PM _3 is grounded by being connected with the current source Ib in series, the drain electrode of the PMOS transistor PM _3 is connected with the input end of a trigger SMIT1, and the output end of the trigger SMIT1 is used as the judgment output port; the output end of the flip-flop SMIT1 is connected with the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected with one input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected with the digital output reset signal, and the output end of the NAND gate NAND2 is used as a judgment delay output port. The trigger SMIT1 is a schmitt trigger.
Specifically, the PMOS transistor PM _3, the current source Ib, the schmitt trigger SMIT1, the switch SW1, the delay circuit DLY1, and the NAND gate NAND2 constitute a switch control circuit. PMOS transistor PM _3 and current source Ib constitute current comparator, and under normal circumstances, sampling voltage VS is lower level, and output Short _ b is high level, and after schmitt trigger reversal, Short is the low level, and switch SW1 disconnection, NMOS pipe NM _1 and NMOS pipe NM _2 constitute the current mirror amplification, output current drive LED lamp pearl. When a Short circuit occurs to a VREXT pin, the voltage VS of the sampling voltage is raised, the output Short _ b jumps to a low level, after the Short level is reversed by a Schmidt trigger SMIT1, the Short level is a high level, a switch SW1 is closed, namely, the VG2 output by the operational amplifier OP2 is connected to the ground through the switch SW1, the grids of an NMOS tube NM _1 and an NMOS tube NM _2 are pulled to a low level, the current for driving the LED lamp bead is closed, and the LED lamp bead burning caused by the Short circuit of the VREXT pin is avoided. The Short passes through the delay circuit, outputs Short _ dly, is input to the nand gate along with the Por _ dig signal, and outputs the signal Short _ dly _ b that controls the switch SW2 for use as a control signal for the switch SW 2. When the VREXT pin is short-circuited, the switch SW2 is switched off after time delay, so that the purpose of saving electricity can be achieved. The Por _ dig signal is a power-on reset signal Por or a soft reset signal after fixed time timing, and is used for restarting the current of the short-circuit detection branch circuit of the VREXT pin when the VREXT pin is recovered to be normally connected with a proper external resistor to the ground.
Preferably, the current amplifying circuit includes an operational amplifier OP2, an operational amplifier OP3, a PMOS transistor PM _2, a switch SW1, an NMOS transistor NM _1, an NMOS transistor NM _2, and an NMOS transistor NM _ 3;
the bias voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS tube PM _2, the source electrode of the PMOS tube PM _2 is connected with a high level, the drain electrode of the PMOS tube PM _2 is connected with the drain electrode of an NMOS tube NM _1, the drain electrode of the PMOS tube PM _2 is also connected with the reverse input end of an operational amplifier OP2, the homodromous input end of the operational amplifier OP2 is connected with a second reference voltage, the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _1, and the source electrode of the NMOS tube NM _1 is grounded;
the drain electrode of the PMOS tube PM _2 is connected with the equidirectional input end of the operational amplifier OP3, the output end of the operational amplifier OP3 is connected with the grid electrode of the NMOS tube NM _3, the source electrode of the NMOS tube NM _3 is connected with the drain electrode of the NMOS tube NM _2, the source electrode of the NMOS tube NM _3 is connected with the reverse input end of the operational amplifier OP3, the source electrode of the NMOS tube NM _2 is grounded, and the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _ 2;
the judgment output port of the switch control circuit is connected with the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected with the output end of the operational amplifier OP 2;
the drain electrode of the NMOS tube NM _3 is connected to the output end of the LED driving chip; the enable terminal of the operational amplifier OP3 serves as the third input terminal of the current amplifying circuit.
Specifically, the second reference voltage Vref2 is a reference voltage of the output current amplification circuit. Operational amplifier OP2, operational amplifier OP3, PMOS pipe PM _2, NMOS pipe NM _1, NMOS pipe NM _2 and NMOS pipe NM _3 constitute current amplification circuit, and the OUT output of current amplification circuit drives LED lamp pearl. The PMOS transistor PM _2 converts the input bias voltage VG1 into a constant current source input, and the NMOS transistor NM _1 and the NMOS transistor NM _2 form a current amplification function. The operational amplifier OP2 is used for providing a stable source-drain voltage VDS1 for the NMOS transistor NM _1, the operational amplifier OP3 is used for providing a stable source-drain voltage VDS2 for the NMOS transistor NM _2, the drain and source voltages of the NMOS transistor NM _1 and the NMOS transistor NM _2 are equal, the performance is stable and reliable, and the output constant current effect can be effectively improved.
The enabling end en of the OP3 is output and controlled by a digital output reset signal output port controlled by a digital control storage circuit, and when a VREXT pin is short-circuited, the PWM output is closed, so that the power consumption of the LED driving chip can be further reduced.
Referring to fig. 4, the operational amplifier OP3 includes an inverter INV1, a PMOS transistor PM _21, a PMOS transistor PM _22, a PMOS transistor PM _23, a PMOS transistor PM _24, a PMOS transistor PM _25, a PMOS transistor PM _26, an NMOS transistor NM _21, an NMOS transistor NM _22, an NMOS transistor NM _23, an NMOS transistor NM _24, a current source I3, and a current source I2;
the grid electrode of the PMOS pipe PM _21 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _22 is used as the homodromous input end of the operational amplifier; the source electrode of the PMOS tube PM _21 and the source electrode of the PMOS tube PM _22 are both connected to the drain electrode of the PMOS tube PM _24, the source electrode of the PMOS tube PM _24 is connected with the high level, the grid electrode of the PMOS tube PM _24 is connected with the grid electrode of the PMOS tube PM _23, the source electrode of the PMOS tube PM _23 is connected with the high level, the drain electrode of the PMOS tube PM _23 is grounded through the current source I3 in series, and the grid electrode of the PMOS tube PM _23 is connected to the drain electrode of the PMOS tube PM _ 23;
the drain electrode of the PMOS tube PM _21 is connected with the drain electrode of the NMOS tube NM _21, the source electrode of the NMOS tube NM _21 is grounded, and the drain electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 21; the drain electrode of the PMOS tube PM _22 is connected with the drain electrode of the NMOS tube NM _22, the source electrode of the NMOS tube NM _22 is grounded, and the grid electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 22;
the node between the drain of the PMOS tube PM _22 and the drain of the NMOS tube NM _22 is connected with the gate of the NMOS tube NM _23, the source of the NMOS tube NM _23 is grounded, the drain of the NMOS tube NM _23 is connected with the drain of the PMOS tube PM _26, the source of the PMOS tube PM _26 is connected with the drain of the PMOS tube PM _25, the source of the PMOS tube PM _25 is connected with the high level, the gate of the PMOS tube PM _26 is connected with the gate of the PMOS tube PM _23, the enable end of the operational amplifier OP3 is connected with the input end of the inverter INV1, the output end of the inverter INV1 is connected with the gate of the PMOS tube PM _25, the output end of the inverter INV1 is connected with the gate of the NMOS tube NM _24, the source of the NMOS tube NM _24 is grounded through the current source I2 connected in series, the drain of the NMOS tube NM _24 is connected with the drain of the NMOS.
Specifically, EN is an enable terminal, and ENB _ INT is generated through the inverter INV1, controlling the PMOS transistor PM _25 and the NMOS transistor NM _ 25. OP3 is turned on when EN is high, whereas OP3 is turned off when EN is low. In + and In-are the In-phase and inverted inputs, respectively, of OP3, and OUT is the output of OP 3. The size of the current source I3 can be adjusted through a register, so that the opening speed of the OP3 is adjusted. The size of the current source I2 can be adjusted through a register, so that the turn-off speed of the OP3 is adjusted. R1 is a current limiting resistor for preventing overshoot during the process of turning on the lamp bead.
For a brief description, the circuit provided by the embodiment of the present invention may refer to the corresponding content in the foregoing embodiments.
Example three:
an LED driving chip comprises the LED short circuit detection circuit.
Specifically, this LED driver chip can set up a plurality of OUT output for drive a plurality of LED lamp pearls, preferably, the number scope of OUT output can be 1 ~ 32.
Specifically, when the LED driving chip is used, the VREXT end needs to be externally connected with a power supply, and also needs to be externally connected with a resistor REXT to ground, so as to adjust the voltage input value of the VREXT end through the resistor REXT. The output end OUT is connected with the cathode of the LED lamp bead to drive the LED lamp bead. The LED driving chip solves the defect that in the prior art, the LED lamp bead is easy to burn out due to the short circuit of the VREXT end of the LED driving chip.
For a brief description, the chip provided by the embodiment of the present invention may refer to the corresponding content in the foregoing embodiments.
Example four:
an LED driving method, executed on the LED short detection circuit, as shown in fig. 5, includes the following steps:
s1: the first reference voltage is input into a configurable voltage source, a judgment delay signal of the switch control circuit is input into the configurable voltage source through a judgment delay output port, and external voltage generated by a VREXT end of the LED driving chip is input into the configurable voltage source;
s2: the configurable voltage source generates sampling voltage, and the sampling voltage is transmitted to the switch control circuit through the sampling voltage output end;
s3: the configurable voltage source generates bias voltage and transmits the bias voltage to the current amplification circuit through the bias voltage output end;
s4: the current amplification circuit converts the bias voltage into current and amplifies the current to generate driving current of the LED lamp bead;
s5: the digital output reset signal of the digital control storage circuit is input to the switch control circuit through a digital output reset signal output port;
s6: the switch control circuit outputs a judgment signal according to the received sampling voltage and transmits the judgment signal to the current amplification circuit through a judgment output port; the judging signal is used for controlling the current amplifying circuit to output the driving current or not;
s7: the switch control circuit transmits a judgment signal to the digital control storage circuit, and the digital control storage circuit closes the short circuit detection branch current according to the judgment signal and the power-on reset signal.
Specifically, according to the LED driving method, a first reference voltage Vref1 and a delayed and inverted judgment delay signal Short _ dly _ b are input into a configurable voltage source, and a resistor REXT is connected to the ground through the outside of a VREXT end to generate a VREXT voltage. The configurable voltage source outputs a sampling voltage VS to the switch control circuit, the switch control circuit outputs a judgment signal Short whether to close the NMOS tube NM _1 and NM _2 of the LED constant-current driving tube, the operational amplifier and the digital control storage circuit, and the Short signal is input to the configurable voltage source after being delayed and reversed. When the switch control circuit detects that the VREXT pin is short-circuited, the short-circuit detection branch circuit (the switch SW2) is closed, and the power consumption of the LED driving chip is reduced.
The switch control circuit outputs a judgment signal Short to the digital control storage circuit, when the digital control storage circuit detects that a VREXT pin is Short-circuited, the PWM output port outputs a pulse width modulation signal which is pulled down, and meanwhile, the Short-circuit detection branch current is closed, so that the purpose of saving power is achieved to the maximum extent.
The configurable voltage source outputs a bias voltage VG1 to the current amplification circuit, the current amplification circuit is used for generating a driving current of the LED lamp bead, and the driving current is a constant current driving signal.
The LED short circuit detection method solves the defect that in the prior art, an LED lamp bead is easy to burn out due to the short circuit of the VREXT end of an LED driving chip, and achieves the VREXT short circuit detection of the LED driving chip with low power consumption and the self-recovery control function.
For the sake of brief description, the method provided by the embodiment of the present invention may refer to the corresponding contents in the foregoing embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention, and they should be construed as being included in the following claims and description.

Claims (10)

1. An LED short-circuit detection circuit is characterized by comprising a configurable voltage source, a switch control circuit, a digital control storage circuit and a current amplification circuit;
the configurable voltage source is used for generating sampling voltage and bias voltage and respectively transmitting the sampling voltage and the bias voltage to the switch control circuit and the current amplification circuit;
the current amplification circuit is used for converting the bias voltage into current and amplifying the current to generate the driving current of the LED lamp bead; the current amplifying circuit is also used for judging whether to output the driving current or not after receiving the judging signal;
the switch control circuit is used for outputting a judgment signal after receiving the sampling voltage and transmitting the judgment signal to the current amplification circuit; the switch control circuit is also used for transmitting the judgment signal to the digital control storage circuit;
and the digital control storage circuit is used for closing the short-circuit detection branch current according to the judgment signal and the power-on reset signal.
2. The LED short detection circuit of claim 1,
the input end of the configurable voltage source is connected with a first reference voltage, a VREXT end of the LED driving chip and a judgment delay output port of the switch control circuit, the bias voltage output end of the configurable voltage source is connected with the first input end of the current amplifying circuit, and the sampling voltage output end of the configurable voltage source is connected with the first input end of the switch control circuit;
the second input end of the switch control circuit is connected with the digital output reset signal output port of the digital control storage circuit, and the judgment output port of the switch control circuit is connected to the second input end of the current amplification circuit;
the judgment output port of the switch control circuit is connected with the first input end of the digital control storage circuit, the second input end of the digital control storage circuit is connected with a power-on reset signal, the third input end of the digital control storage circuit is connected with an external control signal, and the PWM output port of the digital control storage circuit is connected with the third input end of the current amplification circuit;
and the fourth input end of the current amplifying circuit is connected with the second reference voltage, and the output end of the current amplifying circuit is connected with the output end of the LED driving chip.
3. The LED short detection circuit of claim 2,
the judgment delay output port of the switch control circuit is obtained by delaying and reversing the judgment output port of the switch control circuit.
4. The LED short detection circuit of claim 2,
the configurable voltage source comprises an operational amplifier OP1, a PMOS tube PM _1, an NMOS tube NM _4 and a switch SW 2;
the first reference voltage is connected to the equidirectional input end of an operational amplifier OP1, the VREXT end of the LED driving chip is connected to the inverted input end of an operational amplifier OP1 through a series resistor RINT1, the middle node of the resistor RINT1 and the VREXT end of the LED driving chip is connected with the drain electrode of an NMOS tube NM _4, and the source electrode and the grid electrode of the NMOS tube NM _4 are grounded;
the output end of the operational amplifier OP1 is connected to the gate of the PMOS tube PM _1, the source of the PMOS tube PM _1 is connected to the high level, the drain of the PMOS tube PM _1 is connected to one contact end of the switch SW2, the other contact end of the switch SW2 is connected in series with the resistor RINT2 and is connected to the middle node of the resistor RINT1 and the VREXT end of the LED driving chip, and the control end of the switch SW2 is connected to the judgment delay output port of the switch control circuit;
the detection end of the operational amplifier OP1 is used as the sampling voltage output end of the configurable voltage source, and the output end of the operational amplifier OP1 is used as the bias voltage output end of the configurable voltage source.
5. The LED short detection circuit of claim 4,
the operational amplifier OP1 comprises a PMOS tube PM _11, a PMOS tube PM _12, a PMOS tube PM _13, a PMOS tube PM _14, a PMOS tube PM _15, an NMOS tube NM _11, an NMOS tube NM _12, an NMOS tube NM _13 and an NMOS tube NM _ 14;
the grid electrode of the PMOS tube PM _15 is connected with a reference power supply, the drain electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _11 and PM _12, the source electrodes of the PMOS tubes PM _15 are connected to the source electrodes of the PMOS tubes PM _13 and PM _14, the drain electrode of the PMOS tube PM _13 is connected with the drain electrode of the NMOS tube NM _13, the drain electrode of the PMOS tube PM _14 is connected with the drain electrode of the NMOS tube NM _14, the grid electrode of the NMOS tube NM _13 is connected with the grid electrode of the NMOS tube NM _14, the source electrode of the NMOS tube NM _13 is connected with the drain electrode of the NMOS tube NM _11, the source electrode of the NMOS tube NM _14 is connected with the drain electrode of the NMOS tube NM _12, and the; the drain electrode of the PMOS tube PM _11 is connected with the drain electrode of the NMOS tube NM _11, and the drain electrode of the PMOS tube PM _12 is connected with the drain electrode of the NMOS tube NM _ 12;
a node between the drain electrode of the PMOS tube PM _14 and the drain electrode of the NMOS tube NM _14 is used as the output end of the operational amplifier; the grid electrode of the PMOS tube PM _11 is used as the homodromous input end of the operational amplifier; the grid electrode of the PMOS pipe PM _12 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _13, the grid electrode of the PMOS pipe PM _14 and the middle nodes of the drain electrode of the PMOS pipe PM _13 and the drain electrode of the NMOS pipe NM _13 are connected with each other to be used as the detection end of the operational amplifier.
6. The LED short detection circuit of claim 2,
the switch control circuit comprises a PMOS tube PM _3, a current source Ib, a trigger SMIT1, a delay circuit DLY1 and a NAND gate NAND 2;
the sampling voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS (P-channel metal oxide semiconductor) transistor PM _3, the source electrode of the PMOS transistor PM _3 is connected with a high level, the drain electrode of the PMOS transistor PM _3 is grounded by being connected with the current source Ib in series, the drain electrode of the PMOS transistor PM _3 is connected with the input end of a trigger SMIT1, and the output end of the trigger SMIT1 is used as the judgment output port; the output end of the flip-flop SMIT1 is connected with the input end of the delay circuit DLY1, the output end of the delay circuit DLY1 is connected with one input end of the NAND gate NAND2, the other input end of the NAND gate NAND2 is connected with the digital output reset signal, and the output end of the NAND gate NAND2 is used as a judgment delay output port.
7. The LED short detection circuit of claim 2,
the current amplification circuit comprises an operational amplifier OP2, an operational amplifier OP3, a PMOS tube PM _2, a switch SW1, an NMOS tube NM _1, an NMOS tube NM _2 and an NMOS tube NM _ 3;
the bias voltage output end of the configurable voltage source is connected to the grid electrode of a PMOS tube PM _2, the source electrode of the PMOS tube PM _2 is connected with a high level, the drain electrode of the PMOS tube PM _2 is connected with the drain electrode of an NMOS tube NM _1, the drain electrode of the PMOS tube PM _2 is also connected with the reverse input end of an operational amplifier OP2, the homodromous input end of the operational amplifier OP2 is connected with a second reference voltage, the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _1, and the source electrode of the NMOS tube NM _1 is grounded;
the drain electrode of the PMOS tube PM _2 is connected with the equidirectional input end of the operational amplifier OP3, the output end of the operational amplifier OP3 is connected with the grid electrode of the NMOS tube NM _3, the source electrode of the NMOS tube NM _3 is connected with the drain electrode of the NMOS tube NM _2, the source electrode of the NMOS tube NM _3 is connected with the reverse input end of the operational amplifier OP3, the source electrode of the NMOS tube NM _2 is grounded, and the output end of the operational amplifier OP2 is connected with the grid electrode of the NMOS tube NM _ 2;
the judgment output port of the switch control circuit is connected with the control end of the switch SW1, one contact end of the switch SW1 is grounded, and the other contact end of the switch SW1 is connected with the output end of the operational amplifier OP 2;
the drain electrode of the NMOS tube NM _3 is connected to the output end of the LED driving chip; the enable terminal of the operational amplifier OP3 serves as the third input terminal of the current amplifying circuit.
8. The LED short detection circuit of claim 7,
the operational amplifier OP3 comprises an inverter INV1, a PMOS transistor PM _21, a PMOS transistor PM _22, a PMOS transistor PM _23, a PMOS transistor PM _24, a PMOS transistor PM _25, a PMOS transistor PM _26, an NMOS transistor NM _21, an NMOS transistor NM _22, an NMOS transistor NM _23, an NMOS transistor NM _24, a current source I3 and a current source I2;
the grid electrode of the PMOS pipe PM _21 is used as the reverse input end of the operational amplifier; the grid electrode of the PMOS pipe PM _22 is used as the homodromous input end of the operational amplifier; the source electrode of the PMOS tube PM _21 and the source electrode of the PMOS tube PM _22 are both connected to the drain electrode of the PMOS tube PM _24, the source electrode of the PMOS tube PM _24 is connected with the high level, the grid electrode of the PMOS tube PM _24 is connected with the grid electrode of the PMOS tube PM _23, the source electrode of the PMOS tube PM _23 is connected with the high level, the drain electrode of the PMOS tube PM _23 is grounded through the current source I3 in series, and the grid electrode of the PMOS tube PM _23 is connected to the drain electrode of the PMOS tube PM _ 23;
the drain electrode of the PMOS tube PM _21 is connected with the drain electrode of the NMOS tube NM _21, the source electrode of the NMOS tube NM _21 is grounded, and the drain electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 21; the drain electrode of the PMOS tube PM _22 is connected with the drain electrode of the NMOS tube NM _22, the source electrode of the NMOS tube NM _22 is grounded, and the grid electrode of the NMOS tube NM _21 is connected with the grid electrode of the NMOS tube NM _ 22;
the node between the drain of the PMOS tube PM _22 and the drain of the NMOS tube NM _22 is connected with the gate of the NMOS tube NM _23, the source of the NMOS tube NM _23 is grounded, the drain of the NMOS tube NM _23 is connected with the drain of the PMOS tube PM _26, the source of the PMOS tube PM _26 is connected with the drain of the PMOS tube PM _25, the source of the PMOS tube PM _25 is connected with the high level, the gate of the PMOS tube PM _26 is connected with the gate of the PMOS tube PM _23, the enable end of the operational amplifier OP3 is connected with the input end of the inverter INV1, the output end of the inverter INV1 is connected with the gate of the PMOS tube PM _25, the output end of the inverter INV1 is connected with the gate of the NMOS tube NM _24, the source of the NMOS tube NM _24 is grounded through the current source I2 connected in series, the drain of the NMOS tube NM _24 is connected with the drain of the NMOS.
9. An LED driving chip is characterized in that,
the LED short-circuit detection circuit comprises the LED short-circuit detection circuit as claimed in any one of claims 1-8.
10. An LED driving method, performed on the LED short detection circuit of any one of claims 1 to 8, comprising the steps of:
the first reference voltage is input into a configurable voltage source, a judgment delay signal of the switch control circuit is input into the configurable voltage source through a judgment delay output port, and external voltage generated by a VREXT end of the LED driving chip is input into the configurable voltage source;
the configurable voltage source generates sampling voltage, and the sampling voltage is transmitted to the switch control circuit through the sampling voltage output end;
the configurable voltage source generates bias voltage and transmits the bias voltage to the current amplification circuit through the bias voltage output end;
the current amplification circuit converts the bias voltage into current and amplifies the current to generate driving current of the LED lamp bead;
the digital output reset signal of the digital control storage circuit is input to the switch control circuit through a digital output reset signal output port;
the switch control circuit outputs a judgment signal according to the received sampling voltage and transmits the judgment signal to the current amplification circuit through a judgment output port; the judging signal is used for controlling the current amplifying circuit to output the driving current or not;
the switch control circuit transmits a judgment signal to the digital control storage circuit, and the digital control storage circuit closes the short circuit detection branch current according to the judgment signal and the power-on reset signal.
CN201911126739.6A 2019-11-18 2019-11-18 LED short-circuit detection circuit, driving chip and driving method Pending CN110719670A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115561560A (en) * 2022-10-21 2023-01-03 南京信息工程大学 Pure hardware implementation control circuit and control method for power device aging test
CN117354996A (en) * 2023-02-02 2024-01-05 上海谭慕半导体科技有限公司 Control system and method for LED driver, and readable storage medium
CN117354996B (en) * 2023-02-02 2024-05-14 上海谭慕半导体科技有限公司 Control system and method for LED driver, and readable storage medium

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130313973A1 (en) * 2012-05-22 2013-11-28 Texas Instruments Incorporated Led bypass and control circuit for fault tolerant led systems
US20140021979A1 (en) * 2012-07-19 2014-01-23 Fairchild Semiconductor Corporation Circuit and method for overcurrent detection of power switch
CN106550508A (en) * 2016-10-31 2017-03-29 北京集创北方科技股份有限公司 LED drive device and control method and its protection circuit and control method
CN109859681A (en) * 2019-03-28 2019-06-07 北京集创北方科技股份有限公司 A kind of LED display driver circuit, display, driving method and driving chip
CN210807747U (en) * 2019-11-18 2020-06-19 深圳市富满电子集团股份有限公司 LED short circuit detection circuit and driving chip

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130313973A1 (en) * 2012-05-22 2013-11-28 Texas Instruments Incorporated Led bypass and control circuit for fault tolerant led systems
US20140021979A1 (en) * 2012-07-19 2014-01-23 Fairchild Semiconductor Corporation Circuit and method for overcurrent detection of power switch
CN106550508A (en) * 2016-10-31 2017-03-29 北京集创北方科技股份有限公司 LED drive device and control method and its protection circuit and control method
CN109859681A (en) * 2019-03-28 2019-06-07 北京集创北方科技股份有限公司 A kind of LED display driver circuit, display, driving method and driving chip
CN210807747U (en) * 2019-11-18 2020-06-19 深圳市富满电子集团股份有限公司 LED short circuit detection circuit and driving chip

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115561560A (en) * 2022-10-21 2023-01-03 南京信息工程大学 Pure hardware implementation control circuit and control method for power device aging test
CN115561560B (en) * 2022-10-21 2023-09-22 南京信息工程大学 Pure hardware implementation control circuit and control method for power device aging test
CN117354996A (en) * 2023-02-02 2024-01-05 上海谭慕半导体科技有限公司 Control system and method for LED driver, and readable storage medium
CN117354996B (en) * 2023-02-02 2024-05-14 上海谭慕半导体科技有限公司 Control system and method for LED driver, and readable storage medium

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