WO2023130499A1

WO2023130499A1 - Bandgap reference circuit

Info

Publication number: WO2023130499A1
Application number: PCT/CN2022/072219
Authority: WO
Inventors: 雒超; 薛棋文; 郭国平
Original assignee: 中国科学技术大学
Priority date: 2022-01-10
Filing date: 2022-01-17
Publication date: 2023-07-13
Also published as: CN114326906A; CN114326906B

Abstract

Provided in the present disclosure is a bandgap reference circuit, which bandgap reference circuit comprises a current-mode bandgap reference circuit and a starting circuit, wherein the current-mode bandgap reference circuit is connected to a power source; and the starting circuit is configured to convert, when the current-mode bandgap reference circuit is powered on, the current-mode bandgap reference circuit into a voltage-mode structure for starting, and after the current-mode bandgap reference circuit is started, the starting circuit is configured to restore the current-mode bandgap reference circuit to a current-mode structure to work normally.

Description

A bandgap reference circuit

technical field

The present disclosure relates to the technical field of analog circuits in integrated circuits, in particular to a bandgap reference circuit.

Background technique

In the field of integrated circuit design, especially analog circuit design, most circuits require a stable bias, so the design of a bandgap reference circuit is a top priority in the design of integrated circuit systems. The existing bandgap reference circuits are mainly divided into two types: voltage mode and current mode. The voltage-mode bandgap reference generates a negative temperature coefficient voltage by superimposing a negative temperature coefficient current on the resistor and then adding it to the triode Vbe to obtain a zero temperature coefficient voltage. The voltage-mode bandgap reference theoretically produces a fixed voltage value, about 1.25V, so when the power supply voltage is close to or lower than 1.25V, the voltage-mode bandgap reference will no longer be applicable. The current mode circuit directly adds the positive temperature coefficient current and the negative temperature coefficient current, and then flows through the resistor to generate a zero temperature coefficient voltage, which can be applied to a low power supply voltage environment, and the generated voltage can be changed by modifying the resistance value of the resistor . With the gradual development of CMOS technology, the power supply voltage is getting lower and lower, so the current mode bandgap reference circuit is more and more widely used.

Bandgap reference circuits often have multiple degeneracy points in the circuit, that is, the circuit can be stable in multiple states, so the bandgap reference circuit must contain a start-up circuit module, which can help the bandgap reference circuit to stabilize smoothly to normal working status. Among them, the voltage-mode bandgap reference circuit generally has only two operating points: non-start and normal operation, so the design of the voltage-mode bandgap reference start-up circuit is simple and can stably help the circuit to work normally. However, the current-mode bandgap reference circuit generally has three or more degeneracy points, and it is difficult to design the start-up circuit and it is difficult to have strong robustness. In the design of the previous process, because the power supply voltage is high, the voltage-mode bandgap reference is used more, so the design of the bandgap reference start-up circuit is mostly focused on the voltage mode, and the related research on the current-mode bandgap reference start-up circuit is less.

In 1999, Banba et al. published the paper "A CMOS bandgap reference circuit with sub-1-V operation" in "IEEE Journal of solid-State Circuits" and proposed the current mode bandgap reference structure, but did not discuss the design of the start-up circuit ; In 2002, Ka Nang Leung et al. published a paper "A sub-1-V 15-ppm//spl deg/C CMOS bandgap voltage reference without requiring low threshold voltage device" on "IEEE Journal of solid-State Circuits", However, its starting circuit still adopts the structure similar to the voltage mode starting circuit, and the process fluctuation will affect its normal operation, and the robustness to the current mode structure is very poor; in 2007, Keith Sanboen et al. published in "IEEE Journal of solid-State Circuits" The paper "A Sub-1-V Low-Noise Bandgap Voltage Reference", but its circuit mode structure is relatively unique, and the startup circuit is not suitable for conventional current mode bandgap reference circuits; in 2005, Xu Changxi published in "Chinese Journal of Semiconductors" Published the paper "A Low Voltage and LowPower CMOS BandgapVoltage Reference Design with a Novel Start-up Circuit" to design the start-up circuit for the circuit mode bandgap reference, but additionally introduced multiple triodes, which greatly increased the chip area; in 2015, Chengyue Yu Published the paper "An Area-Efficient Current-Mode Bandgap Reference With Intrinsic Robust Start-Up Behavior" in "IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS", reducing a bypass resistor and modifying the current mirror ratio to help the current mode bandgap The gap reference circuit starts, which makes it difficult to determine the feedback strength of the two loops of the circuit, and the circuit is prone to instability.

public content

One aspect of the present disclosure provides a bandgap reference circuit. The above-mentioned bandgap reference circuit includes a current-mode bandgap reference circuit and a start-up circuit. The current-mode bandgap reference circuit is connected to the power supply; the start-up circuit is configured to convert the current-mode bandgap reference circuit into a voltage-mode structure to start when the current-mode bandgap reference circuit is powered on, and to enable all The current mode bandgap reference circuit returns to the normal operation of the current mode structure.

Optionally, the startup circuit includes: a conversion module, a detection and adjustment module, a pull-down module, and a current supply module.

A conversion module, including a conversion input terminal and a conversion output terminal connected to the current-mode bandgap reference circuit, the conversion module is configured to convert the startup process of the current-mode bandgap reference circuit into a voltage-mode structure startup; The adjustment module includes a detection and adjustment input terminal, a detection and adjustment first output terminal, and a detection and adjustment second output terminal, wherein the detection and adjustment input terminal is connected to the conversion output terminal, and the detection and adjustment second output terminal is connected to the Power connection; the detection and adjustment module is configured to detect the voltage state of the conversion output terminal of the conversion module, and adjust the output voltage of the detection and adjustment second output terminal; the pull-down module includes a pull-down input terminal and a pull-down output terminal, wherein the The pull-down input terminal is connected to the detection adjustment first output terminal, and the pull-down output terminal is connected to the current-mode bandgap reference circuit; the pull-down module is configured to reduce the voltage in the current-mode bandgap reference circuit; and A current supply module, including a current supply input terminal and a current supply output terminal, wherein the current supply input terminal is connected to the detection and adjustment first output terminal, and the current supply output terminal is connected to the current mode bandgap circuit; The current supply module is configured to provide additional current to the current mode bandgap reference circuit.

Optionally, the current-mode bandgap reference circuit includes: an operational amplifier, a first triode branch, a second triode branch, a first resistor branch, a second resistor branch, and a first MP group.

Optionally, the first triode branch circuit includes a triode, the emitter of the triode is connected to the negative input terminal of the operational amplifier, and the base and collector of the triode are grounded; the second three The transistor branch circuit includes eight transistors and a resistor R1, the eight transistors are connected in parallel, the emitter of the parallel connected transistor is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the operational amplifier The positive input terminal of each transistor is connected, and the base and collector of each triode are grounded; the first resistance branch circuit includes a resistor R2b, and one end of the resistor R2b is connected to the negative input terminal of the operational amplifier, and the resistor R2b The other end is grounded through the first NMOS switch tube; and the second resistor branch includes a resistor R2a, one end of the resistor R2a is connected to the positive input end of the operational amplifier, and the other end of the resistor R2a is connected through the second NMOS switch pipe to ground.

Optionally, the first MP group includes: a first PMOS transistor and a second PMOS transistor.

A first PMOS transistor, the gate of the first PMOS transistor is connected to the output terminal of the operational amplifier, the drain of the first PMOS transistor is connected to the first triode branch, and the first PMOS transistor is connected to the first triode branch. The source of the tube is connected to the power supply; the second PMOS tube, the gate of the second PMOS tube is connected to the output terminal of the operational amplifier, and the drain of the second PMOS tube is connected to the second triode The tube branch is connected, and the source of the second PMOS tube is connected to the power supply.

Optionally, the converting module includes: a voltage comparator and a first MN group.

The positive input terminal of the voltage comparator is connected to the near power supply end of the resistor R1 in the second triode branch, and the negative input terminal of the voltage comparator is connected to the resistor R1 in the second triode branch. connected to the near-ground end; the first MN group includes: a first NMOS switch tube and a second NMOS switch tube. The drain of the first NMOS switch is connected to the first resistor branch, the gate of the first NMOS switch is connected to the output terminal of the voltage comparator, and the source of the first NMOS switch is grounded; The drains of the two NMOS switch tubes are connected to the second resistor branch, the gates of the second NMOS switch tubes are connected to the output terminal of the voltage comparator, and the source electrodes of the second NMOS switch tubes are grounded; The voltage comparator is used to control the opening and closing of the first NMOS switch tube and the second NMOS switch tube.

Optionally, the detection and adjustment module includes: a detection NMOS transistor and a second MP group. The gate of the detection NMOS transistor is connected to the output terminal of the voltage comparator, the source of the detection NMOS transistor is grounded, and the detection NMOS transistor is configured to detect the output voltage of the conversion module; the second MP group includes a fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube are connected in series in sequence, and the source of one end of the series connected PMOS tube is connected to the Power connection, the drain of the other end of the series connected PMOS transistor is connected to the drain of the detection NMOS transistor, the gate of each PMOS transistor is grounded; the detection NMOS transistor is connected to the second MP group In cooperation, it is configured to adjust the output voltage between the detection NMOS transistor and the second MP group.

Optionally, the current supply module includes: a current supply NMOS transistor and a current mirror. The gate of the current supply NMOS transistor is connected to the drain of the detection NMOS transistor, and the source of the current supply NMOS transistor is grounded; the current mirror includes: an eighth PMOS transistor and a ninth PMOS transistor. The gate of the eighth PMOS transistor is connected to the drain of the current supply NMOS transistor, the drain of the eighth PMOS transistor is connected to the drain of the current supply NMOS transistor, and the source of the eighth PMOS transistor The pole is connected to the power supply; the gate of the ninth PMOS transistor is connected to the drain of the current supply NMOS transistor, and the drain of the ninth PMOS transistor is connected to the first triode of the current mode bandgap reference circuit The branch is connected, and the source of the ninth PMOS transistor is connected to the power supply.

Optionally, the pull-down module includes: a pull-down NMOS transistor, the gate of the pull-down NMOS transistor is connected to the drain of the detection NMOS transistor, the source of the pull-down NMOS transistor is grounded, and the drain of the pull-down NMOS transistor is connected to the drain of the detection NMOS transistor. The gates of each PMOS transistor in the first MP group are connected; the pull-down NMOS transistor is configured to reduce the gate voltage of each PMOS transistor in the first MP group, so that each branch of the current-mode bandgap reference circuit generates current.

Optionally, the current-mode bandgap reference circuit further includes a capacitor, one end of the capacitor is connected to the power supply, and the other end of the capacitor is connected to the output port of the operational amplifier, configured to compensate the bandgap reference loop The phase margin of the circuit and stabilize the voltage between the gate terminal and the source terminal of the first MP group 12 .

The start-up circuit of the present disclosure converts the start-up process of the current-mode bandgap reference circuit into a simple voltage-mode structure start-up, which greatly increases the stability of the circuit; the present disclosure can detect the current state of the triode branch in real time through the comparator, even if the circuit is due to Other external factors have entered the abnormal working point, and the comparator can quickly judge the state and then resume the normal operation of the circuit, which greatly enhances the robustness of the bandgap reference circuit; the working process of the startup circuit of the present disclosure mainly receives high and low level signals , so it is not sensitive to process changes. Compared with most existing current-mode start-up circuits, it does not need to detect the output reference voltage and is not limited by the size of the reference voltage, so it has extremely high applicability.

Description of drawings

FIG. 1 is a schematic diagram of the composition and working principle of a bandgap reference circuit according to an embodiment of the present disclosure;

2 is a circuit structure diagram of a current mode bandgap reference circuit according to an embodiment of the present disclosure;

3 is a circuit structure diagram when the current-mode bandgap reference circuit is converted to a voltage-mode structure and started according to an embodiment of the present disclosure;

4 is an overall structural diagram of a bandgap reference circuit according to an embodiment of the present disclosure;

5 is a circuit structure diagram of a voltage comparator according to an embodiment of the disclosure;

FIG. 6 is a circuit structure diagram of an operational amplifier according to an embodiment of the disclosure;

FIG. 7 is a transient simulation result of power-on of the bandgap reference circuit according to an embodiment of the present disclosure;

FIG. 8 is the result of 500 Monte Carlo simulations of the bandgap reference circuit according to an embodiment of the present disclosure;

FIG. 9 is a temperature characteristic curve of a bandgap reference current according to an embodiment of the disclosure.

Reference signs:

1: Current-mode bandgap reference circuit

2: Start circuit

3: Conversion module

4: Detection and adjustment module

5: Pull-down module

6: Flow supply module

7: The first triode branch

8: The second triode branch

9: The first resistance branch

10: The second resistance branch

11: The third resistance branch

12: The first MP group

13: Operational amplifier

14: Voltage Comparator

15: The first MN group

MN1: the first NMOS switch tube

MN2: the second NMOS switch tube

MN3: Detect NMOS tube

MN4: pull down NMOS tube

MN5: NMOS tube for flow

MP1: the first PMOS tube

MP2: the second PMOS tube

MP3: the third PMOS tube

MP4: the fourth PMOS tube

MP5: Fifth PMOS tube

MP6: the sixth PMOS tube

MP7: the seventh PMOS tube

MP8: Eighth PMOS tube

MP9: ninth PMOS tube

MP21: PMOS input tube

MP11: PMOS input tube

MN11: the first NMOS turn-on switch

MN21: The second NMOS turns on the switch tube

MP21: The first PMOS input tube

MP11: The second PMOS input tube

C1: capacitance

Detailed ways

Embodiments of the present disclosure will be further described below in conjunction with the accompanying drawings.

The present disclosure provides a bandgap reference circuit, and Fig. 1 schematically shows the composition and working principle of the bandgap reference circuit according to an embodiment of the present disclosure.

As shown in FIG. 1 , the bandgap reference circuit includes a current mode bandgap reference circuit 1 and a start-up circuit 2 .

A current-mode bandgap reference circuit 1 connected to a power supply;

The start-up circuit 2 is configured to switch the current-mode bandgap reference circuit 1 to a voltage-mode structure for startup when the current-mode bandgap reference circuit 1 is powered on, and to restore the current-mode bandgap reference circuit 1 to a current-mode structure after startup normal work.

The configuration of the start-up circuit 2 will be described in detail as follows. The starting circuit 2 includes a conversion module 3 , a detection and adjustment module 4 , a pull-down module 5 and a current supply module 6 .

The conversion module 3 includes a conversion input terminal and a conversion output terminal both connected to the current-mode bandgap reference circuit 1, and the conversion module 3 is configured to convert the startup process of the current-mode bandgap reference circuit 1 into a voltage-mode configuration startup.

The detection and adjustment module 4 includes a detection and adjustment input end, a detection and adjustment first output end and a detection and adjustment second output end, wherein the detection and adjustment input end is connected to the conversion output end, and the detection and adjustment second output end is connected to the power supply; the detection and adjustment module 4 is configured to detect the voltage state of the converted output terminal of the conversion module 3, and adjust the output voltage of the detected and adjusted second output terminal.

The pull-down module 5 includes a pull-down input terminal and a pull-down output terminal, wherein the pull-down input terminal is connected to the first output terminal of the detection adjustment, and the pull-down output terminal is connected to the current-mode bandgap reference circuit 1; the pull-down module 5 is configured to reduce the current-mode bandgap the voltage in the reference circuit 1;

The current supply module 6 includes a current supply input terminal and a current supply output terminal, wherein the current supply input terminal is connected to the first output terminal of detection and adjustment, and the current supply output terminal is connected to the current mode bandgap circuit; the current supply module 6 is configured to provide A current-mode bandgap reference circuit 1 provides additional current.

The working process of the starting circuit 2 is described in detail as follows. After the current-mode bandgap reference circuit 1 is powered on, the conversion module 3 receives the voltage signal from the current-mode bandgap reference circuit 1, the conversion module 3 converts the current-mode bandgap reference circuit 1 into a voltage-mode structure to start, and the detection and adjustment module 4 receives To the voltage signal from the conversion module 3, the detection and adjustment module 4 outputs the voltage signal to the pull-down module 5 and the current supply module 6, the pull-down module 5 pulls down the voltage inside the current mode bandgap reference circuit 1, and the current supply module 6 supplies the current mode bandgap The reference circuit 1 provides additional current, and the pull-down module 5 and the current supply module 6 work together to restore the current-mode bandgap reference circuit 1 to the normal operation of the current-mode structure.

FIG. 2 schematically shows a circuit structure diagram of a current-mode bandgap reference circuit according to an embodiment of the present disclosure.

As shown in Figure 2, the current mode bandgap reference circuit 1 includes: an operational amplifier 13, a first triode branch 7, a second triode branch 8, a first resistance branch 9, and a second resistance branch 10 , the third resistor branch 11 and the first MP group 12 .

The structure of each branch in the current-mode bandgap reference circuit 1 is described in detail as follows.

The first transistor branch 7 includes a transistor Q1, the emitter of the transistor Q1 is connected to the negative input terminal of the operational amplifier 13, and the base and collector of the transistor Q1 are grounded.

The second triode branch circuit 8 includes a triode group Q2 and a resistor R1, the triode group Q2 includes eight triodes and the eight triodes are connected in parallel, the emitter of the paralleled triode group Q2 is connected to one end of the resistor R1, and the resistor R1 The other end of the transistor is connected to the positive input of the operational amplifier 13, and the base and collector of each transistor in the transistor group Q2 are grounded.

The first resistance branch 9 includes a resistance R2b, one end of the resistance R2b is connected to the negative input end of the operational amplifier 13, and the other end of the resistance R2b is grounded through the first NMOS switch MN1; and

The second resistor branch 10 includes a resistor R2a, one end of the resistor R2a is connected to the positive input end of the operational amplifier 13, and the other end of the resistor R2a is grounded through the second NMOS switch MN2.

The third resistor branch 11 includes a resistor R3, one end of the resistor R3 is connected to the first MP group 12, and the other end of the resistor R3 is grounded.

The structure of the first MP group 12 in the current mode bandgap reference circuit 1 will be described in detail as follows. The first MP group 12 includes a first PMOS transistor MP1 , a second PMOS transistor MP2 , a third PMOS transistor MP3 and a fourth PMOS transistor MP4 .

The first PMOS transistor MP1, the gate of the first PMOS transistor MP1 is connected to the output terminal of the operational amplifier 13, the drain of the first PMOS transistor MP1 is connected to the first triode branch 7, and the source of the first PMOS transistor MP1 Connect to power supply.

The second PMOS transistor MP2, the grid of the second PMOS transistor MP2 is connected to the output terminal of the operational amplifier 13, the drain of the second PMOS transistor MP2 is connected to the second transistor branch 8, and the source of the second PMOS transistor MP2 Connect to power supply.

The gate of the third PMOS transistor MP3 is connected to the output terminal of the operational amplifier 13, and the source electrode of the third PMOS transistor MP3 is connected to the power supply; and

The gate of the fourth PMOS transistor MP4 is connected to the output terminal of the operational amplifier 13 , and the source of the fourth PMOS transistor MP4 is connected to the power supply.

FIG. 3 schematically shows a circuit structure diagram when the current-mode bandgap reference circuit 1 of the embodiment of the present disclosure is switched to a voltage-mode structure and started.

FIG. 4 schematically shows the overall design of the bandgap reference circuit of the embodiment of the present disclosure.

As shown in FIG. 4 , the conversion module 3 includes a voltage comparator 14 and a first MN group 15 .

The positive input terminal of the voltage comparator 14 is connected with the near power supply end of the resistor R1 in the second triode branch circuit 8, and the negative input terminal of the voltage comparator 14 is connected with the near terminal of the resistor R1 in the second triode branch circuit 8. ground connection.

The structure of the first MN group 15 will be described in detail as follows.

As shown in FIG. 4 , the first MN group 15 includes: a first NMOS switch MN1 and a second NMOS switch MN2 .

The drain of the first NMOS switch MN1 is connected to the first resistor branch 9, the gate of the first NMOS switch MN1 is connected to the output terminal of the voltage comparator 14, and the source of the first NMOS switch MN1 is grounded; and

The drain of the second NMOS switch MN2 is connected to the second resistor branch 10 , the gate of the second NMOS switch MN2 is connected to the output terminal of the voltage comparator 14 , and the source of the second NMOS switch MN2 is grounded.

According to an embodiment of the present disclosure, the current mode bandgap reference circuit 1 further includes a capacitor C1, one end of the capacitor C1 is connected to the power supply, and the other end of the capacitor C1 is connected to the output port of the operational amplifier 13, configured to compensate the phase of the bandgap reference loop margin and stabilize the voltage between the gate terminal and the source terminal of the first MP group 12 .

According to an embodiment of the present disclosure, the voltage comparator 14 is used to control the opening and closing of the first NMOS switch MN1 and the second NMOS switch MN2 .

When the current mode bandgap reference circuit 1 is powered on, the voltage comparator 14 judges the voltage difference between the two ends of the resistor R1 in the second triode branch 8, and when the current mode bandgap reference circuit 1 is powered on The terminal voltage difference is 0. At this time, the voltage comparator 14 will output a low level, that is, the level that does not meet the working level of the first NMOS switch tube MN1 and the second NMOS switch tube MN2, so that the first NMOS switch tube MN1 and the second NMOS switch tube MN1 and the second NMOS switch tube MN1 are controlled. The NMOS switch tube MN2 is in the disconnected state, so that the first resistance branch 9 and the second resistance branch 10 in the current mode bandgap reference circuit 1 are in the disconnected state. At this time, the current mode bandgap reference circuit 1 is converted into a voltage mode The start of the structure is shown in Figure 3.

As shown in FIG. 4 , the detection and adjustment module 4 includes a detection NMOS transistor MN3 and a second MP group.

Detecting that the gate of the NMOS transistor MN3 is connected to the output terminal of the voltage comparator 14, detecting that the source of the NMOS transistor MN3 is grounded, and detecting that the NMOS transistor MN3 is configured to detect the output voltage of the conversion module 3; and

The second MP group includes the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are connected in series in sequence, and the PMOS transistors after the series The source of one end is connected to the power supply, the drain of the other end of the series connected PMOS transistors is connected to the drain of the detection NMOS transistor MN3, and the gates of each PMOS transistor are grounded.

The detection NMOS transistor MN3 cooperates with the second MP group, and is configured to adjust the output voltage between the detection NMOS transistor MN3 and the second MP group.

The drain of the detection tube MN3 is connected to the power supply VDD through the second MP group, the drain of the detection tube MN3 and the second MP group are connected with the current supply NMOS transistor MN5 and the pull-down NMOS transistor MN4, and the source of the detection tube MN3 is grounded. MN3 is turned off when power is first turned on, and the second MP group is in a conducting state because the gate terminal is grounded. At this time, the voltage between the detection tube MN3 and the second MP group is a high voltage, which satisfies the requirements of the current supply NMOS transistor MN5 and the pull-down NMOS transistor MN5. The working voltage of the tube MN4, and then make the current supply NMOS tube MN5 and the pull-down NMOS tube MN4 work.

As shown in FIG. 4 , the current supply module 6 includes: a current supply NMOS transistor MN5 and a current mirror.

The gate of the current supply NMOS transistor MN5 is connected to the drain of the detection NMOS transistor MN3, and the source of the current supply NMOS transistor MN5 is grounded.

The current mirror includes: an eighth PMOS transistor MP8 and a ninth PMOS transistor MP9.

The gate of the eighth PMOS transistor MP8 is connected to the drain of the current supply NMOS transistor MN5, the drain of the eighth PMOS transistor MP8 is connected to the drain of the current supply NMOS transistor MN5, and the source of the eighth PMOS transistor MP8 is connected to the power supply; as well as

The gate of the ninth PMOS transistor MP9 is connected to the drain of the current supply NMOS transistor MN5, the drain of the ninth PMOS transistor MP9 is connected to the branch 7 of the current mode bandgap reference circuit 1, and the source of the ninth PMOS transistor MP9 is connected to power connection.

As shown in Figure 4, the pull-down module 5 includes a pull-down NMOS transistor MN4, the gate of the pull-down NMOS transistor MN4 is connected to the drain of the detection NMOS transistor MN3, the source of the pull-down NMOS transistor MN4 is grounded, and the drain of the pull-down NMOS transistor MN4 is connected to the first drain of the NMOS transistor MN4. The gates of each PMOS transistor in the first MP group 12 are connected; the pull-down NMOS transistor MN4 is configured to reduce the gate terminal voltage of each PMOS transistor in the first MP group 12 , so that each branch of the current-mode bandgap reference circuit 1 generates current.

According to the embodiment of the present disclosure, after detecting the high level output from the drain end of the NMOS transistor MN3, the level at which the pull-down NMOS transistor MN4 and the current supply NMOS transistor MN5 can work is satisfied, the pull-down NMOS transistor MN4 is turned on, and the pull-down NMOS transistor MN4 continues to pull down the current mode. The gate voltage of each PMOS transistor in the first MP group 12 in the bandgap reference circuit 1, and the current supply module 6 also injects current into the current mode bandgap reference circuit 1 to accelerate the startup of the circuit, and then the triode Q1 and the triode group Q2 successfully opened.

In the embodiment of the present disclosure, after the triode Q1 and the triode group Q2 are successfully turned on, there is a relatively large voltage difference between the two ends of the resistor R1 on the second triode branch 8, which is the voltage that meets the voltage comparator 14's flipping requirement. The voltage comparator 14 outputs the switching voltage from low level to high level, that is, the working voltage of the first NMOS switch MN1 and the second NMOS switch MN2.

In the embodiment of the present disclosure, after the first NMOS switch MN1 and the second NMOS switch MN2 in the current mode bandgap reference circuit 1 are turned on, the first resistance branch 9 and the second resistance branch 10 generate a current, that is, the current The mode bandgap reference circuit 1 returns to the current mode structure; at the same time, the NMOS transistor MN3 detects that the output voltage of the voltage comparator 14 is at a high level, and the output voltage at the drain end of the NMOS transistor MN3 is detected to be at a low level, that is, the pull-down NMOS transistor is not satisfied. The working level of MN4 and the current supply NMOS transistor MN5 makes the pull-down NMOS transistor MN4 and the current supply NMOS transistor MN5 turn off, the gate voltage of each PMOS transistor in the first MP group 12 stops falling and the input of additional current is stopped, and the circuit is started 2 no longer affect the normal operation of the bandgap reference circuit.

In the embodiment of the present disclosure, the ratio of the number of triodes in the first triode branch 7 and the second triode branch 8 is 1:8, the voltage difference ΔVbe across R1 is about 57mV, and the first resistance branch After 9 and the second resistor branch 10 are reconnected to the bandgap reference circuit, the first NMOS switch tube MN1 and the second NMOS switch tube MN2 are large-scale switch tubes, so there is basically no voltage consumption, and the first resistor branch 9 and Each of the second resistor branches 10 generates a current of Vbe1/R2b, wherein Vbe1 is the voltage between the base and the emitter of the transistor Q1.

According to the embodiment of the present disclosure, if the current mode bandgap reference circuit enters the third degeneracy point due to some unstable factors during the working process, that is, the first triode branch 7 and the second triode branch 8 have no current, The first resistance branch 9 and the second resistance branch 10 have a current, and the voltage comparator 14 can detect this state, and output a low level, that is, it does not meet the requirements for the first NMOS switch MN1 and the second NMOS switch MN2 to work. The voltage, so that the current in the first resistance branch 9 and the second resistance branch 10 is temporarily disconnected from the bandgap reference circuit, and the whole bandgap reference starts again to enter the normal operating point.

According to the embodiment of the present disclosure, the voltage comparator 14 adopts a high-inversion voltage comparator to prevent output inversion when the voltage difference between the two ends of the resistor is 0 or a small voltage difference due to leakage current, wherein the inversion threshold is not greater than that in the bandgap reference circuit. The difference ΔVbe between the Vbe1 of the transistor Q1 and the Vbe2 of the transistor group Q2 is desirable but not limited to 1/2 or 2/3 of ΔVbe, where Vbe1 is the voltage between the base and the emitter of the transistor Q1, and Vbe2 is the base voltage of the transistor Q2. The voltage between the electrode and the emitter.

5 is a circuit structure diagram of a voltage comparator according to an embodiment of the disclosure; as shown in FIG. 5 , compared with a conventional five-tube open-loop comparator, the W/ L is inconsistent, the W/L of the first PMOS input transistor MP21 is greater than the W/L of the second PMOS input transistor MP11, so that when |Vgs2|<|Vgs1|, the current carrying capacity of the first PMOS input transistor MP21 is higher than that of the second PMOS The input tube MP11 is stronger and realizes the reversal of the output voltage. Among them, W/L is the ratio of the channel width to the length of the MOS tube, Vgs1 is the voltage difference between the gate terminal and the source terminal of MP11, and Vgs2 is the voltage difference between the gate terminal and the source terminal of MP21. |Vgs1|-|Vgs2| is the flipping voltage.

In the embodiment of the present disclosure, the voltage comparator 14 flipping voltage is designed to be about 35mV, and the voltage difference between the two ends of R1 is ΔVbe (57mV), so that after the triode Q1 and the triode group Q2 are turned on, the output of the voltage comparator 14 can be flipped normally, so that the first The NMOS turns on the switch tube and the second NMOS turns on the switch tube, and the reversal voltage of 35mV is also large enough to ensure that the voltage comparator 14 will not misjudge the circuit state due to non-ideal factors such as leakage current.

Combined with Figures 6 to 8, it shows that even if the process changes and the circuit is mismatched, the circuit can work normally, and the circuit has strong robustness due to the addition of the start-up circuit.

FIG. 9 is a temperature characteristic curve of the bandgap reference current of an embodiment of the present disclosure. As shown in FIG. 9 , the reference current changes very little in the range of -40°C-120°C, and the temperature coefficient is 44ppm/°C.

The specific implementation manners of the present disclosure described above are not intended to limit the protection scope of the present disclosure. Any other corresponding changes and modifications made according to the technical concepts of the present disclosure shall be included in the protection scope of the claims of the present disclosure.

Claims

A bandgap reference circuit comprising:

a current-mode bandgap reference circuit connected to a power supply; and

A start-up circuit (2), configured to convert the current-mode bandgap reference circuit (1) into a voltage-mode structure to start when the current-mode bandgap reference circuit (1) is powered on, and to enable the current The mode bandgap reference circuit (1) returns to the normal operation of the current mode structure.
The bandgap reference circuit according to claim 1, wherein the startup circuit (2) comprises:

A conversion module (3), including a conversion input terminal and a conversion output terminal connected to the current-mode bandgap reference circuit (1), and the conversion module (3) is configured to power on the current-mode bandgap reference circuit (1) When the start-up process is converted into a voltage-mode structure start-up;

A detection and adjustment module (4), including a detection and adjustment input terminal, a detection and adjustment first output terminal, and a detection and adjustment second output terminal, wherein the detection and adjustment input terminal is connected to the conversion output terminal, and the detection and adjustment second output terminal The terminal is connected to the power supply; the detection and adjustment module (4) is configured to detect the voltage state of the conversion output terminal of the conversion module (3), and adjust the output voltage of the detection and adjustment second output terminal;

A pull-down module (5), comprising a pull-down input terminal and a pull-down output terminal, wherein the pull-down input terminal is connected to the first detection and adjustment output terminal, and the pull-down output terminal is connected to the current mode bandgap reference circuit (1) connected; the pull-down module (5) is configured to lower the voltage in the current-mode bandgap reference circuit (1); and

A current supply module (6), comprising a current supply input terminal and a current supply output terminal, wherein the current supply input terminal is connected to the first detection and adjustment output terminal, and the current supply output terminal is connected to the current mode bandgap Circuit connection; the current supply module (6) is configured to provide additional current to the current mode bandgap reference circuit (1).
The bandgap reference circuit according to claim 2, wherein the current mode bandgap reference circuit (1) comprises: an operational amplifier (13), a first triode branch (7), a second triode branch Road (8), first resistance branch (9), second resistance branch (10), and first MP group (12).
The bandgap reference circuit of claim 3, wherein:

The first triode branch (7) includes a triode, the emitter of the triode is connected to the negative input terminal of the operational amplifier (13), and the base and collector of the triode are grounded;

The second triode branch (8) includes eight triodes and a resistor (R1), the eight triodes are connected in parallel, the emitter of the parallel connected triode and one end of the resistor (R1), The other end of the resistor (R1) is connected to the positive input of the operational amplifier (13), and the base and collector of each triode are grounded;

The first resistance branch (9) includes a resistance (R2b), one end of the resistance (R2b) is connected to the negative input end of the operational amplifier (13), and the other end of the resistance (R2b) passes through the first NMOS The switching tube (MN1) is grounded; and

The second resistance branch (10) includes a resistance (R2a), one end of the resistance (R2a) is connected to the positive input end of the operational amplifier (13), and the other end of the resistance (R2a) passes through the second NMOS The switch tube (MN2) is grounded.
The bandgap reference circuit according to claim 4, wherein said first MP group (12) comprises:

A first PMOS transistor (MP1), the gate of the first PMOS transistor (MP1) is connected to the output terminal of the operational amplifier (13), and the drain of the first PMOS transistor (MP1) is connected to the first The triode branch (7) is connected, and the source of the first PMOS transistor (MP1) is connected to the power supply; and

A second PMOS transistor (MP2), the gate of the second PMOS transistor (MP2) is connected to the output terminal of the operational amplifier (13), and the drain of the second PMOS transistor (MP2) is connected to the second The triode branch (8) is connected, and the source of the second PMOS transistor (MP2) is connected with the power supply.
The bandgap reference circuit according to any one of claims 2-5, wherein the conversion module (3) comprises:

A voltage comparator (14), the positive input terminal of the voltage comparator (14) is connected to the near power supply end of the resistor (R1) in the second triode branch (8), and the voltage comparator ( 14) the negative input terminal is connected with the near-ground end of the resistor (R1) in the second transistor branch (8); and

The first MN group (15), the first MN group (15) includes:

The first NMOS switch tube (MN1), the drain of the first NMOS switch tube (MN1) is connected to the first resistance branch (9), and the gate of the first NMOS switch tube (MN1) is connected to the voltage The output terminal of the comparator (14) is connected, and the source of the first NMOS switch (MN1) is grounded; and

The second NMOS switch tube (MN2), the drain of the second NMOS switch tube (MN2) is connected to the second resistor branch (10), and the gate of the second NMOS switch tube (MN2) is connected to the voltage The output terminal of the comparator (14) is connected, and the source of the second NMOS switch (MN2) is grounded;

The voltage comparator (14) is used to control the opening and closing of the first NMOS switch tube (MN1) and the second NMOS switch tube (MN2).
The bandgap reference circuit according to any one of claims 2-5, wherein the detection and adjustment module (4) comprises:

Detect the NMOS transistor (MN3), the gate of the detected NMOS transistor (MN3) is connected to the output terminal of the voltage comparator (14), the source of the detected NMOS transistor (MN3) is grounded, and the detected NMOS transistor (MN3) ) configured to detect the output voltage of the conversion module (3); and

The second MP group includes a fifth PMOS transistor (MP5), a sixth PMOS transistor (MP6) and a seventh PMOS transistor (MP7), the fifth PMOS transistor (MP5), the sixth PMOS transistor (MP6) and The seventh PMOS transistor (MP7) is connected in series in sequence, the source of one end of the connected PMOS transistor is connected to the power supply, and the drain of the other end of the connected PMOS transistor is connected to the detection NMOS transistor ( The drain of MN3) is connected, and the gate of each PMOS transistor is grounded;

The detection NMOS transistor (MN3) cooperates with the second MP group, and is configured to adjust the output voltage between the detection NMOS transistor (MN3) and the second MP group.
The bandgap reference circuit according to any one of claims 2-5, wherein the current supply module (6) comprises:

A current supply NMOS transistor (MN5), the gate of the current supply NMOS transistor (MN5) is connected to the drain of the detection NMOS transistor (MN3), and the source of the current supply NMOS transistor (MN5) is grounded;

current mirrors, including:

An eighth PMOS transistor (MP8), the gate of the eighth PMOS transistor (MP8) is connected to the drain of the current supply NMOS transistor (MN5), and the drain of the eighth PMOS transistor (MP8) is connected to the drain of the eighth PMOS transistor (MP8). The drain of the current supply NMOS transistor (MN5) is connected, and the source of the eighth PMOS transistor (MP8) is connected to the power supply; and

A ninth PMOS transistor (MP9), the gate of the ninth PMOS transistor (MP9) is connected to the drain of the current supply NMOS transistor (MN5), and the drain of the ninth PMOS transistor (MP9) is connected to the drain of the ninth PMOS transistor (MP9). The first transistor branch (7) of the current mode bandgap reference circuit (1) is connected, and the source of the ninth PMOS transistor (MP9) is connected with the power supply.
The bandgap reference circuit according to any one of claims 2-5, wherein the pull-down module (5) comprises: a pull-down NMOS transistor (MN4), the grid of the pull-down NMOS transistor (MN4) is connected to the detection NMOS transistor The drain of (MN3) is connected, the source of the pull-down NMOS transistor (MN4) is grounded, and the drain of the pull-down NMOS transistor (MN4) is connected to the grid of each PMOS transistor in the first MP group (12); The pull-down NMOS transistor (MN4) is configured to lower the gate voltage of each PMOS transistor in the first MP group (12), thereby causing each branch of the current-mode bandgap reference circuit (1) to generate current.
The bandgap reference circuit according to claim 3, wherein the current mode bandgap reference circuit (1) further comprises a capacitor (C1), one end of the capacitor (C1) is connected to the power supply, and the capacitor ( The other end of C1) is connected to the output port of the operational amplifier (13), configured to compensate the phase margin of the bandgap reference loop and stabilize the voltage between the gate terminal and the source terminal of the first MP group (12).