CN110718261A - Memory bank management method and system - Google Patents
Memory bank management method and system Download PDFInfo
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- CN110718261A CN110718261A CN201910775868.1A CN201910775868A CN110718261A CN 110718261 A CN110718261 A CN 110718261A CN 201910775868 A CN201910775868 A CN 201910775868A CN 110718261 A CN110718261 A CN 110718261A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
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Abstract
The invention relates to a memory bank management method and a memory bank management system. According to the embodiment of the invention, the logical address of the inferior memory particle in the memory strip is acquired, the logical address is analyzed to obtain the physical address corresponding to the inferior memory particle, the display interface corresponding to the memory particle is generated according to the physical parameters of the memory strip, the display area corresponding to each memory particle is displayed on the display interface, and the display parameter of the display area corresponding to the inferior memory particle in the display interface is adjusted according to the physical address corresponding to the inferior memory particle, so that the display parameter of the display area corresponding to the inferior memory particle is inconsistent with the display parameter of the normal memory particle, and a worker can quickly determine the position of the memory particle with a problem according to real-time display data, thereby facilitating the user to process.
Description
Technical Field
The present invention relates to the field of memory bank management technologies, and in particular, to a memory bank management method and system.
Background
Memory is one of the important components in a computer, and it is the bridge to communicate with the CPU. All programs in the computer are executed in the memory, so the performance of the memory has a great influence on the computer. A Memory (Memory) is also called an internal Memory and a main Memory, and functions to temporarily store operation data in a CPU and data exchanged with an external Memory such as a hard disk. As long as the computer is in operation, the CPU transfers data to be operated to the memory for operation, and after the operation is finished, the CPU transmits the result, and the operation of the memory also determines the stable operation of the computer.
However, in the using process of the memory, the memory grain may be damaged, and if the memory grain is damaged in one physical block, the 64-bit data transmission fails, and the stable operation of the computer is affected by the loss of the data.
Disclosure of Invention
In order to solve the problems in the prior art, at least one embodiment of the present invention provides a memory bank management method and system.
In a first aspect, an embodiment of the present invention provides a memory bank management method, where the management method includes:
acquiring a logic address of the inferior memory particle in the memory bank;
analyzing the logic address to obtain a physical address of the inferior memory particle;
generating a display interface corresponding to the memory particles according to the physical parameters of the memory bank;
determining a display area of the inferior memory particles on the display interface according to the physical address;
and adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with those of the normal memory particles.
Based on the above technical solutions, the embodiments of the present invention may be further improved as follows.
With reference to the first aspect, in a first embodiment of the first aspect, the analyzing the logical address to obtain the physical address of the bad memory granule includes:
converting the logical address into a binary number;
and according to a pre-stored query rule, acquiring the physical block where the inferior memory particles are located and the position of the inferior memory particles on the physical block according to the binary number.
With reference to the first aspect, in a second embodiment of the first aspect, the generating a display interface corresponding to the memory granule according to the physical parameter of the memory bank includes:
acquiring physical parameters of the memory bank, wherein the physical parameters comprise: the number of physical blocks and the number of memory granules in each physical block;
dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks;
and aiming at each group of the sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area which is displayed corresponding to the memory particles.
With reference to the second embodiment of the first aspect, in a third embodiment of the first aspect, the determining a display area of the bad memory particles on the display interface according to the physical address includes:
confirming a sub-display interface where the inferior particles are located according to the physical block where the inferior particles are located in the physical address;
and confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
With reference to the first aspect or the first, second or third embodiment of the first aspect, in a fourth embodiment of the first aspect, the adjusting the display parameters of the display area of the poor-quality memory particle, where the display parameters of the poor-quality memory particle are not consistent with the display parameters of the normal memory particle, includes:
adjusting the display color of the display area corresponding to the poor-quality memory particles;
and the display colors of the display areas corresponding to the poor-quality memory particles and the normal memory particles are inconsistent.
In a second aspect, an embodiment of the present invention provides a memory bank management system, where the management system includes:
the obtaining unit is used for obtaining the logic address of the inferior memory particle in the memory bank;
the first processing unit is used for analyzing the logic address to obtain a physical address of the inferior memory particle;
the display unit is used for generating a display interface corresponding to the memory particles according to the physical parameters of the memory bars;
the second processing unit is used for determining a display area of the inferior memory particles on the display interface according to the physical address;
and the adjusting unit is used for adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with the display parameters of the normal memory particles.
With reference to the second aspect, in a first embodiment of the second aspect, the first processing unit is specifically configured to convert the logical address into a binary number; and according to a pre-stored query rule, acquiring the physical block where the inferior memory particles are located and the position of the inferior memory particles on the physical block according to the binary number.
With reference to the second aspect, in a second embodiment of the second aspect, the display unit is specifically configured to acquire physical parameters of the memory bank, where the physical parameters include: the number of physical blocks and the number of memory granules in each physical block; dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks; and aiming at each group of the sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area which is displayed corresponding to the memory particles.
With reference to the second embodiment of the second aspect, in a third embodiment of the second aspect, the second processing unit is specifically configured to confirm, according to a physical block where a bad particle is located in the physical address, a sub-display interface where the bad particle is located; and confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
With reference to the second aspect or the first, second, or third embodiment of the second aspect, in a fourth embodiment of the second aspect, the adjusting unit is specifically configured to adjust a display color of a display area corresponding to the poor-quality memory particle; and the display colors of the display areas corresponding to the poor-quality memory particles and the normal memory particles are inconsistent.
Compared with the prior art, the technical scheme of the invention has the following advantages: according to the embodiment of the invention, the logical address of the inferior memory particle in the memory strip is acquired, the logical address is analyzed to obtain the physical address corresponding to the inferior memory particle, the display interface corresponding to the memory particle is generated according to the physical parameters of the memory strip, the display area corresponding to each memory particle is displayed on the display interface, and the display parameter of the display area corresponding to the inferior memory particle in the display interface is adjusted according to the physical address corresponding to the inferior memory particle, so that the display parameter of the display area corresponding to the inferior memory particle is inconsistent with the display parameter of the normal memory particle, and a worker can quickly determine the position of the memory particle with a problem according to real-time display data, thereby facilitating the user to process.
Drawings
Fig. 1 is a schematic flow chart illustrating a memory bank management method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart illustrating a memory bank management method according to another embodiment of the present invention;
fig. 3 is a first flowchart illustrating a memory bank management method according to another embodiment of the present invention;
fig. 4 is a second flowchart illustrating a memory bank management method according to another embodiment of the present invention;
fig. 5 is a schematic structural diagram of a memory bank management system according to another embodiment of the present invention;
fig. 6 is an internal structural diagram of a computer device according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
As shown in fig. 1, an embodiment of the invention provides a memory bank management method. Referring to fig. 1, the management method includes the steps of:
and S11, acquiring the logic address of the bad memory grain in the memory bank.
In this embodiment, the memory bank is composed of a memory chip, a circuit board, a gold finger, and the like, and the logical address refers to an address of a memory cell (memory cell), a storage cell (storage element), and a network host (network host) seen from an application program in a computer architecture, and the poor memory particle may cause data stored or read by the memory particle to be lost, and it may be determined whether the memory particle is the poor memory particle according to a data loss condition.
And S12, analyzing the logic address to obtain the physical address of the poor-quality memory particle.
In this embodiment, the logical address is used for processing to obtain the physical address where the damaged memory granule is located, where the logical address is analyzed to obtain the physical data such as the transmission Channel where the memory granule is located, the Slot position where the memory granule is located, and the physical block where the memory granule is located, for example, bits 8 to 13 of the logical address can determine the Channel where the memory granule is located, bits 15 to 20 of the logical address can determine the Slot where the memory granule is located, and bits 5 to 8 of the logical address can determine the rank where the memory granule is located. The Channel is a memory bank Channel on the mainboard, the Slot is a Slot of each Channel, and rank is the number of faces of the memory bank module.
And S13, generating a display interface corresponding to the memory particles according to the physical parameters of the memory bars.
In this embodiment, the physical parameters of the memory bank include: the number of physical blocks included in the memory bank and the number of memory granules in each physical block, for example, the interface bit width between the CPU and the memory is 64 bits, which means that the CPU sends or reads 64 bits of data to or from the memory in one clock cycle. However, a single memory granule may be only 4, 8 or 16 bits wide, and individually 32 bits wide. Therefore, a plurality of particles are connected in parallel to form a data set with a bit width of 64 bits, the data set can be interconnected with a CPU, a manufacturer refers the 64bit set to be a physical block, the number of memory particles in the physical block is determined by the bit width of the memory particles, in order to ensure the communication between the memory and the CPU, at least one physical block is required in a memory module, a display interface corresponding to the memory particles is generated according to physical parameters of the memory, a rectangular interface with a preset size can be averagely divided according to the number of the physical blocks of the memory, for example, the number of the physical blocks is 2, the interface is divided into two halves to obtain 2 rectangular small interfaces, the number of the physical blocks is 4, the interfaces are divided into 4 rectangular small interfaces with the same size, display areas are uniformly arranged in each small interface according to the number of the memory particles in the physical block, each display area corresponds to one memory particle, the order of the small interfaces is the order of the physical blocks in the memory, the order of the display areas corresponds to the order of the memory particles in the physical blocks, and the manner for generating the display interface is only a specific implementation manner, and other display interfaces can be generated according to other arrangement manners.
And S14, determining the display area of the bad memory particles on the display interface according to the physical address.
In this embodiment, the physical address obtained in the above steps is used to determine the display area corresponding to the poor-quality memory particle on the display interface.
And S15, adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with the display parameters of the normal memory particles.
In this embodiment, the display parameters of the poor memory particles and the normal memory particles are not consistent by adjusting the display parameters of the display region corresponding to the poor memory particles, for example, adjusting the display shape of the display region, which may be adjusting the display region from the original shape to another shape, for example, from a rectangle to a star, or adjusting the display color of the display region, for example, adjusting the color of the display region from green to red, or adjusting the size of the display region, although the above adjustment modes may be performed simultaneously, and the display region corresponding to the poor memory particles and the display region corresponding to the normal memory particles are distinguished, so that the worker can quickly determine the display region corresponding to the memory particles with problems, and determine the position of the problem in the memory according to the position of the display region on the display interface, to perform corresponding processing.
For example, as shown in fig. 2, in this embodiment, resolving the logical address to obtain the physical address of the bad memory granule may include the following steps:
and S21, converting the logic address into a binary number.
In the actual memory test, when a memory error occurs, software only records the current error-reporting logical address, i.e. a 16-ary address, for example: the 0xF1670AF9C converts the hexadecimal logical address into a corresponding binary number, and resolves the logical address.
And S22, according to a pre-stored query rule, acquiring the physical block where the inferior memory particle is located and the position on the physical block according to the binary number.
In this embodiment, the query rule is determined according to the setting of the parameters in the memory, where the setting of the parameters is already set when the memory leaves the factory, for example, information such as the arrangement mode of the memory granules, the bit width of the memory granules, the number of physical blocks in the memory, and the like, and an area corresponding to the logical address of the memory granules set by a manufacturer, and the physical block where the corresponding memory granule is located and the arrangement position on the physical block are obtained through binary numbers.
Specifically, resolving the corresponding physical address through the logical address includes the following steps:
the first step is as follows: resolving a Channel address;
the second step is that: resolving a Slot address of a memory Slot;
the third step: and resolving the memory Rank/Bank/Column/Row address.
For example, the following steps are carried out: if the logical address of a memory granule is 1a0007880, it is converted into binary 000110100000000000000111100010000000, and bit8 to bit9 determine the Channel address where the Channel is located, where the Channel is 00b, so that the Channel at 0 th (the few described below, all starting from 0) is identified; bits 14-15 determine the Slot address, where the Slot is 01b, and therefore confirm in Slot 1; bit16 identifies the address where the Rank is located, where Rank is 0b, and therefore is identified at Rank 0; bit7, bit28, bit29 determine the Bank address, where Bank 101b, and thus confirm that it is in Bank 5H; bits 8-bit 16 identified the Column address, where Column is 001111000b, and thus was identified at 78H; bits 17-27 and bits 30-35 determine the Row address, where Row is 0001100000000000b, and thus confirm the 3000H Row. The Channel is a memory bank Channel on the mainboard, the Slot is a Slot of each Channel, rank is the number of faces of the memory bank module, bank is a Channel for exchanging data between the memory and a north bridge chip on the mainboard, Column is a Row where memory particles are located, and Row is a Row where the memory particles are located.
As shown in fig. 3, an embodiment of the present invention provides a memory bank management method. Referring to fig. 3, the management method includes the steps of:
and S31, acquiring the logic address of the bad memory grain in the memory bank.
Regarding step S31, refer to the description in step S11 for details, which are not repeated herein.
And S32, analyzing the logic address to obtain the physical address of the poor-quality memory particle.
Regarding step S32, refer to the description in step S12 for details, which are not repeated herein.
S33, acquiring physical parameters of the memory bank, wherein the physical parameters comprise: the number of physical blocks and the number of memory granules in each physical block.
And S34, dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks.
In this embodiment, the display interface in this step may be a pre-generated display interface, and the display interface is divided according to a preset layout rule according to the physical parameters, for example, the display interface is divided averagely or according to the user habit, and the user habit may include parameters such as a distance between sub display interfaces, a distance between a sub display interface and a frame, and a display size of the sub display interface, so as to obtain the sub display interface corresponding to the number of the physical blocks.
And determining whether the display interface is divided or not according to the number of the physical blocks, when the number of the physical blocks is 1, not dividing the display interface, using the display interface as a sub-display interface displayed by the memory particles, and when the number of the physical blocks is not 1, dividing the display interface.
And S35, aiming at each group of sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area for displaying the corresponding memory particles.
In this embodiment, based on the above steps, each sub-display interface corresponds to a corresponding physical block, each physical block includes a plurality of memory granules, in this step, the sub-display interfaces are divided according to the number of the memory granules, the sub-display interfaces can be divided according to the same rule as that for dividing the display interfaces, and a plurality of display areas with the number identical to that of the memory granules are obtained, where each display area corresponds to one memory granule.
And S36, determining the display area of the bad memory particles on the display interface according to the physical address.
Regarding step S36, refer to the description in step S14 for details, which are not repeated herein.
And S37, adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with the display parameters of the normal memory particles.
Regarding step S37, refer to the description in step S15 for details, which are not repeated herein.
As shown in fig. 4, in this embodiment, determining a display area of the bad memory particle on the display interface according to the physical address includes the following steps:
and S41, confirming the sub-display interface where the inferior particle is located according to the physical block where the inferior particle is located in the physical address.
In this embodiment, the sub-display interfaces in the above embodiments are combined to correspond to the physical blocks, so as to obtain the sub-display interface corresponding to the physical block where the inferior particles are located.
And S42, confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
In this embodiment, the memory particles corresponding to the red display area are displayed in combination with the above embodiment, and the corresponding display area of the inferior particles in the sub-display interface is determined according to the positions of the inferior particles in the physical block.
As shown in fig. 5, an embodiment of the present invention provides a memory bank management system. Referring to fig. 5, the management system includes: the device comprises an acquisition unit, a first processing unit, a display unit, a second processing unit and an adjusting unit.
In this embodiment, the obtaining unit is configured to obtain a logical address of a bad memory granule in a memory bank.
In this embodiment, the memory bank is composed of a memory chip, a circuit board, a gold finger, and the like, and the logical address refers to an address of a memory cell (memory cell), a storage cell (storage element), and a network host (network host) seen from an application program in a computer architecture, and the poor memory particle may cause data stored or read by the memory particle to be lost, and it may be determined whether the memory particle is the poor memory particle according to a data loss condition.
In this embodiment, the first processing unit is configured to analyze the logical address to obtain a physical address of the bad memory granule.
In this embodiment, the logical address is used for processing to obtain the physical address where the damaged memory granule is located, where the logical address is analyzed to obtain the physical data such as the transmission Channel where the memory granule is located, the Slot position where the memory granule is located, and the physical block where the memory granule is located, for example, bits 8 to 13 of the logical address can determine the Channel where the memory granule is located, bits 15 to 20 of the logical address can determine the Slot where the memory granule is located, and bits 5 to 8 of the logical address can determine the rank where the memory granule is located. The Channel is a memory bank Channel on the mainboard, the Slot is a Slot of each Channel, and rank is the number of faces of the memory bank module.
In this embodiment, the display unit is configured to generate a display interface corresponding to the memory granule according to the physical parameter of the memory bank.
In this embodiment, the physical parameters of the memory bank include: the number of physical blocks included in the memory bank and the number of memory granules in each physical block, for example, the interface bit width between the CPU and the memory is 64 bits, which means that the CPU sends or reads 64 bits of data to or from the memory in one clock cycle. However, a single memory granule may be only 4, 8 or 16 bits wide, and individually 32 bits wide. Therefore, a plurality of particles are connected in parallel to form a data set with a bit width of 64 bits, the data set can be interconnected with a CPU, a manufacturer refers the 64bit set to be a physical block, the number of memory particles in the physical block is determined by the bit width of the memory particles, in order to ensure the communication between the memory and the CPU, at least one physical block is required in a memory module, a display interface corresponding to the memory particles is generated according to physical parameters of the memory, a rectangular interface with a preset size can be averagely divided according to the number of the physical blocks of the memory, for example, the number of the physical blocks is 2, the interface is divided into two halves to obtain 2 rectangular small interfaces, the number of the physical blocks is 4, the interfaces are divided into 4 rectangular small interfaces with the same size, display areas are uniformly arranged in each small interface according to the number of the memory particles in the physical block, each display area corresponds to one memory particle, the order of the small interfaces is the order of the physical blocks in the memory, the order of the display areas corresponds to the order of the memory particles in the physical blocks, and the manner for generating the display interface is only a specific implementation manner, and other display interfaces can be generated according to other arrangement manners.
In this embodiment, the second processing unit is configured to determine a display area of the bad memory particle on the display interface according to the physical address.
In this embodiment, the physical address obtained in the above steps is used to determine the display area corresponding to the poor-quality memory particle on the display interface.
In this embodiment, the adjusting unit is configured to adjust display parameters of a display area of the poor memory particles, where the display parameters of the poor memory particles are inconsistent with the display parameters of the normal memory particles.
In this embodiment, the display parameters of the poor memory particles and the normal memory particles are not consistent by adjusting the display parameters of the display region corresponding to the poor memory particles, for example, adjusting the display shape of the display region, which may be adjusting the display region from the original shape to another shape, for example, from a rectangle to a star, or adjusting the display color of the display region, for example, adjusting the color of the display region from green to red, or adjusting the size of the display region, although the above adjustment modes may be performed simultaneously, distinguishing the display region corresponding to the poor memory particles from the display region corresponding to the normal memory particles, so that the x-worker may quickly determine the display region corresponding to the memory particles with problems, and determine the position of the problem in the memory according to the position of the display region in the display interface, to perform corresponding processing.
In this embodiment, the first processing unit is specifically configured to convert a logical address into a binary number; and according to a pre-stored query rule, acquiring the physical block where the inferior memory particles are located and the position of the inferior memory particles on the physical block according to the binary number.
In the actual memory test, when a memory error occurs, software only records the current error-reporting logical address, i.e. a 16-ary address, for example: the 0xF1670AF9C converts the hexadecimal logical address into a corresponding binary number, and resolves the logical address. Determining a query rule according to the setting of parameters in the memory, wherein the setting of the parameters is already set when the memory leaves a factory, for example, information such as the arrangement mode of memory particles, the bit width of the memory particles, the number of physical blocks in the memory and the like, and an area corresponding to a logical address of the memory particles set by a manufacturer, and acquiring the physical block where the corresponding memory particle is located and the arrangement position on the physical block through binary numbers.
An embodiment of the present invention provides a memory bank management system, and compared with the memory bank management method shown in fig. 5, the difference is that the management system includes:
in this embodiment, the display unit is specifically configured to obtain physical parameters of the memory bank, where the physical parameters include: the number of physical blocks and the number of memory granules in each physical block; dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks; and aiming at each group of sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area for displaying the corresponding memory particles.
In this embodiment, the display interface in this step may be a pre-generated display interface, and the display interface is divided according to a preset layout rule according to the physical parameters, for example, the display interface is divided averagely or according to the user habit, and the user habit may include parameters such as a distance between sub display interfaces, a distance between a sub display interface and a frame, and a display size of the sub display interface, so as to obtain the sub display interface corresponding to the number of the physical blocks. And determining whether the display interface is divided or not according to the number of the physical blocks, when the number of the physical blocks is 1, not dividing the display interface, using the display interface as a sub-display interface displayed by the memory particles, and when the number of the physical blocks is not 1, dividing the display interface. In the step, the sub-display interfaces are divided according to the number of the memory particles, the sub-display interfaces can be divided according to the same rule as the divided display interfaces, and a plurality of display areas with the number consistent with the number of the memory particles are obtained, wherein each display area corresponds to one memory particle.
In this embodiment, the second processing unit is specifically configured to determine, according to the physical block where the inferior particle is located in the physical address, the sub-display interface where the inferior particle is located; and confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
In this embodiment, the sub-display interface corresponding to the physical block where the inferior particle is located is obtained by combining the sub-display interface corresponding to the physical block in the above embodiment, the memory particle corresponding to the red display area is displayed by combining the above embodiment, and the display area corresponding to the inferior particle in the sub-display interface is determined according to the position of the inferior particle in the physical block.
FIG. 6 is a diagram illustrating an internal structure of a computer device in one embodiment. The computer device may specifically be a memory bank management system. As shown in fig. 6, the computer apparatus includes a processor, a memory, a network interface, an input device, and a display screen connected through a system bus. Wherein the memory includes a non-volatile storage medium and an internal memory. The non-volatile storage medium of the computer device stores an operating system and may also store a computer program that, when executed by the processor, causes the processor to implement a memory bank management method. The internal memory may also have stored therein a computer program that, when executed by the processor, causes the processor to perform a memory bank management method. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, the memory bank management system provided herein may be implemented in the form of a computer program that is executable on a computing device such as that shown in fig. 6. The memory of the computer device may store various program modules constituting the solid state disk system, such as the acquisition unit, the first processing unit, the display unit, the second processing unit, and the adjustment unit shown in fig. 5. The computer program constituted by the respective program modules causes the processor to execute the steps in the memory bank management method of the embodiments of the present application described in the present specification.
For example, the computer device shown in fig. 6 may perform step S11 through the obtaining unit in the memory bank management system as shown in fig. 5, and the computer device may perform step S12 through the first processing unit.
An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following steps:
acquiring a logic address of an inferior memory particle in a memory bank;
resolving the logical address to obtain the physical address of the inferior memory particle;
generating a display interface corresponding to the memory particles according to the physical parameters of the memory bank;
determining a display area of the inferior memory particles on the display interface according to the physical address;
and adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with the display parameters of the normal memory particles.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, and the program can be stored in a non-volatile computer readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A memory bank management method is characterized by comprising the following steps:
acquiring a logic address of the inferior memory particle in the memory bank;
analyzing the logic address to obtain a physical address of the inferior memory particle;
generating a display interface corresponding to the memory particles according to the physical parameters of the memory bank;
determining a display area of the inferior memory particles on the display interface according to the physical address;
and adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with those of the normal memory particles.
2. The memory bank management method according to claim 1, wherein the parsing the logical address to obtain the physical address of the bad memory granule comprises:
converting the logical address into a binary number;
and according to a pre-stored query rule, acquiring the physical block where the inferior memory particles are located and the position of the inferior memory particles on the physical block according to the binary number.
3. The memory bank management method according to claim 1, wherein the generating a display interface corresponding to memory grains according to the physical parameters of the memory bank comprises:
acquiring physical parameters of the memory bank, wherein the physical parameters comprise: the number of physical blocks and the number of memory granules in each physical block;
dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks;
and aiming at each group of the sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area which is displayed corresponding to the memory particles.
4. The memory bank management method according to claim 3, wherein the determining a display area of the bad memory granules on the display interface according to the physical address comprises:
confirming a sub-display interface where the inferior particles are located according to the physical block where the inferior particles are located in the physical address;
and confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
5. The memory bank management method according to any one of claims 1 to 4, wherein the adjusting the display parameters of the display area of the bad memory particles, wherein the display parameters of the bad memory particles are not consistent with those of the normal memory particles, comprises:
adjusting the display color of the display area corresponding to the poor-quality memory particles;
and the display colors of the display areas corresponding to the poor-quality memory particles and the normal memory particles are inconsistent.
6. A memory bank management system, the management system comprising:
the obtaining unit is used for obtaining the logic address of the inferior memory particle in the memory bank;
the first processing unit is used for analyzing the logic address to obtain a physical address of the inferior memory particle;
the display unit is used for generating a display interface corresponding to the memory particles according to the physical parameters of the memory bars;
the second processing unit is used for determining a display area of the inferior memory particles on the display interface according to the physical address;
and the adjusting unit is used for adjusting the display parameters of the display area of the poor-quality memory particles, wherein the display parameters of the poor-quality memory particles are inconsistent with the display parameters of the normal memory particles.
7. The memory bank management system according to claim 6, wherein the first processing unit is specifically configured to convert the logical address into a binary number; and according to a pre-stored query rule, acquiring the physical block where the inferior memory particles are located and the position of the inferior memory particles on the physical block according to the binary number.
8. The system according to claim 6, wherein the display unit is specifically configured to obtain physical parameters of the memory bank, where the physical parameters include: the number of physical blocks and the number of memory granules in each physical block; dividing the display interface according to the number of the physical blocks to obtain at least one group of sub-display interfaces corresponding to the physical blocks; and aiming at each group of the sub-display interfaces, dividing the sub-display interfaces according to the number of the memory particles to obtain a display area which is displayed corresponding to the memory particles.
9. The system according to claim 8, wherein the second processing unit is specifically configured to determine, according to the physical block where the bad granule is located in the physical address, the sub-display interface where the bad granule is located; and confirming the display area of the inferior particles in the sub-display interface according to the positions of the inferior particles in the physical blocks in the physical addresses.
10. The memory bank management system according to any one of claims 6 to 9, wherein the adjusting unit is specifically configured to adjust a display color of a display area corresponding to the inferior memory particles; and the display colors of the display areas corresponding to the poor-quality memory particles and the normal memory particles are inconsistent.
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