CN113436668A - Method and device for distinguishing product information of multiple memory chips - Google Patents
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention relates to a product information distinguishing method of a plurality of memory chips, which comprises the following steps: initializing a dynamic random access memory chip (S101); acquiring a scanning result of the DRAM controller (S102); reading data of the JEDEC read register (S103); calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the JEDEC register (S104); the measured data of the dynamic random access memory chip are presented in different ways according to different roles and different use scenes (S105). Still relate to a product information of many memory chips and distinguish device, include: the device comprises a user selection module, a reading module, a calculation module, a comparison module and a display module. The invention can accurately measure the related information in the dynamic random access memory, and present the information in different modes according to different roles and different use scenes, thereby meeting the requirements of users on production and life.
Description
Technical Field
The invention relates to the field of memory test, in particular to a method and a device for distinguishing product information of multiple memory chips.
Background
The processing power of 5G mobile phones currently on the market is nearly mad, and it can be seen that device manufacturers are looking for lower power Dynamic Random Access Memories (DRAMs) whenever the processing speed of mobile devices increases. With the increasing demand of mobile devices for DRAM Power consumption, some Low Power DRAM (LPDDR) is derived on the market. The LPDDR4/5 is the current popular LPDDR product, the running speed is higher than 4266MT/S, far exceeds the traditional DDR memory, and in addition, the power consumption has no comparable advantages. The method is characterized in that a qualified dynamic random access memory product has a great influence on the use of a mobile device, so that a manufacturer of a chip in the dynamic random access memory can accurately obtain the version information, the Die number and the data bit width of the Die so as to judge the wafer model of a package and whether the version of the packaged Die is correct, and accurately calculate the memory capacity of the dynamic random access memory, such as the LPDDR4/5 so as to judge whether the chip is consistent with the information described in a specification or not, and in addition, the total capacity and the current residual capacity of the chip are more concerned for a product user so as to manage and store data.
Disclosure of Invention
The invention provides a method and a device for distinguishing product information of a plurality of memory chips, and aims to at least solve one of the technical problems in the prior art.
A first aspect of the present invention is a method for identifying product information of a multi-memory chip, including the steps of: initializing a dynamic random access memory chip; acquiring a scanning result of the DRAM controller; reading the data of the JEDEC reading register; calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the JEDEC register; and presenting the measured related data of the dynamic random access memory chip in different modes according to different roles and different use scenes.
In some embodiments, the product information identification method for multiple memory chips includes the following steps:
wherein, if the bit width of the crystal grain is 16bit, BW is 2; if the bit width of the crystal grain is 8 bits, BW is 1; m is the total number of permutations in one channel; die sizerank(i)The capacity size of the ith permutation; n is the total number of channels of the memory chip.
In some embodiments, the method for identifying product information of a multi-memory chip includes: the DRAM controller scans the channel number of the memory chip; the DRAM controller scans the memory chips for the number of ranks.
In some embodiments, the method for identifying product information of a multi-memory chip includes presenting measured data related to a dynamic random access memory chip in different ways according to different roles and different usage scenarios, including comparing the measured data related to the dynamic random access memory chip with data in a dynamic random product specification, and directly locating a fault point according to comparison information when a manufacturer produces the memory chip.
In some embodiments, the method for identifying product information of multiple memory chips, wherein the measured data related to the dynamic random access memory chips are presented in different ways according to different roles and different usage scenarios includes calculating a total capacity and a remaining capacity according to the measured data related to the dynamic random access memory chips, and displaying quality and/or capacity information of the memory chips.
In some embodiments, the method for identifying product information of a multi-memory chip includes presenting measured data related to the dynamic random access memory chip in different ways according to different roles and different usage scenarios, and generating a detailed list of various types of information of the memory chip according to the measured data related to the dynamic random access memory chip.
A second aspect of the present invention is a product information discrimination apparatus for a multi-memory chip, including:
the user selection module is used for selecting different use scenes to adapt to different objects; the reading module is used for reading related configuration information in the memory chip; the calculation module is used for calculating the information such as the capacity and the like in the memory chip; the comparison module is used for comparing the measured actual data of the memory chip with the data in the product specification; and the display module is used for displaying the relevant information of the memory chip in the appointed scene.
The invention has the following beneficial effects:
according to the technical scheme, relevant information such as manufacturers, capacities and the like of relevant chips in the dynamic random access memory can be accurately measured, the information is presented in different modes according to different roles and different use scenes, the requirements of production and life of users are met, when the manufacturers produce the memory chips, fault points can be directly located according to comparison information obtained by a comparison module, problems can be found as soon as possible, and enterprise loss is reduced. And for a common user, calculating the total capacity and the residual capacity according to the read content, and displaying the information concerned by the user, such as the quality and the capacity of the whole chip. For the technical enthusiasts, the read information is acquired, and a detailed list of various information of the chip is generated, so that the users can know the technical information of the memory chip in detail.
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Fig. 1 is a general flowchart of a method for discriminating product information of a multi-memory chip according to the present invention.
FIG. 2 is a block diagram of a memory chip according to an embodiment of the method for discriminating product information of LPDDR4 or LPDDR5 of the present invention.
FIG. 3 is a structural diagram of DRAM components according to an embodiment of the method for identifying product information of LPDDR4 or LPDDR 5.
FIG. 4 is a chart of the MR5 information index of the register in the embodiment of the method for identifying LPDDR4 or LPDDR5 product information according to the present invention.
FIG. 5 is a chart of the MR8 information index of the register in the embodiment of the method for identifying LPDDR4 or LPDDR5 product information according to the present invention.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any combination of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language ("e.g.," such as "or the like") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed.
The following describes in detail a method and an apparatus for identifying product information of a multi-memory chip according to an embodiment of the present invention in a specific embodiment, as shown in fig. 1, including the steps of:
s101, initializing a dynamic random access memory chip;
specifically, in an embodiment, the memory Chip is LPDDR4 or LPDDR5, and an internal structure thereof is as shown in fig. 2, where a System-on-a-Chip (SoC) is a center of a mobile device such as a mobile phone, and many key components such as a CPU, a GPU, and the like are integrated. Wherein a command/address bus on the SoC is coupled to a command/address bus located on the DRAM and a SoC data bus is coupled to the DRAM data bus. The Chip Select (CS) may use DRAM when needed. The LPDDR4/5 memory chip is initialized, namely, a DRAM controller of the SoC is initialized, and basic information in a register is configured.
S102, obtaining a scanning result of the DRAM controller;
specifically, in an embodiment, the step of obtaining the scan result of the controller includes:
s201, the DRAM controller scans the number of channels of the chip, in one embodiment, the number of channels that the DRAM controller scans to LPDDR4 or LPDDR5 is 2, as shown in FIG. 3, channel 0 and channel 1;
s202, the DRAM controller scans the memory chips to obtain the number of ranks, and in one embodiment, the DRAM controller scans the ranks (rank) to be 2, as shown in FIG. 3, rank0 and rank1, respectively. As shown in fig. 3, the interface bit width between the SoC and the DRAM is 32-bit data, the bit width of a single memory crystal is only 8 bits, a plurality of memory crystals are connected in parallel to form a data set with a bit width of 32 bits, and the data set is connected to the SoC, where the set of 32 bits is called rank.
S103, reading data of a JEDEC reading register;
specifically, in one embodiment, the access between the SoC and the register is performed through a bus inside the SoC, and the LPDDR4 or LPDDR5 has a plurality of registers, and in one embodiment, the JEDEC reads data in the registers MR5-8 to obtain basic configuration information of the LPDDR4 or LPDDR5 chip, for example, the configuration information stored in the registers MR5 and MR8 is shown in fig. 4-5. The related information of each channel and each rank can be obtained according to the stored data of the register, including the ID number of the manufacturer and the like.
S104, calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the register;
specifically, in the embodiment, the calculation formula of the total chip capacity information is as follows:
if the bit width of die is 16 bits, BW is 2; if the bit width of die is 8 bits, BW is 1; m is the total number of rank in one channel; die sizerank(i)Is the capacity of the ith rank; n is the total number of channels of the memory chip.
In one embodiment, the size (total) is (rank0 die size) BW + (rank1 die size) BW
Wherein, as shown in fig. 3, rank in one channel is 2, rank0, rank 1; the total number of channels is 2; the bit width of the crystal grain is 8bit, so BW is 1; die sizerank(0)＝die sizerank(1)＝2^32(ii) a size (total) ═ 2^32*2*1+2^32*2*1≈16G。
S105, according to different roles and different use scenes, the data related to the LPDDR4/5 memory chip obtained through measurement are presented in different modes.
In one embodiment, the system comprises a user selection module for selecting different usage scenarios to accommodate different objects; the reading module is used for reading related configuration information in the memory chip; the calculation module is used for calculating the information such as the capacity and the like in the memory chip; the comparison module is used for comparing the measured actual data of the memory chip with the data in the product specification; and the display module is used for displaying the relevant information of the memory chip in the appointed scene. According to different roles and different use scenes, different presentation modes exist: for a memory chip manufacturer, a reading module reads information such as the number of channels, the number and the capacity of rank, a manufacturer and the like, and a calculating module calculates the total capacity value of the memory according to the information; the comparison module compares actual data obtained by the reading module and the calculation module with data on a product specification, and when a manufacturer produces a memory chip, aiming at comparison information obtained by the comparison module, a fault point can be directly positioned when a problem exists, for example, the rank model of the fourth block is not matched or damaged, so that a manufacturer can correct the fault point and find the problem as soon as possible to reduce enterprise loss. For a common user, the information of the total capacity, the current residual capacity, the qualification of the memory chip and the like is relatively concerned, the calculation module calculates the total capacity and the residual capacity according to the content of the reading module, and the display module displays the information of the quality, the capacity and the like of the whole chip. For the technical enthusiasts, the information of the computing module and the reading module is extracted, and a detailed list of various information of the chip is generated, so that the users can know the information of the memory chip in detail.
It should be recognized that the method steps in embodiments of the present invention may be embodied or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Further, the operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes described herein (or variations and/or combinations thereof) may be performed under the control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) collectively executed on one or more processors, by hardware, or combinations thereof. The computer program includes a plurality of instructions executable by one or more processors.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable interface, including but not limited to a personal computer, mini computer, mainframe, workstation, networked or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and the like. Aspects of the invention may be embodied in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optically read and/or write storage medium, RAM, ROM, or the like, such that it may be read by a programmable computer, which when read by the storage medium or device, is operative to configure and operate the computer to perform the procedures described herein. Further, the machine-readable code, or portions thereof, may be transmitted over a wired or wireless network. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media include instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. The invention may also include the computer itself when programmed according to the methods and techniques described herein.
A computer program can be applied to input data to perform the functions described herein to transform the input data to generate output data that is stored to non-volatile memory. The output information may also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including particular visual depictions of physical and tangible objects produced on a display.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention as long as the technical effects of the present invention are achieved by the same means. The invention is capable of other modifications and variations in its technical solution and/or its implementation, within the scope of protection of the invention.
Claims (8)
1. A method for distinguishing product information of a multi-memory chip is characterized by comprising the following steps:
s101, initializing a dynamic random access memory chip;
s102, obtaining a scanning result of the DRAM controller;
s103, reading data of a JEDEC reading register;
s104, calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the JEDEC register;
and S105, presenting the measured related data of the dynamic random access memory chip in different modes according to different roles and different use scenes.
2. The method of claim 1, wherein the formula for calculating the total chip capacity information is as follows:
wherein, if the bit width of the crystal grain is 16bit, BW is 2; if the bit width of the crystal grain is 8 bits, BW is 1; m is the total number of permutations in one channel; die sizerank(i)The capacity size of the ith permutation; n is the total number of channels of the dynamic random access memory chip.
3. The method for identifying product information of multiple memory chips as claimed in claim 1, wherein step S102 specifically comprises:
s201, the DRAM controller scans a memory chip to obtain the channel number;
s202, the DRAM controller scans the memory chips to obtain the number of the arrangements.
4. The method as claimed in claim 1, wherein the step S105 includes comparing the measured data related to the dram chip with the data in the dram specification, and directly locating the fault point according to the comparison information when the manufacturer manufactures the dram chip.
5. The method for identifying the product information of multiple memory chips as claimed in claim 1, wherein the step S105 comprises calculating the total capacity, the remaining capacity and displaying the quality and/or capacity information of the memory chips according to the measured data related to the dram chips.
6. The method as claimed in claim 1, wherein the step S105 includes generating a detailed list of various types of information of the memory chips according to the measured data related to the dram chips.
7. A product information discrimination apparatus of a multi-memory chip, comprising:
the user selection module is used for selecting different use scenes to adapt to different objects;
the reading module is used for reading related configuration information in the memory chip;
the calculation module is used for calculating the information such as the capacity and the like in the memory chip;
the comparison module is used for comparing the data on the product specification of the memory chip with the measured actual data;
and the display module is used for displaying the relevant information of the memory chip in the appointed scene.
8. A computer-readable storage medium having stored thereon computer instructions, characterized in that the instructions, when executed by a processor, carry out the steps of the method according to any one of claims 1 to 6.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116578453A (en) * | 2023-04-25 | 2023-08-11 | 深圳市晶存科技有限公司 | Method and device for reducing defective rate of memory chip, electronic equipment and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5383147A (en) * | 1992-02-18 | 1995-01-17 | Mitsubishi Denki Kabushiki Kaisha | IC card and method of checking the memory capacity of IC card |
| JP2008034028A (en) * | 2006-07-28 | 2008-02-14 | Yokogawa Electric Corp | Memory test system and method |
| CN105760266A (en) * | 2016-02-24 | 2016-07-13 | 深圳芯邦科技股份有限公司 | Mobile device capacity detecting method based on Nand Flash |
| CN110718261A (en) * | 2019-08-21 | 2020-01-21 | 深圳市金泰克半导体有限公司 | Memory bank management method and system |
| CN111221696A (en) * | 2019-12-31 | 2020-06-02 | 苏州浪潮智能科技有限公司 | SPEC Power test method and device |
| CN111338860A (en) * | 2020-02-14 | 2020-06-26 | 浪潮电子信息产业股份有限公司 | Memory monitoring method, device, equipment and storage medium |
-
2021
- 2021-06-28 CN CN202110720314.9A patent/CN113436668B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5383147A (en) * | 1992-02-18 | 1995-01-17 | Mitsubishi Denki Kabushiki Kaisha | IC card and method of checking the memory capacity of IC card |
| JP2008034028A (en) * | 2006-07-28 | 2008-02-14 | Yokogawa Electric Corp | Memory test system and method |
| CN105760266A (en) * | 2016-02-24 | 2016-07-13 | 深圳芯邦科技股份有限公司 | Mobile device capacity detecting method based on Nand Flash |
| CN110718261A (en) * | 2019-08-21 | 2020-01-21 | 深圳市金泰克半导体有限公司 | Memory bank management method and system |
| CN111221696A (en) * | 2019-12-31 | 2020-06-02 | 苏州浪潮智能科技有限公司 | SPEC Power test method and device |
| CN111338860A (en) * | 2020-02-14 | 2020-06-26 | 浪潮电子信息产业股份有限公司 | Memory monitoring method, device, equipment and storage medium |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116578453A (en) * | 2023-04-25 | 2023-08-11 | 深圳市晶存科技有限公司 | Method and device for reducing defective rate of memory chip, electronic equipment and storage medium |
| CN116578453B (en) * | 2023-04-25 | 2024-01-16 | 深圳市晶存科技有限公司 | Method and device for reducing defective rate of memory chip, electronic equipment and storage medium |
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