CN113436668B - Product information identification method and device for multiple memory chips - Google Patents
Product information identification method and device for multiple memory chips Download PDFInfo
- Publication number
- CN113436668B CN113436668B CN202110720314.9A CN202110720314A CN113436668B CN 113436668 B CN113436668 B CN 113436668B CN 202110720314 A CN202110720314 A CN 202110720314A CN 113436668 B CN113436668 B CN 113436668B
- Authority
- CN
- China
- Prior art keywords
- memory chip
- information
- random access
- dynamic random
- access memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004364 calculation method Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 238000012850 discrimination method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention relates to a product information identification method of a multi-memory chip, which comprises the following steps: initializing a dynamic random access memory chip (S101); acquiring a scanning result of the DRAM controller (S102); reading JEDEC read register data (S103); calculating total chip capacity information based on the scan result of the DRAM controller and the read data of the JEDEC register (S104); and according to different roles and different use scenes, the measured data related to the dynamic random access memory chip are presented in different modes (S105). The product information distinguishing device of the multi-memory chip comprises: the device comprises a user selection module, a reading module, a calculation module, a comparison module and a display module. The invention can accurately measure the related information in the dynamic random access memory, and present the information in different modes according to different roles and different use scenes, thereby meeting the demands of users for production and life.
Description
Technical Field
The present invention relates to the field of memory testing, and in particular, to a method and apparatus for identifying product information of multiple memory chips.
Background
Currently marketed 5G handsets are increasingly more capable, it can be seen that device manufacturers are looking for lower power dynamic random access memory (Dynamic Random Access Memory, DRAM) whenever mobile device processing speeds are increased. As the requirements of mobile devices for DRAM power consumption become higher, some low power DRAM (Low Power Double Data Rate SDRAM, LPDDR) is derived on the market. The LPDDR4/5 is a relatively popular LPDDR product at present, the running speed is more than 4266MT/S, and the running speed is far more than that of the traditional DDR memory, and in addition, the LPDDR4/5 has incomparable advantages in the aspect of power consumption. A qualified DRAM product has huge influence on the use of mobile equipment, so that manufacturers of chips in the DRAM are accurately obtained, the version information, the number of Dies and the data bit width of Dies are judged, whether the packaged wafer model and the packaged Die version of the DRAM are correct or not is judged, the memory capacity of the DRAM, such as LPDDR4/5, is accurately calculated, and whether the chips are consistent with the information described in the specification or not is the problem which needs to be solved at present.
Disclosure of Invention
The invention provides a method and a device for distinguishing product information of multiple memory chips, which aim to at least solve one of the technical problems in the prior art.
The first aspect of the technical scheme of the invention is a product information identification method of a multi-memory chip, which comprises the following steps: initializing a dynamic random access memory chip; acquiring a scanning result of the DRAM controller; reading JEDEC data of a read register; calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the JEDEC register; and according to different roles and different use scenes, the measured data related to the dynamic random access memory chip are presented in different modes.
In some embodiments, the product information identification method of a multi-memory chip, wherein the formula for calculating the total chip capacity information is:
wherein, if the bit width of the die is 16 bits, bw=2; if the bit width of the die is 8 bits, bw=1; m is the total number of permutations in a channel;
is->
The capacity size of the individual arrangement; n is the total number of channels of the memory chip.
In some embodiments, the method for identifying product information of a multi-memory chip, wherein obtaining a scan result of a DRAM controller specifically includes: the DRAM controller scans the channel number of the memory chip; the DRAM controller scans the memory chips for the number of ranks.
In some embodiments, the method for distinguishing product information of multiple memory chips includes presenting the measured data related to the dynamic random access memory chip in different manners according to different roles and different usage scenarios, including comparing the measured data related to the dynamic random access memory chip with data on a dynamic random product instruction book, and directly locating a fault point according to the comparison information when a manufacturer produces the memory chip.
In some embodiments, the method for distinguishing product information of multiple memory chips includes presenting the measured data related to the dynamic random access memory chip in different manners according to different roles and different usage scenarios, including calculating total capacity, remaining capacity, and displaying quality and/or capacity information of the memory chip according to the measured data related to the dynamic random access memory chip.
In some embodiments, the method for distinguishing product information of multiple memory chips includes presenting the measured data related to the dynamic random access memory chip in different manners according to different roles and different usage scenarios, including generating a detailed table of various information of the memory chip according to the measured data related to the dynamic random access memory chip.
A second aspect of the present invention is a product information identifying apparatus for a multi-memory chip, including:
the user selection module is used for selecting different use scenes to be suitable for different objects; the reading module is used for reading the relevant configuration information in the memory chip; the computing module is used for computing information such as capacity in the memory chip; the comparison module is used for comparing the actual data of the memory chip obtained by measurement with the data on the product instruction book; and the display module is used for displaying the related information of the memory chip in the appointed scene.
The beneficial effects of the invention are as follows:
according to the technical scheme, the method and the device can accurately measure the related information such as the manufacturer, capacity and the like of the related chip in the dynamic random access memory, present the information in different modes according to different roles and different use scenes, meet the demands of users for production and life, and can directly locate fault points when problems exist aiming at the comparison information obtained by the comparison module when the manufacturer produces the memory chip, discover the problems early and reduce the enterprise loss. For a common user, calculating the total capacity and the residual capacity according to the read content, and displaying the information of the whole chip quality, capacity and the like which are concerned by the user. For technical lovers, the read information is obtained, and a detailed list of various information of the chip is generated, so that the users can know the technical information of the memory chip in detail.
Drawings
Fig. 1 is a general flow chart of a method for distinguishing product information of a multi-memory chip according to the present invention.
Fig. 2 is a block diagram of a memory chip in an embodiment of an LPDDR4 or LPDDR5 product information identification method according to the present invention.
Fig. 3 is a diagram showing a DRAM component structure in an embodiment of the LPDDR4 or LPDDR5 product information identification method according to the present invention.
FIG. 4 is a diagram illustrating the register MR5 information according to an embodiment of the LPDDR4 or LPDDR5 product information discrimination method according to the invention.
FIG. 5 is a diagram illustrating the register MR8 information according to an embodiment of the LPDDR4 or LPDDR5 product information discrimination method according to the invention.
Detailed Description
The conception, specific structure, and technical effects produced by the present invention will be clearly and completely described below with reference to the embodiments and the drawings to fully understand the objects, aspects, and effects of the present invention.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly or indirectly fixed or connected to the other feature. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any combination of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could also be termed a second element, and, similarly, a second element could also be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the invention and does not pose a limitation on the scope of the invention unless otherwise claimed.
The following describes in detail, by way of specific embodiments, a method and an apparatus for identifying product information of a multi-memory chip according to an embodiment of the present invention, as shown in fig. 1, including the steps of:
s101, initializing a dynamic random access memory chip;
specifically, in one embodiment, the memory Chip is LPDDR4 or LPDDR5, and the internal structure is shown in fig. 2, where a System-on-a-Chip (SoC) is a center of a mobile device such as a mobile phone, and many key components, such as a CPU, a GPU, and the like, are integrated. Wherein a command/address bus on the SoC is coupled to a command/address bus on the DRAM and a SoC data bus is coupled to the DRAM data bus. Chip Select (CS) may use DRAM when needed. Initializing the LPDDR4/5 memory chip, namely initializing the DRAM controller of the SoC and configuring basic information in the register.
S102, acquiring a scanning result of a DRAM controller;
specifically, in an embodiment, the specific steps of obtaining the scan result of the controller are as follows:
s201, the DRAM controller scans the channel number of the chip, in one embodiment, the channel number of the LPDDR4 or LPDDR5 scanned by the DRAM controller is 2, as shown in FIG. 3, which is channel 0 and channel 1 respectively;
s202, the DRAM controller scans the memory chips to obtain the number of ranks, and in one embodiment, the DRAM controller scans the number of ranks (rank) to be 2, as shown in FIG. 3, rank0 and rank1, respectively. As shown in fig. 3, the interface bit width between the SoC and the DRAM is 32 bits of data, the bit width of a single memory crystal is only 8 bits, and a plurality of memory crystals are connected in parallel to form a data set with the bit width of 32 bits, and the data set with the bit width of 32 bits is connected with the SoC, wherein the set with the bit width of 32 bits is called rank.
S103, reading JEDEC data of a read register;
specifically, in an embodiment where access between the SoC and the registers is performed via a bus internal to the SoC, there are multiple registers in LPDDR4 or LPDDR5, JEDEC reads data from registers MR5-8 to obtain basic configuration information of the LPDDR4 or LPDDR5 chip, as illustrated in fig. 4-5 for configuration information stored in registers MR5 and MR 8. The relevant information of each channel and each rank can be obtained according to the stored data of the register, including ID numbers of manufacturers and the like.
S104, calculating total chip capacity information according to the scanning result of the DRAM controller and the read data of the register;
specifically, in the embodiment, the calculation formula of the total chip capacity information is:
wherein, if die bit width is 16 bits, bw=2; if die bit width is 8 bits, bw=1; m is the total number of rank in one channel;
is->
The capacity size of the individual rank; n is the total number of channels of the memory chip.
In one embodiment, size (total) = (rank 0 die size number of channels) × bw+ (rank 1 die size number of channels) × BW
As shown in fig. 3, the rank in one channel is 2, and is rank0, rank1; the total number of channels is 2; the die bit width is 8 bits, so bw=1;
=/>
=/>
the method comprises the steps of carrying out a first treatment on the surface of the size (total) = =>
*2*1+/>
*2*1/>
16G。
S105, according to different roles and different use scenes, the data related to the LPDDR4/5 memory chip obtained through measurement are presented in different modes.
In one embodiment, the user selection module is used for selecting different use scenes to adapt to different objects; the reading module is used for reading the relevant configuration information in the memory chip; the computing module is used for computing information such as capacity in the memory chip; the comparison module is used for comparing the actual data of the memory chip obtained by measurement with the data on the product instruction book; and the display module is used for displaying the related information of the memory chip in the appointed scene. According to different roles and different use scenes, different presentation modes exist: for a memory chip manufacturer, a reading module reads the information of the number of channels, the number and the capacity of rank, a manufacturer, and the like, and a calculating module calculates the total capacity value of the memory according to the information; the comparison module compares the actual data obtained by the reading module and the calculation module with the data on the product specification, and when a manufacturer produces a memory chip, the comparison module can directly locate a fault point when a problem exists, for example, the number of rank models is not matched or damaged, so that the manufacturer can correct the fault, and the problem can be found early to reduce the enterprise loss. For a common user, comparing the information of the total capacity, the current residual capacity, whether the memory chip is qualified or not and the like of the concerned memory chip, and calculating the total capacity, the residual capacity and the like by a calculating module according to the content of a reading module, wherein a display module displays the information of the whole chip quality, the capacity and the like. For technical lovers, information of the calculation module and the reading module is extracted, and a detailed list of various information of the chip is generated, so that the users can know the information of the memory chip in detail.
It should be appreciated that the method steps in embodiments of the present invention may be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in non-transitory computer-readable memory. The method may use standard programming techniques. Each program may be implemented in a high level procedural or object oriented programming language to communicate with a computer system. However, the program(s) can be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language. Furthermore, the program can be run on a programmed application specific integrated circuit for this purpose.
Furthermore, the operations of the processes described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The processes (or variations and/or combinations thereof) described herein may be performed under control of one or more computer systems configured with executable instructions, and may be implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications), by hardware, or combinations thereof, collectively executing on one or more processors. The computer program includes a plurality of instructions executable by one or more processors.
Further, the method may be implemented in any type of computing platform operatively connected to a suitable computing platform, including, but not limited to, a personal computer, mini-computer, mainframe, workstation, network or distributed computing environment, separate or integrated computer platform, or in communication with a charged particle tool or other imaging device, and so forth. Aspects of the invention may be implemented in machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and/or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, which when read by a computer, is operable to configure and operate the computer to perform the processes described herein. Further, the machine readable code, or portions thereof, may be transmitted over a wired or wireless network. When such media includes instructions or programs that, in conjunction with a microprocessor or other data processor, implement the steps described above, the invention described herein includes these and other different types of non-transitory computer-readable storage media. The invention may also include the computer itself when programmed according to the methods and techniques of the present invention.
The computer program can be applied to the input data to perform the functions described herein, thereby converting the input data to generate output data that is stored to the non-volatile memory. The output information may also be applied to one or more output devices such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects produced on a display.
The present invention is not limited to the above embodiments, but can be modified, equivalent, improved, etc. by the same means to achieve the technical effects of the present invention, which are included in the spirit and principle of the present invention. Various modifications and variations are possible in the technical solution and/or in the embodiments within the scope of the invention.
Claims (5)
1. A method for identifying product information of a multi-memory chip, the method comprising the steps of:
s101, initializing a dynamic random access memory chip;
s102, acquiring a scanning result of a DRAM controller;
s103, reading JEDEC data of a read register;
s104, calculating total chip capacity information according to a scanning result of the DRAM controller and read data of a JEDEC register, wherein a formula for calculating the total chip capacity information is as follows:
wherein bw=2 if the bit width of the die is 16 bits; if the bit width of the die is 8 bits, bw=1; m is the total number of permutations in a channel; />
Is->
The capacity size of the individual arrangement; n is the total number of channels of the dynamic random access memory chip;
s105, according to different roles and different use scenes, the measured data related to the dynamic random access memory chip are presented in different modes;
the step S102 specifically includes:
s201, a DRAM controller scans a memory chip to obtain the channel number;
s202, the DRAM controller scans the memory chips to obtain the number of permutations.
2. The method for distinguishing product information of multiple memory chips as recited in claim 1, wherein step S105 includes comparing the measured data related to the dynamic random access memory chip with the data in the dynamic random access memory specification, and locating the fault point directly according to the comparison information when the manufacturer produces the memory chip.
3. The method for distinguishing product information of multiple memory chips as defined in claim 1, wherein the step S105 includes calculating total capacity, remaining capacity, and displaying quality and/or capacity information of the memory chips based on the measured data related to the dynamic random access memory chips.
4. The method for distinguishing product information of multiple memory chips as recited in claim 1, wherein step S105 includes generating a list of various types of information of the memory chips based on the measured data related to the dynamic random access memory chips.
5. A computer readable storage medium having stored thereon computer instructions, which when executed by a processor, implement the steps of the method of any of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110720314.9A CN113436668B (en) | 2021-06-28 | 2021-06-28 | Product information identification method and device for multiple memory chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110720314.9A CN113436668B (en) | 2021-06-28 | 2021-06-28 | Product information identification method and device for multiple memory chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113436668A CN113436668A (en) | 2021-09-24 |
| CN113436668B true CN113436668B (en) | 2023-05-16 |
Family
ID=77755000
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110720314.9A Active CN113436668B (en) | 2021-06-28 | 2021-06-28 | Product information identification method and device for multiple memory chips |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113436668B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116578453B (en) * | 2023-04-25 | 2024-01-16 | 深圳市晶存科技有限公司 | Method and device for reducing defective rate of memory chip, electronic equipment and storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05233901A (en) * | 1992-02-18 | 1993-09-10 | Mitsubishi Electric Corp | Confirming method for ic card and memory capacity of memory ic mounted on ic card and ic card |
| JP2008034028A (en) * | 2006-07-28 | 2008-02-14 | Yokogawa Electric Corp | Memory test system and method |
| CN105760266B (en) * | 2016-02-24 | 2019-09-03 | 深圳芯邦科技股份有限公司 | A kind of mobile device capacity check method based on Nand Flash memory |
| CN110718261A (en) * | 2019-08-21 | 2020-01-21 | 深圳市金泰克半导体有限公司 | Memory bank management method and system |
| CN111221696B (en) * | 2019-12-31 | 2022-07-08 | 苏州浪潮智能科技有限公司 | SPEC Power test method and device |
| CN111338860A (en) * | 2020-02-14 | 2020-06-26 | 浪潮电子信息产业股份有限公司 | Memory monitoring method, device, equipment and storage medium |
-
2021
- 2021-06-28 CN CN202110720314.9A patent/CN113436668B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN113436668A (en) | 2021-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6005895B1 (en) | Intelligent multi-core control for optimal performance per watt | |
| US20200254348A1 (en) | System, method, and computer program product for simultaneously determining settings for a plurality of parameter variations | |
| CN106462465A (en) | Algorithm for preferred core sequencing to maximize performance and reduce chip temperature and power | |
| US11231760B1 (en) | Techniques for accurately determining the temperature at various locations of an operating integrated circuit | |
| US11507348B2 (en) | Method and apparatus for generating chip-based computing function, device, and storage medium | |
| CN106708587A (en) | Parameter configuration method and system | |
| CN113436668B (en) | Product information identification method and device for multiple memory chips | |
| US11436188B2 (en) | Resource optimization and update method, server, and device | |
| US12112166B2 (en) | Data processing method and apparatus, and related product for increased efficiency of tensor processing | |
| US8953893B2 (en) | System and method to determine feature candidate pixels of an image | |
| CN109002331A (en) | Starting method and device of touch screen, computer equipment and storage medium | |
| CN103135049A (en) | Test pattern generation device, test program generation device, generation method, and test device | |
| CN104809053A (en) | Control style testing method and device | |
| US20100115351A1 (en) | Data storage apparatus, data storage controller, and related automated testing method | |
| US10861201B2 (en) | Information generation system, method, and computer program product | |
| CN108600042B (en) | WiFi test method and device for electronic equipment, storage medium and test equipment | |
| CN112417802A (en) | Method, system, equipment and storage medium for simulating storage chip | |
| WO2016050221A1 (en) | Hardware-accelerated dynamic voltage and frequency scaling | |
| CN116384505A (en) | Data processing method and device, storage medium and electronic equipment | |
| CN115587026A (en) | Chip testing method and device, storage medium and chip | |
| CN114356289A (en) | Shader using method based on multiple platforms and related equipment | |
| US10573306B2 (en) | Method and device for processing data based on speech recognizing and scoring system | |
| US20190362459A1 (en) | Information processing device and method of controlling same, and non-transitory computer readable medium | |
| CN107247577B (en) | Method, device and system for configuring SOC IP core | |
| US20130155087A1 (en) | System and method for configuring graphics register data and recording medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518048 zone FB, 2f, Dasheng building, No. 1-3 Taohua Road, Fubao community, Fubao street, Futian District, Shenzhen, Guangdong Province Patentee after: Shenzhen Jingcun Technology Co.,Ltd. Country or region after: China Address before: 518048 zone FB, 2f, Dasheng building, No. 1-3 Taohua Road, Fubao community, Fubao street, Futian District, Shenzhen, Guangdong Province Patentee before: Shenzhen Jingcun Technology Co.,Ltd. Country or region before: China |