CN115116511A - Power consumption prediction method, device, equipment and storage medium - Google Patents
Power consumption prediction method, device, equipment and storage medium Download PDFInfo
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- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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Abstract
The application provides a power consumption prediction method, a power consumption prediction device, equipment and a storage medium, which can be applied to equipment memory power consumption prediction, wherein the method comprises the following steps: acquiring instruction data of a device memory in a target scene, wherein the instruction data is used for indicating the state change of the memory in a preset time period; determining power consumption corresponding to each state of the memory in a preset time period according to the instruction data; determining the average power consumption of the memory in a preset time period according to the power consumption corresponding to each state of the memory in the preset time period; the average power consumption is taken as the predicted power consumption of the memory. The prediction scheme improves the accuracy and reliability of the prediction result.
Description
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a power consumption prediction method, apparatus, device, and storage medium.
Background
Currently, Dynamic Random Access Memory (DRAM) power consumption data is determined based on current (IDD) values defined by Jedec specifications in different application modes, for example, IDD0 defines a current value of frequently switching a Memory cell (bank) in Jedec, however, in practical applications, such application mode does not exist, and the instruction sequence sent by a device processor to a Memory is Random and unpredictable. Therefore, how to predict the power consumption of the device memory and make the prediction result real and reliable is a problem to be solved urgently at present.
Disclosure of Invention
The embodiment of the application provides a power consumption prediction method, a power consumption prediction device, power consumption prediction equipment and a power consumption prediction storage medium, and accuracy and reliability of prediction results are improved.
A first aspect of an embodiment of the present application provides a power consumption prediction method, including:
acquiring instruction data of a device memory in a target scene, wherein the instruction data is used for indicating the state change of the memory in a preset time period;
determining power consumption corresponding to each state of the memory in the preset time period according to the instruction data;
determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
taking the average power consumption as the predicted power consumption of the memory.
In an optional embodiment of the first aspect of the present application, the instruction data includes an instruction sequence sent by the device processor to the memory within the preset time period, and a duration of the memory state corresponding to each instruction in the instruction sequence;
the acquiring of the instruction data of the device memory in the target scene includes:
obtaining a sequence of instructions of the device memory in the target scenario from a protocol analyzer.
In an optional embodiment of the first aspect of the present application, the determining, according to the instruction data, power consumption corresponding to each state of the memory in the preset time period includes:
acquiring a first state corresponding to a first instruction in the instruction data and the duration of the first state; the first instruction is any one instruction in the instruction sequence, and the first state comprises the state of at least one storage unit in the memory;
acquiring a first predicted current value of the memory in the first state;
and determining first predicted power consumption corresponding to the first state according to the first predicted current value, the duration of the first state and a preset voltage value.
In an optional embodiment of the first aspect of the present application, the obtaining a first predicted current value of the memory in the first state comprises:
acquiring a first preset current formula corresponding to the first state;
and acquiring a first predicted current value of the memory in the first state through the first preset current formula.
In an optional embodiment of the first aspect of the present application, the state of any one of the storage units in the memory includes any one of:
closed state, open state, refresh state.
In an optional embodiment of the first aspect of the present application, the method further comprises:
acquiring a first measured current value of the memory in the first state;
and verifying whether a first preset current formula corresponding to the first state is reasonable or not by comparing the first actually-measured current value with the first predicted current value.
In an optional embodiment of the first aspect of the present application, the verifying whether the first preset current formula corresponding to the first state is reasonable by comparing the first measured current value with the first predicted current value includes:
if the absolute value of the difference value between the first measured current value and the first predicted current value is smaller than a threshold value, determining that the first preset current formula is reasonable; or
And if the absolute value of the difference value between the first actually-measured current value and the first predicted current value is greater than or equal to the threshold value, determining that the first preset current formula is unreasonable.
In an optional embodiment of the first aspect of the present application, the obtaining a first measured current value of the memory in the first state includes:
acquiring a current value on the equipment power supply in a period corresponding to the first state through detection equipment;
and taking the current value of the equipment power supply in the period corresponding to the first state as the first measured current value.
In an optional embodiment of the first aspect of the present application, the determining, according to power consumption corresponding to each state of the memory in the preset time period, an average power consumption of the memory in the preset time period includes:
determining the total power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
and determining the average power consumption of the memory in the preset time period according to the total power consumption and the total duration of the preset time period.
In an optional embodiment of the first aspect of the present application, the method further comprises: acquiring the ratio of the power consumption corresponding to each state of the memory in the preset time period to the total power consumption of the memory in the preset time period;
determining a state power consumption distribution diagram of the memory according to the ratio of the power consumption corresponding to each state to the total power consumption;
and displaying the state power consumption distribution diagram, wherein the state power consumption distribution diagram is used for guiding a tester to improve the power consumption of the equipment.
In an optional embodiment of the first aspect of the present application, the target scenario includes any one of:
standby, video playing, audio playing, text displaying and game executing.
A second aspect of an embodiment of the present application provides a power consumption prediction apparatus, including:
the device comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring instruction data of a device memory in a target scene, and the instruction data is used for indicating the state change of the memory in a preset time period;
the processing module is used for determining power consumption corresponding to each state of the memory in the preset time period according to the instruction data;
determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
taking the average power consumption as the predicted power consumption of the memory.
In an optional embodiment of the second aspect of the present application, the instruction data includes an instruction sequence sent by the device processor to the memory within the preset time period, and a duration of the memory state corresponding to each instruction in the instruction sequence;
the acquisition module is used for acquiring the instruction sequence of the equipment memory in the target scene from a protocol analyzer.
In an optional embodiment of the second aspect of the present application, the obtaining module is configured to obtain a first state corresponding to a first instruction in the instruction data and a duration of the first state; the first instruction is any one instruction in the instruction sequence, and the first state comprises the state of at least one storage unit in the memory;
the obtaining module is used for obtaining a first predicted current value of the memory in the first state;
the processing module is configured to determine a first predicted power consumption corresponding to the first state according to the first predicted current value, the duration of the first state, and a preset voltage value.
In an optional embodiment of the second aspect of the present application, the obtaining module is configured to:
acquiring a first preset current formula corresponding to the first state;
and acquiring a first predicted current value of the memory in the first state through the first preset current formula.
In an optional embodiment of the second aspect of the present application, the state of any one of the memory cells in the memory comprises any one of:
closed state, open state, refresh state.
In an optional embodiment of the second aspect of the present application, the obtaining module is configured to obtain a first measured current value of the memory in the first state;
the processing module is configured to verify whether a first preset current formula corresponding to the first state is reasonable by comparing the first actually-measured current value with the first predicted current value.
In an optional embodiment of the second aspect of the present application, the processing module is configured to:
if the absolute value of the difference value between the first measured current value and the first predicted current value is smaller than a threshold value, determining that the first preset current formula is reasonable; or
And if the absolute value of the difference value between the first measured current value and the first predicted current value is greater than or equal to the threshold value, determining that the first preset current formula is unreasonable.
In an optional embodiment of the second aspect of the present application, the obtaining module is configured to:
acquiring a current value on the equipment power supply in a period corresponding to the first state through detection equipment;
and taking the current value of the equipment power supply in the period corresponding to the first state as the first measured current value.
In an optional embodiment of the second aspect of the present application, the processing module is configured to:
determining the total power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
and determining the average power consumption of the memory in the preset time period according to the total power consumption and the total duration of the preset time period.
In an optional embodiment of the second aspect of the present application, the power consumption predicting apparatus further includes: and a display module.
The obtaining module is configured to obtain a ratio of power consumption corresponding to each state of the memory in the preset time period to total power consumption of the memory in the preset time period;
the processing module is used for determining a state power consumption distribution diagram of the memory according to the ratio of the power consumption corresponding to each state to the total power consumption;
the display module is used for displaying the state power consumption distribution diagram, and the state power consumption distribution diagram is used for guiding a tester to improve the power consumption of the equipment.
In an optional embodiment of the second aspect of the present application, the target scenario includes any one of:
standby, video playing, audio playing, text displaying and game executing.
A third aspect of embodiments of the present application provides an electronic device, including:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any of the first aspects.
A fourth aspect of embodiments of the present application provides a computer-readable storage medium having stored thereon a computer program for execution by a processor to perform the method according to any one of the first aspect.
A fifth aspect of embodiments of the present application provides a computer program product comprising a computer program that, when executed by a processor, performs the method of any one of the first aspects.
The embodiment of the application provides a power consumption prediction method, a power consumption prediction device, equipment and a storage medium, which can be applied to equipment memory power consumption prediction, wherein the method comprises the following steps: acquiring instruction data of a device memory in a target scene, wherein the instruction data is used for indicating the state change of the memory in a preset time period; determining power consumption corresponding to each state of the memory in a preset time period according to the instruction data; determining the average power consumption of the memory in a preset time period according to the power consumption corresponding to each state of the memory in the preset time period; the average power consumption is taken as the predicted power consumption of the memory. The prediction scheme improves the accuracy and reliability of the prediction result.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a memory structure according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a power consumption prediction method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a command sequence corresponding to different currents according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart of a power consumption prediction method according to an embodiment of the present application;
FIG. 5 is a state power consumption distribution diagram provided by an embodiment of the present application;
fig. 6 is a schematic structural diagram of a power consumption prediction apparatus according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a power consumption prediction apparatus according to an embodiment of the present application;
fig. 8 is a hardware structure diagram of an electronic device according to an embodiment of the present application.
Specific embodiments of the present application have been shown by way of example in the drawings and will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," and the like in the description and in the claims, and in the drawings, of the embodiments of the application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in other sequences than described or illustrated herein.
It should be understood that the terms "comprises" and "comprising," and any variations thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In the description of the embodiments of the present application, the term "correspond" may indicate that there is a direct correspondence or an indirect correspondence between the two, may also indicate that there is an association between the two, and may also indicate and be indicated, configure and configured, and so on.
Before describing the technical solutions provided in the embodiments of the present application, relevant contents and terms related to the embodiments of the present application will be briefly described.
1) A Memory (Memory) is an important component of an electronic device, and is also called an internal Memory and a main Memory, and is used for temporarily storing operation data in a processor CPU and data exchanged with an external Memory such as a hard disk. The method is a bridge for communicating an external memory with a CPU, all programs in the equipment are operated in the internal memory, and the level of the whole performance of the equipment is influenced by the strength of the performance of the internal memory. As long as the equipment starts to operate, the system transfers data needing to be operated into the CPU from the memory for operation, and when the operation is completed, the CPU transmits the result out. The operation of the memory determines the overall operation speed of the equipment. The memories can be divided into the following types: random access memory RAM, read only memory ROM, dynamic random access memory DRAM, static random access memory SRAM, programmable read only memory PROM, EPROM electrically programmable read only memory, EEPROM electrically programmable/erasable read only memory, FLASH FLASH memory, etc.
2) The main action principle of a Dynamic Random Access Memory (DRAM), which is a semiconductor memory, is to represent whether a binary bit (bit) is 1 or 0 by the amount of stored charges in a capacitor. In reality, the amount of charges stored in the capacitor is not enough to correctly determine data due to leakage current of the transistor, which results in data corruption. Therefore, for DRAM, periodic charging is an unavoidable requirement. Due to this characteristic of requiring timed refresh, it is referred to as "dynamic" memory. In contrast, a static memory (SRAM) does not lose memory even if it is not refreshed, as long as it stores data.
3) Basic structure of DRAM device: each DRAM memory unit comprises a MOS tube, a capacitor, a word line (row) and a bit line (column), a memory array of the DRAM device comprises a plurality of memory units, the memory array generally occupies 50-65% of the area of the whole DRAM device, and the rest area is mainly peripheral circuits. In each memory cell, the MOS transistor is controlled by the byte line to play a role of a switch and control the reading, writing and updating of the memory cell. In a write operation, charge flows from the bit line and is stored in the charge; in a read operation, charge flows from the capacitor and is fed back onto the bit line. Peripheral circuits of the DRAM device include a row address decoder (row address decoder), a column address decoder (column address decoder), a row input buffer (X input buffer), a column input buffer (Y input buffer), a write driver (write driver), an input/output port (device I/O & buffer), and a sense amplifier (sense amplifier). The row and column address decoders are used for decoding row and column addresses in an external instruction to obtain addresses of an internal memory array of the DRAM device when the external instruction is used for reading/writing a certain memory cell, and further controlling byte lines and bit lines to be opened so as to read/write the specified memory cell.
4) A Protocol Analyzer (PA) is a special test tool that monitors data flow in a data communication system and checks whether data exchange is reasonably performed according to the specifications of a protocol.
5) Precharge, which means that all memory cells in the working row are subjected to data rewriting in the memory, and the row address is reset, and at the same time, the sense amplifier is released to prepare for the operation of a new row.
The embodiment of the application relates to power consumption analysis/prediction of a system or equipment, in particular to memory power consumption analysis/prediction in different application modes (states), and memory power consumption prediction is performed by using a predefined memory preset current formula and DRAM IDDx test data, so that the method can be used for system power consumption optimization and memory power consumption improvement.
For ease of understanding, the internal structure of the device memory will be briefly described with reference to fig. 1.
Fig. 1 is a schematic diagram of a memory structure according to an embodiment of the present disclosure. As shown in fig. 1, the memory structure includes a core array circuit region and a peripheral logic circuit region, and the peripheral logic circuit region is connected to the core array circuit region through a data bus. The core array circuit region includes, for example, 2 groups of memory cells (banks), such as BG (bank group)0 and BG1 in fig. 1, each group of memory cells includes 4 memory cells, such as BG0 in fig. 1 including bank0-bank3, and BG1 including bank 4-7. The peripheral logic circuit area is responsible for analyzing instructions of the data bus, and the core array circuit area is responsible for storing data.
It should be noted that the above-mentioned memory structure is only an example, and a larger number of storage units and external interfaces may be expanded according to the actual application requirements, which is not limited in this embodiment.
It should be further noted that the memory structure has three power supply inputs, which are respectively denoted as VDD1, VDD2 and VDDQ, and which respectively supply power to the core array circuit region, the peripheral logic circuit region and the interface region of the memory structure.
At present, memory power consumption data is determined based on current values in different application modes defined by a Jedec specification, wherein the current values in 15 different application modes shown in table 1 are defined in the Jedec specification, and each application mode corresponds to a DRAM memory (access) sequence. However, in practical applications, the DRAM memory sequence is random and unpredictable, and thus the power consumption determined based on the current value defined by the Jedec specification does not represent the real device power consumption. Although the actual measured power consumption data may reflect a real device power consumption result, the result may not guide a tester to perform system power consumption optimization and memory power consumption improvement.
TABLE 1
| Sign of current | Application mode/state |
| IDD0 | bank cycle on and off |
| IDD2N | bank off, Clock (CK) on, non low power mode |
| IDD2NS | bank off, CK off, non low power mode |
| IDD2P | bank off, CK on, low power mode |
| IDD2PS | bank off, CK off, low power mode |
| IDD3N | bank on, CK on, non low power mode |
| IDD3NS | bank on, CK off, non low power mode |
| IDD3P | bank on, CK on, low power mode |
| IDD3PS | bank on, CK off, low power mode |
| IDD4R | bank open, reading |
| IDD4W | bank open, writing |
| IDD5 | Continuous all bank refresh |
| IDD5AB | Distributed all bank refresh |
| IDD5PB | Distributed single bank refresh |
| IDD6 | Self-refresh |
In view of the above, the technical solutions provided in the embodiments of the present application aim to: the dimension difference between the IDD definition in the Jedec specification and the actually measured power consumption result of the equipment is improved, the memory power consumption corresponding to each instruction in the DRAM memory sequence in practical application is determined through a predefined preset current formula and the current value defined by the Jedec specification, the total power consumption of the equipment can be obtained, and the proportion of the memory power consumption corresponding to each instruction in the DRAM memory sequence to the total power consumption can be obtained, so that a tester is guided to perform system power consumption optimization and memory power consumption improvement.
The technical solutions provided in the embodiments of the present application are described in detail below with specific embodiments. It should be noted that the technical solutions provided in the embodiments of the present application may include part or all of the following contents, and these specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 2 is a schematic flow chart of a power consumption prediction method according to an embodiment of the present application. As shown in fig. 2, the power consumption prediction method of the present embodiment includes the following steps:
step 201, acquiring instruction data of the device memory in a target scene, wherein the instruction data is used for indicating the state change of the memory in a preset time period.
In an optional embodiment of this embodiment, the instruction data of the device memory in the target scenario is obtained from the protocol analyzer PA. The PA is used for grabbing a communication process between the device processor and the memory, and analyzing an instruction sequence sent to the memory by the device processor in a preset time period.
Optionally, the instruction data includes an instruction sequence sent by the device processor to the memory within a preset time period, and a duration of a memory state corresponding to each instruction in the instruction sequence. The instruction sequence in the preset time period comprises at least one instruction. The processor generally waits for a period of time after sending an instruction to the memory, and then sends another instruction, and accordingly, each instruction corresponds to a time length, which is the duration of the memory state corresponding to each instruction. The memory state may be understood as the state of at least one bank in the memory. The instruction data will be described below with reference to fig. 3.
For example, fig. 3 is a schematic diagram of a command sequence corresponding to different currents provided in an embodiment of the present application. As shown in fig. 3, the command sequence corresponding to the current IDD0 includes an Act0 command and a Pre0 command, which indicate to open a bank, wait for a period of time, close the bank, and wait for a period of time. The instruction sequence corresponding to the current IDD2P includes a PreAll instruction, which indicates that the memory enters the low power mode and maintains the state without any other state change. The instruction sequence corresponding to the current IDD2PS includes a PreAll instruction, which indicates that the memory enters a low power mode, the clock input is stopped, and the state is maintained without any other state change. The command sequence corresponding to the current IDD2N includes a PreAll command, which indicates that the memory enters the precharge state and maintains the state without any other state change.
Based on the above example, by analyzing each instruction in the read instruction data, the state change of the memory in the preset time period can be determined, for example, the memory is determined to be opened after a certain bank is closed in the preset time period. The obtained instruction data provides reliable measured data for subsequent power consumption analysis, so that the power consumption prediction precision is improved.
Optionally, the target scenario includes any one of: standby, video playing, audio playing, text displaying and game executing.
For convenience of description, in the following, an arbitrary instruction in the instruction data, for example, a first instruction is taken as an example, the first instruction corresponds to a first state of the memory, and the first state includes a state of at least one storage unit in the memory. Wherein, the state of any one storage unit in the memory comprises any one of the following: closed state, open state, refresh state.
The following is a description of how to determine the power consumption of the memory corresponding to the first state according to the first instruction in the instruction data. Specifically, determining power consumption corresponding to the first state of the memory in the preset time period according to the instruction data may include the following steps:
step 2021, obtain a first state corresponding to the first instruction in the instruction data and a duration of the first state.
The duration of the first state corresponding to the first instruction is determined according to the time when the first instruction is received by the memory and the time when another instruction after the first instruction is received by the memory.
Step 2022, obtain a first predicted current value of the memory in the first state.
The first preset current value of the memory in the first state can be determined based on a first preset current formula corresponding to the first state. The first preset current formula corresponding to the first state is a predefined current formula, and the first preset current formula comprises one or more currents shown in table 1.
Illustratively, the instruction corresponding to the first state is that the processor sends a pair of bank (two bank) open and close instructions, and accordingly, the current consumed by the memory in the first state, i.e., the first preset current value iract, may be determined based on a first preset current formula corresponding to the first state. Wherein the first predetermined current formula is defined as: the Iact is IDD 0-6/8, IDD2P-IDD2N + IDD2P, and thus it can be seen that the first predetermined current formula includes three currents shown in table 1, i.e., IDD0, IDD2P, and IDD2N, respectively.
The following describes the derivation process of the first predetermined current formula Iact ═ IDD 0-6/8 × IDD2P-IDD2N + IDD2P in the above example:
in step a, IDD0 is defined as frequently switching the current of one Bank in Jedec, however, this application mode does not exist in practical application. Therefore, the inventor defines IDD0 as the current Iact consumed by sending a pair of Bank open and close commands, and the standby current of 8 banks is split into three parts of 8 equal Ipi and peripheral logic circuit current Iper, and the current combination method is more consistent with the practical application mode/scene/state of the memory.
Step b, using the application mode current defined in step a to represent the IDD current defined by Jedec, such as: IDD0 ═ Iact +8 × Ipi + Iper. Jedec of IDD2N is defined as the standby current, and IDD2N is split 8 × Ipi + Iper according to the application mode. Jedec of IDD2P is defined as a low power consumption standby current, and IDD2P is split 8 × Ipi according to the application mode. The current formula for the other application modes shown in table 1 is defined in such a way.
And c, reversely substituting the application mode current into the IDD current defined by Jedec to form formula interlocking, such as: the power consumption of a pair of Bank opening and closing instructions, Iact, IDD 0-6/8 IDD2P-IDD2N + IDD2P and IDD2P are introduced because the peripheral logic circuits basically do not consume power in the low power consumption mode, and the power consumption of 8 banks from the core array circuit region is mainly contributed.
The above embodiments only describe the first preset current formula corresponding to the first state of the memory, and the preset current formulas corresponding to other states of the memory may be defined in a similar manner.
The defined preset current formula comprises a current defined by Jedec, and IDDx defined in the Jedec specification can be related to the current of the actual application model of the memory, so that memory power consumption prediction is performed based on DRAM IDDx test data and a plurality of preset current formulas.
Based on the above example, in practical applications, a certain state of a memory in a certain period of time generally includes a plurality of bank states, and the plurality of bank states are concurrent.
In an optional embodiment of this embodiment, a first preset current formula corresponding to the first state is obtained from the database; and acquiring a first predicted current value of the memory in a first state through a first preset current formula. For example, the first predetermined current formula corresponding to the first state is Iact (IDD 0-6/8) IDD2P-IDD2N + IDD2P, and the test data IDD0, IDD2P, and IDD2N are substituted into the formula to obtain the first predicted current value Iact of the memory in the first state. The test data IDD0, IDD2P, and IDD2N are data measured based on Jedec specifications provided by DRAM manufacturers.
Step 2023, determining a first predicted power consumption corresponding to the first state according to the first predicted current value, the duration of the first state, and the preset voltage value.
The first predicted power consumption W1 corresponding to the first state may be expressed as: w1 ═ U × I1 × t1, where U denotes a preset voltage value, the preset voltage value is a fixed value, I1 denotes a first preset current value, for example, I1 is Iact, and t1 denotes the duration of the first state.
In an optional embodiment of this embodiment, the total power consumption of the memory in the preset time period is determined according to the power consumption corresponding to each state of the memory in the preset time period; and determining the average power consumption of the memory in the preset time period according to the total power consumption and the total duration of the preset time period.
For example, suppose that the processor sends 3 different instructions to the memory within a preset time period, the durations of the instructions 1, 2, and 3 are t1, t2, and t3, respectively, the memory state corresponding to the instruction 1 is state 1, the predicted current value of the state 1 is denoted as I1, the memory state corresponding to the instruction 2 is state 2, the predicted current value of the state 2 is denoted as I2, the memory state corresponding to the instruction 3 is state 3, and the predicted current value of the state 3 is denoted as I3. The supply voltage of the memory is constant and is denoted as U. Then, the total power consumption W ═ U × I1 × t1+ U × I2 × t2+ U × I3 × t3 of the memory in the preset period, and the average power consumption of the memory in the preset period
And step 204, taking the average power consumption as the predicted power consumption of the memory.
And step 205, outputting the predicted power consumption of the memory.
In an optional embodiment of this embodiment, the predicted power consumption of the memory is pushed to a terminal device of a tester, or a display interface of the processing device is directly processed to display the predicted power consumption of the memory.
According to the power consumption prediction method, instruction data of a device memory in a target scene are acquired, and the instruction data are used for indicating the state change of the memory in a preset time period; determining power consumption corresponding to each state of the memory in a preset time period according to the instruction data; determining the average power consumption of the memory in a preset time period according to the power consumption corresponding to each state of the memory in the preset time period; the average power consumption is taken as the predicted power consumption of the memory. According to the scheme, the actual state change of the memory in the preset time period is determined by analyzing the instruction data sent to the memory by the processor, the total power consumption of the memory in the preset time period is obtained by obtaining the corresponding power consumption of each state in the preset time period and combining the duration of the preset time period, the prediction result can represent the real power consumption of the memory, and the accuracy and the reliability of the prediction result are improved.
The above embodiments show the preset current formula of the memory state, for example, the first preset current formula corresponding to the first state. The preset current formula is a predefined current formula, and before the memory power consumption prediction is carried out by using the current formula, the rationality of the current formula needs to be verified.
In one embodiment, a first measured current value of the memory in the first state is obtained, and whether a first preset current formula corresponding to the first state is reasonable or not is verified by comparing the first measured current value with a first predicted current value.
The first predicted current value is determined based on a first preset current formula corresponding to the first state.
Optionally, the current value of the device power supply in the period corresponding to the first state is acquired through the detection device; and taking the current value on the power supply of the equipment in the period corresponding to the first state as a first measured current value. That is, the first measured current value is obtained by collecting the current value on the VDD power supply of the device memory during the same period (i.e., the duration of the memory in the first state). Wherein the detection device may be a multimeter.
In one possible case, if the absolute value of the difference between the first measured current value and the first predicted current value is less than the threshold, it is determined that the first preset current formula is reasonable.
In one possible case, the first predetermined current formula is determined to be unreasonable if the absolute value of the difference between the first measured current value and the first predicted current value is greater than or equal to the threshold value.
The first preset current formula is irrational, a tester needs to check whether the formula derivation process is wrong, whether formula parameters (such as the number of equipment storage units and the like) are set correctly and the like, and after the formula is readjusted, formula verification is carried out again until the requirements are met.
On the basis of the above embodiments, the following embodiment shows how to determine the power consumption distribution of different states of the memory within a preset period.
Fig. 4 is a schematic flowchart of a power consumption prediction method according to an embodiment of the present application. As shown in fig. 4, the power consumption prediction method of the present embodiment includes the following steps:
In this step, reference may be made to step 202 in the foregoing embodiment to obtain power consumption corresponding to each state of the memory in the preset time period. In this step, the total power consumption of the memory in the preset time period is the sum of the power consumptions corresponding to the states of the memory in the preset time period.
And 403, displaying a state power consumption distribution diagram, wherein the state power consumption distribution diagram is used for guiding a tester to improve the power consumption of the equipment.
For example, fig. 5 is a distribution diagram of state power consumption provided by an embodiment of the present application. Fig. 5 shows power consumption distribution of the memory state in a preset time period when the voltage of the memory is constant at U in a standby scene, and power consumption ratios corresponding to states 1 to 5 are 75%, 4%, 11%, 3%, and 7%, respectively. The tester can know that the maximum power consumption ratio of the memory in the standby scene is the state 1 based on the state power consumption distribution diagram, if the state corresponding to the expected maximum power consumption ratio in the standby scene is the state 1, the test requirement of the standby scene is met, if the state corresponding to the expected maximum power consumption ratio in the standby scene is the state 4, the test requirement of the standby scene is not met, and the tester can perform targeted optimization on the power consumption of the memory based on the power consumption ratio data. For example, the state 1 relates to the opening and closing of two banks in the memory, and the power consumption corresponding to the state 1 is too large, so that the performance of the two banks can be detected in a targeted manner, the direction is pointed out for the optimization of the memory power consumption, and the optimization efficiency of the memory power consumption is improved.
The power consumption prediction method provided in the embodiment of the present application is described above, and the power consumption prediction apparatus provided in the embodiment of the present application will be described below.
In the embodiment of the present application, the power consumption prediction apparatus may be divided into the functional modules according to the method embodiment, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a form of hardware or a form of a software functional module. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation. The following description will be given by taking an example in which each functional module is divided by using a corresponding function.
Fig. 6 is a schematic structural diagram of a power consumption prediction apparatus according to an embodiment of the present application. As shown in fig. 6, the power consumption prediction apparatus 600 according to the present embodiment includes: an acquisition module 601 and a processing module 602.
An obtaining module 601, configured to obtain instruction data of a device memory in a target scene, where the instruction data is used to indicate a state change of the memory within a preset time period;
a processing module 602, configured to determine, according to the instruction data, power consumption corresponding to each state of the memory in the preset time period;
determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
taking the average power consumption as the predicted power consumption of the memory.
In an optional embodiment of this embodiment, the instruction data includes an instruction sequence sent by the device processor to the memory within the preset time period, and a duration of the memory state corresponding to each instruction in the instruction sequence;
an obtaining module 601, configured to obtain, from a protocol analyzer, an instruction sequence of the device memory in the target scene.
In an optional embodiment of this embodiment, the obtaining module 601 is configured to obtain a first state corresponding to a first instruction in the instruction data and a duration of the first state; the first instruction is any one instruction in the instruction sequence, and the first state comprises the state of at least one storage unit in the memory;
an obtaining module 601, configured to obtain a first predicted current value of the memory in the first state;
the processing module 602 is configured to determine a first predicted power consumption corresponding to the first state according to the first predicted current value, the duration of the first state, and a preset voltage value.
In an optional embodiment of this embodiment, the obtaining module 601 is configured to:
acquiring a first preset current formula corresponding to the first state;
and acquiring a first predicted current value of the memory in the first state through the first preset current formula.
In an optional embodiment of this embodiment, the state of any one of the storage units in the memory includes any one of:
closed state, open state, refresh state.
In an optional embodiment of this embodiment, the obtaining module 601 is configured to obtain a first measured current value of the memory in the first state;
the processing module 602 is configured to verify whether the first preset current formula corresponding to the first state is reasonable by comparing the first actually measured current value with the first predicted current value.
In an optional embodiment of this embodiment, the processing module 602 is configured to:
if the absolute value of the difference value between the first measured current value and the first predicted current value is smaller than a threshold value, determining that the first preset current formula is reasonable; or
And if the absolute value of the difference value between the first actually-measured current value and the first predicted current value is greater than or equal to the threshold value, determining that the first preset current formula is unreasonable.
In an optional embodiment of this embodiment, the obtaining module 601 is configured to:
collecting the current value of the equipment power supply in the time period corresponding to the first state through detection equipment;
and taking the current value of the equipment power supply in the period corresponding to the first state as the first measured current value.
In an optional embodiment of this embodiment, the processing module 602 is configured to:
determining the total power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
and determining the average power consumption of the memory in the preset time period according to the total power consumption and the total duration of the preset time period.
Fig. 7 is a schematic structural diagram of a power consumption prediction apparatus according to an embodiment of the present application. In addition to the apparatus shown in fig. 6, as shown in fig. 7, the power consumption prediction apparatus 600 of the present embodiment further includes: a module 603 is shown.
An obtaining module 601, configured to obtain a ratio of power consumption corresponding to each state of the memory in the preset time period to total power consumption of the memory in the preset time period;
a processing module 602, configured to determine a state power consumption distribution map of the memory according to a ratio of power consumption corresponding to each state to the total power consumption;
a displaying module 603, configured to display the status power consumption distribution map, where the status power consumption distribution map is used to guide a tester to improve power consumption of the device.
In an optional embodiment of this embodiment, the target scenario includes any one of:
standby, video playing, audio playing, text displaying and game executing.
The power consumption prediction apparatus provided in this embodiment may implement the technical solutions of any of the above method embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 8 is a hardware structure diagram of an electronic device according to an embodiment of the present application. As shown in fig. 8, the electronic device 800 provided in this embodiment includes:
a memory 801;
a processor 802; and
a computer program;
the computer program is stored in the memory 801 and configured to be executed by the processor 802 to implement the technical solution of any one of the above method embodiments, which has similar implementation principles and technical effects, and is not described herein again.
Optionally, the memory 801 may be separate or integrated with the processor 802. When the memory 801 is a separate device from the processor 802, the electronic device 800 further comprises: a bus 803 for connecting the memory 801 and the processor 802.
The embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by the processor 802 to implement the technical solution of any one of the foregoing method embodiments.
An embodiment of the present application provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the computer program implements the technical solutions of any of the foregoing method embodiments.
An embodiment of the present application further provides a chip, including: a processing module and a communication interface, the processing module being capable of performing the solution of any of the method embodiments described above.
Further, the chip further includes a storage module (e.g., a memory), the storage module is configured to store instructions, the processing module is configured to execute the instructions stored in the storage module, and the execution of the instructions stored in the storage module causes the processing module to execute the technical solution of any one of the foregoing method embodiments.
It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.
The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, etc.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The storage medium may be implemented by any type or combination of volatile and non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the storage medium may reside as discrete components in an electronic device.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (15)
1. A method for power consumption prediction, comprising:
acquiring instruction data of a device memory in a target scene, wherein the instruction data is used for indicating the state change of the memory in a preset time period;
determining power consumption corresponding to each state of the memory in the preset time period according to the instruction data;
determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
taking the average power consumption as the predicted power consumption of the memory.
2. The method according to claim 1, wherein the instruction data includes a sequence of instructions sent by a device processor to the memory within the preset time period, and a duration of the memory state corresponding to each instruction in the sequence of instructions;
the acquiring of the instruction data of the device memory in the target scene includes:
obtaining a sequence of instructions of the device memory in the target scenario from a protocol analyzer.
3. The method of claim 1, wherein the determining the power consumption corresponding to each state of the memory in the preset time period according to the instruction data comprises:
acquiring a first state corresponding to a first instruction in the instruction data and the duration of the first state; the first instruction is any one instruction in the instruction sequence, and the first state comprises the state of at least one storage unit in the memory;
acquiring a first predicted current value of the memory in the first state;
and determining first predicted power consumption corresponding to the first state according to the first predicted current value, the duration of the first state and a preset voltage value.
4. The method of claim 3, wherein obtaining the first predicted current value for the memory in the first state comprises:
acquiring a first preset current formula corresponding to the first state;
and acquiring a first predicted current value of the memory in the first state through the first preset current formula.
5. The method of claim 3, wherein the state of any one of the memory cells in the memory comprises any one of:
closed state, open state, refresh state.
6. The method of claim 3, further comprising:
acquiring a first measured current value of the memory in the first state;
and verifying whether a first preset current formula corresponding to the first state is reasonable or not by comparing the first actually-measured current value with the first predicted current value.
7. The method of claim 6, wherein verifying whether a first predetermined current formula corresponding to the first state is rational by comparing the first measured current value with the first predicted current value comprises:
if the absolute value of the difference value between the first measured current value and the first predicted current value is smaller than a threshold value, determining that the first preset current formula is reasonable; or
And if the absolute value of the difference value between the first actually-measured current value and the first predicted current value is greater than or equal to the threshold value, determining that the first preset current formula is unreasonable.
8. The method of claim 6, wherein said obtaining a first measured current value of said memory in said first state comprises:
acquiring a current value on the equipment power supply in a period corresponding to the first state through detection equipment;
and taking the current value of the equipment power supply in the period corresponding to the first state as the first measured current value.
9. The method according to any one of claims 1 to 8, wherein the determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period comprises:
determining the total power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
and determining the average power consumption of the memory in the preset time period according to the total power consumption and the total duration of the preset time period.
10. The method according to any one of claims 1 to 8,
the method further comprises the following steps: acquiring the ratio of the power consumption corresponding to each state of the memory in the preset time period to the total power consumption of the memory in the preset time period;
determining a state power consumption distribution diagram of the memory according to the ratio of the power consumption corresponding to each state to the total power consumption;
and displaying the state power consumption distribution diagram, wherein the state power consumption distribution diagram is used for guiding a tester to improve the power consumption of the equipment.
11. The method of any one of claims 1 to 8, wherein the target scene comprises any one of:
standby, video playing, audio playing, text displaying and game executing.
12. A power consumption prediction apparatus, comprising:
the device comprises an acquisition module, a storage module and a control module, wherein the acquisition module is used for acquiring instruction data of a device memory in a target scene, and the instruction data is used for indicating the state change of the memory in a preset time period;
the processing module is used for determining power consumption corresponding to each state of the memory in the preset time period according to the instruction data;
determining the average power consumption of the memory in the preset time period according to the power consumption corresponding to each state of the memory in the preset time period;
taking the average power consumption as the predicted power consumption of the memory.
13. An electronic device, comprising:
a memory;
a processor; and
a computer program;
wherein the computer program is stored in the memory and configured to be executed by the processor to implement the method of any one of claims 1 to 11.
14. A computer-readable storage medium, having stored thereon a computer program for execution by a processor to perform the method of any one of claims 1 to 11.
15. A computer program product, characterized in that it comprises a computer program which, when executed by a processor, implements the method of any one of claims 1 to 11.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116090388A (en) * | 2022-12-21 | 2023-05-09 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
| CN117971438A (en) * | 2024-03-29 | 2024-05-03 | 浪潮电子信息产业股份有限公司 | System power consumption management method and device, electronic equipment and readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116090388A (en) * | 2022-12-21 | 2023-05-09 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
| CN116090388B (en) * | 2022-12-21 | 2024-05-17 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
| CN117971438A (en) * | 2024-03-29 | 2024-05-03 | 浪潮电子信息产业股份有限公司 | System power consumption management method and device, electronic equipment and readable storage medium |
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