CN112083882B - SRAM (static random Access memory) dead point processing method, system and device and computer equipment - Google Patents
SRAM (static random Access memory) dead point processing method, system and device and computer equipment Download PDFInfo
- Publication number
- CN112083882B CN112083882B CN202010921042.4A CN202010921042A CN112083882B CN 112083882 B CN112083882 B CN 112083882B CN 202010921042 A CN202010921042 A CN 202010921042A CN 112083882 B CN112083882 B CN 112083882B
- Authority
- CN
- China
- Prior art keywords
- address
- dead pixel
- sram
- data
- access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003068 static effect Effects 0.000 title claims abstract description 9
- 238000003672 processing method Methods 0.000 title description 9
- 238000000034 method Methods 0.000 claims abstract description 49
- 230000015654 memory Effects 0.000 claims abstract description 31
- 238000012545 processing Methods 0.000 claims abstract description 16
- 238000004590 computer program Methods 0.000 claims description 13
- 238000007726 management method Methods 0.000 description 61
- 238000010586 diagram Methods 0.000 description 9
- 230000007547 defect Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
- G06F3/0607—Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/008—Reliability or availability analysis
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Quality & Reliability (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application relates to the technical field of memories, and provides a method, a system and a device for processing SRAM (static random access memory) bad points, computer equipment and a storage medium. The method comprises the following steps: the access address aiming at the SRAM obtained by the data access module is received and matched with the dead pixel address stored in the information register after being scanned by the CPU, so that a target dead pixel address matched with the access address is obtained, the data register corresponding to the target dead pixel address is obtained, and corresponding data content is read and written from the data register. According to the scheme provided by the application, the dead pixel addresses scanned by the CPU are stored in the information register, the corresponding data registers are configured for the respective dead pixel addresses in advance and used for storing the data contents corresponding to the dead pixel addresses, so that the dead pixel conditions of the SRAM can be dynamically managed in the using process of the SRAM, the data contents of the SRAM corresponding to the dead pixel addresses are read and written through the data registers, the replacement operation of the dead pixels of the SRAM is realized, the efficiency of SRAM dead pixel management is improved, and the reliability of the SRAM is further improved.
Description
Technical Field
The present application relates to the field of memory technologies, and in particular, to a method, a system, an apparatus, a computer device, and a storage medium for processing a SRAM dead point.
Background
A Static Random-Access Memory (SRAM) is one type of Random Access Memory, and is widely used for cache of a chip, and when an address unit of the SRAM fails, the whole SRAM cannot work normally, thereby affecting functions of the chip. Therefore, during the shipping and using processes of the chip, the defect condition of the SRAM needs to be tested.
In the prior art, generally, when a chip leaves a factory, a method of adding redundant columns and redundant rows is adopted for replacing dead pixels of an SRAM, the manufacturing process is complex, and the dead pixels in the using process cannot be replaced.
Disclosure of Invention
Based on this, it is necessary to provide a method, a system, an apparatus, a computer device and a storage medium for SRAM bad point processing, which are directed to the technical problem of SRAM bad point processing in the prior art.
A method of SRAM bad point handling, the method comprising:
receiving an access address aiming at the SRAM obtained by a data access module;
obtaining a dead pixel address stored in an information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU;
matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matched with the access address;
and acquiring a data register corresponding to the target dead pixel address, and reading and writing data content corresponding to the target dead pixel address from the data register.
In one embodiment, the method further comprises:
receiving a dead pixel address of the SRAM scanned by the CPU;
storing the dead pixel address in the information register;
configuring a corresponding data register for each dead pixel address in the information register, and storing the configuration information; the data register is used for accessing the data content corresponding to the dead pixel address.
In one embodiment, the tasks corresponding to the access addresses comprise a writing task and a reading task for the SRAM; the reading and writing of the data content corresponding to the target dead pixel address from the data register includes:
if the task is confirmed to be a write-in task, writing the data content corresponding to the access address into a data register corresponding to the target dead pixel address;
and if the task is determined to be a reading task, acquiring the data content corresponding to the target dead pixel address from the data register, and returning the data content to the data access module.
In one embodiment, after the matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matching the access address, the method further includes:
if the task corresponding to the access address is determined to be a writing task, acquiring data content corresponding to the access address; and writing the data content corresponding to the access address into the SRAM storage address corresponding to the access address.
In one embodiment, the method further comprises:
and if the information register does not contain the dead pixel address corresponding to the access address, reading and writing data content corresponding to the access address from the SRAM.
In one embodiment, the data access module includes at least one of a CPU and a DMA.
An SRAM (static random access memory) dead pixel management system comprises a CPU (central processing unit), a data register, an information register and an SRAM (static random access memory), wherein a dead pixel manager is configured in the SRAM, and the dead pixel management system comprises:
the CPU is used for scanning a dead pixel address of the SRAM, sending the dead pixel address to the dead pixel manager, acquiring an access address aiming at the SRAM and sending the access address to the dead pixel manager;
the dead pixel manager is configured to store the dead pixel addresses in the information register, configure a corresponding data register for each dead pixel address in the information register, and perform SRAM dead pixel management according to any one of the above methods.
An SRAM bad point processing apparatus, the apparatus comprising:
the access address receiving module is used for receiving the access address aiming at the SRAM obtained by the data access module;
the dead pixel address acquisition module is used for acquiring the dead pixel address stored in the information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU;
the matching module is used for matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matched with the access address;
and the data reading and writing module is used for acquiring a data register corresponding to the target dead pixel address and reading and writing data content corresponding to the target dead pixel address from the data register.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the following steps when executing the computer program:
receiving an access address aiming at the SRAM obtained by a data access module; obtaining a dead pixel address stored in an information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU; matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matched with the access address; and acquiring a data register corresponding to the target dead pixel address, and reading and writing data content corresponding to the target dead pixel address from the data register.
A computer-readable storage medium, on which a computer program is stored which, when executed by a processor, carries out the steps of:
receiving an access address aiming at the SRAM obtained by a data access module; obtaining a dead pixel address stored in an information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU; matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matched with the access address; and acquiring a data register corresponding to the target dead pixel address, and reading and writing data content corresponding to the target dead pixel address from the data register.
According to the SRAM dead pixel processing method, the system, the device, the computer equipment and the storage medium, the access address aiming at the SRAM, which is obtained by the data access module, is matched with the dead pixel address stored in the information register after being scanned by the CPU, the target dead pixel address matched with the access address is obtained, the data register corresponding to the target dead pixel address is obtained, and the corresponding data content is read and written from the data register. According to the scheme provided by the application, the dead pixel addresses scanned by the CPU are stored in the information register, the corresponding data registers are configured for the respective dead pixel addresses in advance and used for storing the data contents corresponding to the dead pixel addresses, so that the dead pixel conditions of the SRAM can be dynamically managed in the using process of the SRAM, the data contents of the SRAM corresponding to the dead pixel addresses are read and written through the data registers, the replacement operation of the dead pixels of the SRAM is realized, the efficiency of SRAM dead pixel management is improved, and the reliability of the SRAM is further improved.
Drawings
FIG. 1 is a flow chart illustrating a method for handling SRAM bad bits in one embodiment;
FIG. 2 is a system diagram of a dynamic replacement and management system for SRAM bad pixels in one embodiment;
FIG. 3 is a system diagram of a dynamic replacement and management system for SRAM bad pixels in one embodiment;
FIG. 4 is a flow chart illustrating a method for dynamically replacing and managing SRAM bad pixels in the SRAM bad pixel dynamic replacement and management system according to an embodiment;
FIG. 5 is a flow chart illustrating a method for dynamically replacing and managing SRAM bad pixels in the SRAM bad pixel dynamic replacement and management system according to an embodiment;
FIG. 6 is a flow chart illustrating a method for dynamically replacing and managing SRAM bad pixels in the SRAM bad pixel dynamic replacement and management system according to an embodiment;
FIG. 7 is a block diagram of an SRAM dead pixel management system in one embodiment;
FIG. 8 is a block diagram of an SRAM bad point processing apparatus in one embodiment;
FIG. 9 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The SRAM dead pixel processing method can be applied to a dead pixel management unit of a chip, and the dead pixel management unit can be an independent control device, such as a dead pixel manager; or may be a functional block in the system-on-chip. The dead pixel management unit can comprise an information register and a data register, and performs read-write operation on data content stored in the data register and corresponding to the SRAM dead pixel address according to an access request of a CPU or other peripheral IP.
In one embodiment, as shown in fig. 1, an SRAM bad pixel processing method is provided, which is described by taking the method as an example for being applied to the above-mentioned bad pixel management unit, and includes the following steps:
step S101, receiving an access address aiming at the SRAM obtained by the data access module.
The data Access module may be a CPU or a DMA (Direct Memory Access), and may be configured to acquire an Access address, which is input by a user and is directed to the SRAM. The access address may be an address corresponding to an address where the SRAM stores corresponding data content, and the SRAM may determine a position where data is read and written according to the access address. When the dead pixel address exists in the SRAM, the dead pixel management unit can determine a corresponding replacement storage address according to the dead pixel address so as to ensure that the data read-write operation of the SRAM is normally carried out.
In specific implementation, the data access module can send the access address of the user for the SRAM to the dead pixel management unit after acquiring the access address, and the dead pixel management unit can receive the access address of the data access module to obtain the access requirement of the user.
Step S102, the dead pixel address stored in the information register is obtained.
The CPU can perform scanning test on the SRAM in the process of leaving a factory or using the chip, and configures the scanned dead pixel address into a preset information register, and the dead pixel address in the information register can be updated at any time. In addition, the information register can also be used for storing the dead pixel address of the SRAM scanned by the CPU.
In a specific implementation, the dead pixel management unit can obtain a dead pixel address of the SRAM configured in the information register after being scanned by the CPU from the information register in the use process of the SRAM.
And step S103, matching the access address with each dead pixel address in the information register to obtain a target dead pixel address matched with the access address.
The access address obtained by the data access module usually corresponds to a storage address of the SRAM, and when the SRAM has a dead pixel, data reading from the dead pixel address cannot be performed. Therefore, the dead pixel management unit needs to match the obtained access address with each dead pixel address in the information register to determine whether the SRAM storage address corresponding to the access address is a dead pixel address. When the access address is matched with the dead pixel address, the dead pixel management unit can read and write corresponding data content from the replacement module corresponding to the dead pixel address. The replacement module may be a data register corresponding to the dead pixel address.
In a specific implementation, the dead pixel management unit may match the access address with each dead pixel address in the information register, and if the access address is the same as one of each dead pixel address in the information register, the same dead pixel address may be used as the target dead pixel address.
And step S104, acquiring a data register corresponding to the target dead pixel address, and reading and writing data content corresponding to the target dead pixel address from the data register.
The data registers can correspond to the dead pixel addresses, each dead pixel address can correspond to one data register, data contents corresponding to the SRAM dead pixel addresses can be stored in the data registers, and the number and the addresses of the data registers can be dynamically configured according to the dead pixel addresses. Therefore, the data register can be regarded as a replacement module of the SRAM dead point address, and the data content stored in the data register can be read and written. The bit width of the data register may not be limited, and may be consistent with the data bit width of a single address of the system SRAM.
In a specific implementation, the dead pixel management unit may determine the data register corresponding to the target dead pixel address according to a pre-configured corresponding relationship between the dead pixel address and the data register, and read and write data content corresponding to the target dead pixel address from the data register.
In the SRAM dead pixel processing method, the access address aiming at the SRAM, which is obtained by the data access module, is received and matched with the dead pixel address stored in the information register after being scanned by the CPU, so that a target dead pixel address matched with the access address is obtained, the data register corresponding to the target dead pixel address is obtained, and the corresponding data content is read and written from the data register. In the scheme, the dead pixel addresses scanned by the CPU are stored in the information register, and the corresponding data registers are configured for the respective dead pixel addresses in advance to store the data contents corresponding to the dead pixel addresses, so that the dead pixel conditions of the SRAM can be dynamically managed in the use process of the SRAM, the data contents of the SRAM corresponding to the dead pixel addresses are read and written through the data registers, the replacement operation of the dead pixels of the SRAM is realized, the efficiency of SRAM dead pixel management is improved, and the reliability of the SRAM is further improved.
In one embodiment, the method further comprises:
receiving a dead pixel address of the SRAM scanned by the CPU; storing the dead pixel address in an information register; and configuring a corresponding data register for each dead pixel address in the information register, and storing the configuration information.
In this embodiment, the data register is used to access the data content corresponding to the dead pixel address. The dead pixel management unit can receive the SRAM dead pixel address scanned by the CPU. The CPU can scan the SRAM dead pixel address when the chip leaves a factory or when the chip is used, so as to update the dead pixel address. The CPU can store the dead pixel address in the nonvolatile memory, and after the chip is powered on, the CPU can read the dead pixel address from the nonvolatile memory and send the dead pixel address to the dead pixel management unit. In some cases, the defect address may also be read from the nonvolatile memory by the DMA and sent to the defect management unit. The dead pixel management unit can store the dead pixel addresses in the information register, configure the corresponding data register according to each dead pixel address in the information register, and configure the data content stored in the SRAM corresponding to the dead pixel address into the corresponding data register. The configuration information may be a corresponding relationship between the dead pixel address and the data register, and data content stored in the SRAM corresponding to the dead pixel address. The data register is used for storing the dead point data, so that the storage space of the SRAM is not wasted, the problem that dead points also occur in a backup area caused by the traditional backup in the SRAM is solved, and meanwhile, a user can continuously access the storage space of the whole SRAM when the dead points exist in the SRAM.
In the scheme of the embodiment, the dead pixel management unit stores the dead pixel addresses in the information register by receiving the dead pixel addresses of the SRAM scanned by the CPU, configures corresponding data registers for the respective dead pixel addresses, and stores data contents corresponding to the dead pixel addresses, so that the dead pixel addresses have corresponding replacement modules, thereby improving the reliability of the SRAM.
In one embodiment, the tasks corresponding to the access addresses include a write task and a read task for the SRAM, and the step of reading and writing the data content corresponding to the target dead pixel address from the data register determined in step S104 includes:
if the task is confirmed to be a write-in task, writing the data content corresponding to the access address into a data register corresponding to the target dead pixel address; and if the task is determined to be a reading task, acquiring the data content corresponding to the target dead pixel address from the data register and returning the data content to the data access module.
In this embodiment, the access address sent by the data access module may include a write task and a read task for the SRAM, where the write task may be that a user writes corresponding data content into an SRAM storage address corresponding to the access address, and the read task may be that a user reads the data content stored in the address from the SRAM storage address corresponding to the access address. When the SRAM storage address is a dead pixel address, the dead pixel management unit can perform read-write operation of data content according to different tasks through a data register corresponding to the dead pixel address. Under the reading task, the dead pixel management unit can select the data content corresponding to the reading access address from the SRAM or the data register through the data selector, does not select when data are written, and selects through the data selector when data are read, so that the circuit structure of the chip can be simplified.
In some implementations, when the task corresponding to the access address is a write task, the dead pixel management unit may match the target dead pixel address according to the access address, determine a data register corresponding to the target dead pixel address, and write data content corresponding to the access address into the data register under the write task.
In some embodiments, when the task corresponding to the access address is a read task, the dead pixel management unit may match the target dead pixel address according to the access address, determine a data register corresponding to the target dead pixel address, acquire, through the data selector, data content corresponding to the target dead pixel address from the data register in the read task, and return the data content to the data access module.
In the above-mentioned embodiment, the dead pixel management unit determines the target dead pixel address corresponding to the access address according to the write task and the read task corresponding to the SRAM corresponding to the access address, and reads and writes the corresponding data content from the data register corresponding to the target dead pixel address, so that the dead pixel management unit can read and write from the data register when the SRAM has a dead pixel, thereby improving the reliability of the SRAM.
In one embodiment, after the step S103 determines to match the access address with each dead pixel address in the information register, and obtain a target dead pixel address matching the access address, the method further includes:
if the task corresponding to the access address is determined to be a writing task, acquiring data content corresponding to the access address; and writing the data content corresponding to the access address into the SRAM storage address corresponding to the access address.
In this embodiment, when the task corresponding to the access address is a write task, the dead pixel management unit may obtain data content corresponding to the access address, and write the data content into the SRAM storage address corresponding to the access address. That is, even if there is a SRAM dead pixel, the dead pixel manager can write the data content corresponding to the access address into the SRAM in a write task, so as to improve the fault tolerance of the SRAM dead pixel management.
In one embodiment, the method further comprises:
and if the information register does not contain the dead pixel address corresponding to the access address, reading and writing the data content corresponding to the access address from the SRAM.
In this embodiment, when the access address acquired by the dead pixel management unit does not have a corresponding dead pixel address in the information register, it indicates that the SRAM storage address corresponding to the access address is available, so that the dead pixel management unit can read and write data content corresponding to the access address according to the SRAM storage address corresponding to the access address. The step of reading and writing the corresponding data content from the SRAM by the dead pixel management unit may be the same as the step of reading the data content from a certain data register.
According to the scheme of the embodiment, under the condition that the access address is not matched with the corresponding dead pixel address, the dead pixel management unit can read and write the data content corresponding to the access address from the SRAM according to the access address, and the SRAM read and write efficiency and reliability can be improved by screening the dead pixel address of the SRAM.
In one embodiment, the data access module may include at least one of a CPU and a DMA. The SRAM can be read and written by the CPU, DMA or other peripheral IP. Therefore, the dead pixel management unit can perform read-write operation on the SRAM and the data register or perform read-write operation on the SRAM and the data register according to the access address acquired by the CPU, the DMA or other peripheral IP.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a portion of the steps in fig. 1 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.
In order to more clearly illustrate the above scheme of the present application, the following further describes the application of the SRAM dead-point processing method in the SRAM dead-point dynamic replacement and management system.
Fig. 2 is a system structure diagram of a SRAM dead pixel dynamic replacement and management system, the main structure of which includes three major parts, namely a CPU, a nonvolatile memory and a dead pixel management unit, and the dead pixel management unit includes an SRAM, an information register, a data register and a data selector module. The dead pixel management unit may be an independent control device, or may be a functional module in the system chip, and its existing form needs to be selected according to the actual use situation. The dead pixel management unit can be configured in the process of delivery and use of the chip, so that dynamic update of the dead pixel information is realized. The dead pixel management unit can also be only composed of an information register, a data register and a data selector module to control the SRAM outside the dead pixel management unit. The types of the CPU and the nonvolatile memory are not limited, the nonvolatile memory stores the addresses and the number of the dead pixels, data cannot be lost after power failure, and the CPU can modify the data of the nonvolatile memory after power on.
Fig. 3 is a system block diagram of a dynamic SRAM dead pixel replacement and management system, which shows an application environment of the dynamic SRAM dead pixel replacement and management system in some cases, including CPU, DMA, nonvolatile memory, SRAM with a dead pixel management unit, system controller, other peripherals, and the like. The system parts are connected by a system bus.
Fig. 4 is a specific flowchart of SRAM dead pixel processing in the SRAM dead pixel dynamic replacement and management system. The method comprises the following steps: step S401, the CPU carries out scanning test on the SRAM and records the dead pixel information into a nonvolatile memory; step S402, after the chip is powered on, the CPU configures the relevant dead pixel information into an information register of a dead pixel management unit; step S403, the dead pixel management unit configures data registers according to dead pixel addresses, wherein each dead pixel address corresponds to one data register; step S404, when data is written, if the access address is matched with the dead pixel address, the data content corresponding to the access address is written into the data register corresponding to the dead pixel address; step S405, when data is read, if the access address is matched with the dead pixel address, the data selector inputs the data content of the data register corresponding to the dead pixel address; and if the access address does not match the dead pixel address, outputting the data content corresponding to the SRAM.
Fig. 5 is a flowchart of SRAM dead pixel processing performed in the SRAM dead pixel dynamic replacement and management system, and specifically discloses the data writing process in step S404.
Fig. 6 is a flowchart of SRAM dead pixel processing performed in the SRAM dead pixel dynamic replacement and management system, and specifically discloses the process of data reading in step S405 above.
In one embodiment, as shown in fig. 7, an SRAM dead pixel management system is provided, which comprises a CPU 701, a data register 702, an information register 703 and an SRAM 704, wherein the SRAM 704 is configured with a dead pixel manager 705 therein, wherein,
a CPU 701 configured to scan a dead pixel address of the SRAM 704, send the dead pixel address to the dead pixel manager 705, obtain an access address for the SRAM 704, and send the access address to the dead pixel manager 705;
the dead pixel manager 705 is configured to store a dead pixel address in the information register 703, configure a corresponding data register 702 for each dead pixel address in the information register 703, and perform SRAM dead pixel management according to the method described in any of the above method embodiments.
According to the SRAM dead pixel management system, the CPU scans the dead pixel address and sends the dead pixel address to the dead pixel manager 705, the dead pixel manager 705 configures and stores the dead pixel address to the information register 703 and configures the data register 702 corresponding to the dead pixel address, so that the dead pixel condition of the SRAM can be dynamically managed, the data register 702 realizes reading and writing of the data content of the SRAM corresponding to the dead pixel address, the replacement operation of the dead pixel of the SRAM is realized, the SRAM dead pixel management efficiency is improved, and the reliability of the SRAM is further improved.
In one embodiment, as shown in fig. 8, there is provided an SRAM bad point processing apparatus 800, the apparatus comprising:
an access address receiving module 801, configured to receive an access address for the SRAM obtained by the data access module;
a dead pixel address obtaining module 802, configured to obtain a dead pixel address stored in the information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU;
a matching module 803, configured to match the access address with each dead pixel address in the information register, to obtain a target dead pixel address matched with the access address;
and the data reading and writing module 804 is configured to obtain a data register corresponding to the target dead pixel address, and read and write data content corresponding to the target dead pixel address from the data register.
In one embodiment, the apparatus 800 is further configured to receive a dead pixel address of the SRAM scanned by the CPU; storing the dead pixel address in an information register; configuring corresponding data registers for each dead pixel address in the information register, and storing configuration information; the data register is used for accessing the data content corresponding to the dead pixel address.
In one embodiment, the tasks corresponding to the access address include a write task and a read task for the SRAM, and the data read/write module 804 is further configured to write the data content corresponding to the access address into the data register corresponding to the target dead pixel address if it is determined that the task is the write task; and if the task is determined to be a reading task, acquiring the data content corresponding to the target dead pixel address from the data register and returning the data content to the data access module.
In an embodiment, the apparatus 800 is further configured to, if it is determined that the task corresponding to the access address is a write task, obtain data content corresponding to the access address; and writing the data content corresponding to the access address into the SRAM storage address corresponding to the access address.
In one embodiment, the apparatus 800 is further configured to read and write data content corresponding to the access address from the SRAM if the information register does not include the defect address corresponding to the access address.
In one embodiment, the apparatus 800 further comprises: the data access module includes at least one of a CPU and a DMA.
For the specific definition of the SRAM bad point processing apparatus, reference may be made to the above definition of the SRAM bad point processing method, which is not described herein again. The various modules in the SRAM dead-end processing apparatus described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
The SRAM dead-spot processing method provided by the present application may be applied to a computer device, where the computer device may be a server, and its internal structure diagram may be as shown in fig. 9. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing the obtained dead pixel addresses and the corresponding data content. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method of SRAM bad point handling.
Those skilled in the art will appreciate that the architecture shown in fig. 9 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the above-described method embodiments when executing the computer program.
In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (13)
1. A method for SRAM bad point processing, the method comprising:
receiving an access address aiming at the SRAM obtained by a data access module; tasks corresponding to the access addresses comprise a writing task and a reading task aiming at the SRAM;
obtaining a dead pixel address stored in an information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU;
matching the access address with each dead pixel address in the information register to determine whether the storage address of the SRAM corresponding to the access address is a dead pixel address, and obtaining a target dead pixel address matched with the access address when matching is successful;
acquiring a data register corresponding to the target dead pixel address, wherein the data register is used for accessing data content corresponding to the dead pixel address;
if the task is determined to be a reading task, selecting to read the data content corresponding to the target dead pixel address from the data register through a data selector, and returning the data content to the data access module;
and if the task is confirmed to be a writing task, the data content corresponding to the access address is directly written into the data register without selection.
2. The method of claim 1, further comprising:
receiving a dead pixel address of the SRAM scanned by the CPU;
storing the dead pixel address in the information register;
and configuring a corresponding data register for each dead pixel address in the information register, and storing configuration information.
3. The method of claim 1, wherein the matching the access address with each bad point address in the information register is performed to determine whether a storage address of the SRAM corresponding to the access address is a bad point address, and when the matching is successful, after obtaining a target bad point address matching the access address, the method further comprises:
if the task corresponding to the access address is determined to be a writing task, acquiring data content corresponding to the access address; and writing the data content corresponding to the access address into the SRAM storage address corresponding to the access address.
4. The method of claim 1, further comprising:
and if the information register does not contain the dead pixel address corresponding to the access address, reading and writing data content corresponding to the access address from the SRAM.
5. The method of any of claims 1 to 4, wherein the data access module comprises at least one of a CPU and a DMA.
6. An SRAM (static random access memory) dead pixel management system is characterized by comprising a CPU (central processing unit), a data register, an information register and an SRAM (static random access memory), wherein a dead pixel manager is configured in the SRAM, and the dead pixel management system comprises:
the CPU is used for scanning a dead pixel address of the SRAM, sending the dead pixel address to the dead pixel manager, acquiring an access address aiming at the SRAM and sending the access address to the dead pixel manager;
the dead pixel manager is used for storing the dead pixel addresses into the information register, configuring corresponding data registers for the dead pixel addresses in the information register, and performing SRAM dead pixel management according to the method of any one of claims 1 to 5.
7. An SRAM bad point processing apparatus, comprising:
the access address receiving module is used for receiving the access address aiming at the SRAM obtained by the data access module; tasks corresponding to the access addresses comprise a writing task and a reading task aiming at the SRAM;
the dead pixel address acquisition module is used for acquiring the dead pixel address stored in the information register; the information register is used for storing the dead pixel address of the SRAM scanned by the CPU;
the matching module is used for matching the access address with each dead pixel address in the information register so as to determine whether the storage address of the SRAM corresponding to the access address is a dead pixel address or not, and when the matching is successful, a target dead pixel address matched with the access address is obtained;
the data reading and writing module is used for acquiring a data register corresponding to the target dead pixel address, and the data register is used for accessing data content corresponding to the dead pixel address; if the task is determined to be a reading task, selecting to read the data content corresponding to the target dead pixel address from the data register through a data selector, and returning the data content to the data access module; and if the task is confirmed to be a writing task, the data content corresponding to the access address is directly written into the data register without selection.
8. The apparatus of claim 7, wherein the apparatus is further configured to receive a dead pixel address of the SRAM scanned by a CPU; storing the dead pixel address in the information register; and configuring a corresponding data register for each dead pixel address in the information register, and storing configuration information.
9. The apparatus according to claim 7, wherein the apparatus is further configured to, if it is determined that the task corresponding to the access address is a write task, obtain data content corresponding to the access address; and writing the data content corresponding to the access address into the SRAM storage address corresponding to the access address.
10. The apparatus of claim 7, further configured to read and write data content corresponding to the access address from the SRAM if the information register does not contain a bad pixel address corresponding to the access address.
11. The apparatus of any of claims 7 to 10, wherein the data access module comprises at least one of a CPU and a DMA.
12. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 5.
13. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010921042.4A CN112083882B (en) | 2020-09-04 | 2020-09-04 | SRAM (static random Access memory) dead point processing method, system and device and computer equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010921042.4A CN112083882B (en) | 2020-09-04 | 2020-09-04 | SRAM (static random Access memory) dead point processing method, system and device and computer equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112083882A CN112083882A (en) | 2020-12-15 |
| CN112083882B true CN112083882B (en) | 2021-12-17 |
Family
ID=73732824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010921042.4A Active CN112083882B (en) | 2020-09-04 | 2020-09-04 | SRAM (static random Access memory) dead point processing method, system and device and computer equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112083882B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112783742B (en) * | 2021-01-15 | 2022-06-14 | 苏州浪潮智能科技有限公司 | Method and device for counting CPU frequency and voltage and electronic equipment |
| CN113312676B (en) * | 2021-05-25 | 2022-07-19 | 飞腾信息技术有限公司 | Data access method and device, computer equipment and readable storage medium |
| CN116312671B (en) * | 2023-05-19 | 2023-08-29 | 珠海妙存科技有限公司 | SRAM resetting method, circuit, chip, device and medium |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098103B (en) * | 2016-06-03 | 2019-10-18 | 北京兆易创新科技股份有限公司 | The replacement method of bad point unit in a kind of nonvolatile memory |
| CN107908506A (en) * | 2017-09-28 | 2018-04-13 | 芯海科技（深圳）股份有限公司 | A kind of implementation method of memory bad point management |
| CN109726040B (en) * | 2017-10-31 | 2024-04-26 | 华润微集成电路(无锡)有限公司 | Small-capacity OTPROM memory with fault-tolerant mechanism and fault-tolerant control method thereof |
-
2020
- 2020-09-04 CN CN202010921042.4A patent/CN112083882B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN112083882A (en) | 2020-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112083882B (en) | SRAM (static random Access memory) dead point processing method, system and device and computer equipment | |
| US20070016719A1 (en) | Memory device including nonvolatile memory and memory controller | |
| US20080082737A1 (en) | Memory card and semiconductor device | |
| CN110555041A (en) | Data processing method, data processing device, computer equipment and storage medium | |
| US11816038B2 (en) | Method and apparatus of mapping table reconstruction based on SSD, and computer device | |
| US20030212922A1 (en) | Computer system and methods for acquiring dump information and system recovery | |
| US11442636B2 (en) | Method, apparatus for managing the redundant array of independent disks (RAID) and related computer readable medium | |
| CN108829347A (en) | A kind of hardware control, control method and the liquid crystal display of Nand equipment | |
| CN114968130B (en) | Chain table initialization device, method, system, computer equipment and storage medium | |
| CN115129519A (en) | Method and system for realizing multiple write operations of chip with efuse structure and SOC (system on chip) | |
| CA3129982A1 (en) | Method and system for accessing distributed block storage system in kernel mode | |
| CN117406932A (en) | Data processing method, device, server and storage medium | |
| CN115686932A (en) | Backup set file recovery method and device and computer equipment | |
| CN111026417A (en) | Embedded equipment upgrading method and embedded equipment | |
| CN111966531B (en) | Data snapshot method and device, computer equipment and storage medium | |
| US6934537B2 (en) | Radio communication device, method of and program for rewriting boot program therefor | |
| CN114610230B (en) | Flash memory data exchange method and terminal based on single chip microcomputer | |
| CN114138176B (en) | Nor Flash erasing and upgrading method and device, computer equipment and storage medium | |
| CN111651124B (en) | Parallel reconstruction method, device, equipment and medium for SSD mapping table multi-core partition | |
| CN112000591B (en) | SSD scanning method capable of designating logical block address, SSD scanning device, SSD scanning computer equipment and storage medium | |
| US20200272366A1 (en) | Semiconductor Device and Debug System | |
| CN111666103A (en) | Instruction processing method and device | |
| CN112988037A (en) | Static wear leveling method, terminal and computer-readable storage medium | |
| JP4239754B2 (en) | Nonvolatile memory system | |
| CN114710441B (en) | Link aggregation method, system, computer equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |