CN116312671B - SRAM resetting method, circuit, chip, device and medium - Google Patents
SRAM resetting method, circuit, chip, device and medium Download PDFInfo
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- CN116312671B CN116312671B CN202310570789.3A CN202310570789A CN116312671B CN 116312671 B CN116312671 B CN 116312671B CN 202310570789 A CN202310570789 A CN 202310570789A CN 116312671 B CN116312671 B CN 116312671B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application discloses an SRAM resetting method, a circuit, a chip, a device and a storage medium, wherein the method is used for resetting an SRAM through a peripheral circuit; the peripheral circuit includes a register; the number of registers is equal to the number of addresses of the SRAM; any one address of the SRAM corresponds to any one register, and the method comprises the following steps: resetting each register to a first preset value in response to the received reset signal; determining a write circuit to write first data to any one address in the SRAM, and setting a register corresponding to any one address in the SRAM as a second preset value; when the read-out circuit reads out data from any one address in the SRAM, the read-out data of the read-out circuit is adjusted according to the first preset value and the second preset value. The method can improve the adaptability of the SRAM and the practicability of the SRAM. The application can be widely applied to the technical field of chip circuit design.
Description
Technical Field
The application relates to the technical field of chip circuit design, in particular to an SRAM resetting method, an SRAM resetting circuit, an SRAM resetting device and a storage medium.
Background
SRAM is a specially customized IP, generally without reset functionality. In some application scenarios, it is necessary to reset the SRAM in one clock cycle, and after the reset is completed, the data read from all the addresses in the SRAM is all 0 or all 1 before being written again. For example, in SPI NAND, load Program Data operation, only data is written to a partial address of a data buffer, and an unused address needs to be duplicated to FF. Therefore, a new SRAM reset method is needed.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art to a certain extent.
Therefore, an object of the embodiments of the present application is to provide an SRAM resetting method, circuit, device and storage medium, which can improve the adaptability of the SRAM and the practicability of the SRAM.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the application comprises the following steps: an SRAM resetting method is used for resetting an SRAM through an SRAM peripheral circuit; the SRAM peripheral circuit comprises a plurality of registers; the number of the registers is equal to the number of the addresses of the SRAM; any one address of the SRAM corresponds to any one register, and the reset method comprises the following steps: resetting each register to a first preset value in response to the received reset signal; determining a write circuit to write first data to any one address in the SRAM, and setting the register corresponding to any one address in the SRAM as a second preset value; when the reading circuit reads data from any one address in the SRAM, the reading data of the reading circuit is adjusted according to the first preset value and the second preset value.
In addition, the method for resetting the SRAM according to the above embodiment of the present application may further have the following additional technical features:
further, in the embodiment of the present application, the step of adjusting the readout data of the readout circuit according to the first preset value and the second preset value includes determining that the register corresponding to any one address in the SRAM is the first preset value, and adjusting the readout data of the readout circuit to be reset data; and determining the register corresponding to any one address in the SRAM as a second preset value, and adjusting the read data of the read circuit to be first data.
Further, in the embodiment of the present application, the reset data is 1 in each bit area corresponding to any address in the SRAM or 0 in each bit area corresponding to any address.
Further, in the embodiment of the present application, the first preset value is 0, and the second preset value is 1.
On the other hand, an embodiment of the present application further provides an SRAM reset circuit, configured to perform the SRAM reset method according to any one of the foregoing embodiments, including:
a write circuit, a read circuit, an SRAM, and a plurality of registers; the write circuit is connected with the SRAM; the reading circuit is connected with the SRAM and the plurality of registers; the number of registers is the same as the number of addresses of the SRAM.
On the other hand, the application also provides an SRAM resetting device, which comprises:
at least one processor;
at least one memory for storing at least one program;
when the at least one program is executed by the at least one processor, the at least one processor is caused to implement an SRAM reset method as set forth in any one of the inventive aspects.
Furthermore, the present application provides a storage medium having stored therein processor-executable instructions which, when executed by a processor, are adapted to carry out an SRAM resetting method as defined in any one of the above.
The advantages and benefits of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
The application can firstly set a plurality of registers with the same number as the addresses of the SRAM, and can firstly set the register corresponding to any one address as a first preset value through resetting before data writing, and when determining that a writing circuit writes first data to any one address in the SRAM, the register corresponding to any one address in the SRAM is set as a second preset value; when the reading circuit reads data from any one address in the SRAM, the reading data of the reading circuit is adjusted according to the first preset value and the second preset value. According to the method, before data writing, the register corresponding to any one address can be set to be the first preset value through resetting, so that the SRAM can be prevented from being reset after data reading, the SRAM is not limited to an application scene without resetting, the adaptability of the SRAM can be improved, and the practicability of the SRAM can be improved.
Drawings
FIG. 1 is a schematic diagram showing steps of an SRAM resetting method according to an embodiment of the present application;
FIG. 2 is a schematic diagram showing steps for adjusting the read data of the read circuit according to the first preset value and the second preset value in an embodiment of the present application;
FIG. 3 is a schematic diagram of an SRAM reset circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an SRAM reset device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings, and the principles and processes of the SRAM resetting method, system, device and storage medium in the embodiments of the present application are described below.
Referring to fig. 1, the present application provides an SRAM reset method, which can reset an SRAM through an SRAM peripheral circuit; wherein the SRAM peripheral circuit may include a number of registers; the number of registers may be equal to the number of addresses of the SRAM; any one address in the SRAM corresponds to any one register. Wherein the reset method may comprise the steps of:
s1, resetting each register to a first preset value in response to a received reset signal;
in this step, when receiving the reset signal of the SRAM, the processing module may set a plurality of registers of the SRAM peripheral circuit to a first preset value, the resetting manner may write the binary value into the registers in the prior art, the pre-reset of the SRAM may be completed by resetting the registers, the registers after the pre-reset may adjust the set values of the registers according to the subsequent data writing state, and different register set values may obtain different data reading results.
S2, determining that a write circuit writes first data into any one address in the SRAM, and setting the register corresponding to any one address in the SRAM as a second preset value;
in this step, when the write circuit succeeds in writing the first data to any address in the SRAM, the processor may set a register corresponding to any address in the SRAM to a second preset value; the method comprises the steps that whether the writing of any address in the SRAM is successful or not can be detected through the existing detection method, when the writing is determined to be successful, a register corresponding to any address in the SRAM can be set to be a second preset value, and the second preset value can be different from the first preset value; the first preset value and the second preset value can be any value which can be stored in a register; the first preset value of this step may be 0 or 1 or a value that other registers may store.
S3, when the reading circuit reads data from any one address in the SRAM, adjusting the reading data of the reading circuit according to the first preset value and the second preset value;
in this step, when the readout circuit reads out data from any address in the SRAM, the readout data of the readout circuit may be adjusted according to different preset values in the registers, and if the value of the register corresponding to the address in the SRAM is the first preset value, the readout data of the readout circuit may be adjusted to be reset data, where the reset data may be a data string with 1 bit area or a data string with 0 bit area. Specifically, with the first preset value being 0, the value of each bit area of any address of the reset data is 1, eight bit areas are provided for the A1 address of the SRAM, A1-a8 are respectively provided, any one bit area is 0 or 1, if A1-a8 is 11101011 before reset, the data of the A1 address is 11101011, and when the first preset value is 0, the read data of the read circuit from the address A1 can be adjusted to 11111111.
Further, referring to fig. 2, in some embodiments of the present application, the step of adjusting the read data of the read circuit according to the first preset value and the second preset value may include
S21, determining that the register corresponding to any one address in the SRAM is a first preset value, and adjusting the read data of the read circuit to be reset data;
s22, determining that the register corresponding to any one address in the SRAM is a second preset value, and adjusting the read data of the read circuit to be first data.
In this embodiment, when a register corresponding to any one address in the SRAM is a first preset value, the readout data of the readout circuit may be adjusted to be reset data; when the register corresponding to any one address in the SRAM is a second preset value, the read data of the read circuit may be adjusted to the first data. Specifically, the first preset value and the second preset value are different values, the first preset value may be set to 0, the second preset value may be set to 1, that is, the values of all registers after the reset is completed are set to 0, when a certain address of the SRAM is successfully written into a data, the register corresponding to the certain address may be set to 1, after the writing is completed, the register with 1 and 0 may be obtained, when the reading circuit is to read the data of the certain address of the SRAM, if the register corresponding to the address is set to 1, the data written by the address may be directly read, and if the register corresponding to the address is set to 0, the reading circuit directly outputs the reset data, such as 00000000 or 11111111.
Further, in some embodiments of the present application, the reset data is 1 for each bit region corresponding to any address in the SRAM or 0 for each bit region corresponding to any address. In this embodiment, the reset data may be 1 in each bit area corresponding to any address in the SRAM, or 0 in each bit area corresponding to any address. Specifically, any one address A1 in the SRAM is an address A1-a8 in the 8-bit region, and in this embodiment, A1-a8 may be 1 or A1-a8 may be 0, that is, the data of the address A1 is 11111111 or 00000000.
Further, in some embodiments of the present application, the first preset value may be 0 and the second preset value may be 1. The first preset value may be set to 0 in this embodiment. 0 may represent SRAM data write failure and 1 may represent SRAM data write success.
The resetting method of the present application will be described with reference to the specific embodiment
In this embodiment, the width of the SRAM, that is, the bit area is 8, the first data is 11010110, the number of registers is 4, the addresses of the SRAM are a01-a04, and the first preset value is 0; resetting the data to 0000000;
firstly, setting 4 registers as a01-a04 in an SRAM peripheral circuit, and setting all 4 registers to 0 after a reset signal is received by a processor;
after receiving the reset signal, the write circuit writes data to address a01 in the SRAM; when a write circuit fails to write 11010110 to an address a01 in the SRAM or does not write any data, setting a register a01 corresponding to the address a01 to 0; according to 0 set by the a01 register, when the readout circuit reads out data from the address a01 in the SRAM, the readout data of the readout circuit is adjusted to 00000000.
When the write circuit successfully writes 11010110 to the address A01 in the SRAM, setting a register a01 corresponding to the address A01 to be 1; according to 1 set by the a01 register, when the readout circuit reads out data from a01 in the SRAM, the readout data of the readout circuit is adjusted to 11010110, that is, after the data written into the SRAM succeeds, the data of the original SRAM at a01 will be refreshed to 11010110, and the readout circuit can directly read 11010110 as the output of the final readout circuit.
In addition, referring to fig. 3, corresponding to the method of fig. 1, an SRAM reset circuit is further provided in an embodiment of the present application, where the SRAM reset method according to any one of the above embodiments may be performed, including:
a write circuit 1, a read circuit 4, an SRAM2, and a plurality of registers 3; wherein the write circuit 1 can be connected with the SRAM 2; the reading circuit 4 is connected with the SRAM2 and a plurality of registers 3; the number of registers 3 is the same as the number of addresses in SRAM 2.
The content of the embodiment of the SRAM reset method is applicable to the embodiment of the SRAM reset circuit, and the functions of the embodiment of the SRAM reset circuit are the same as those of the embodiment of the SRAM reset method, and the achieved beneficial effects are the same as those of the embodiment of the SRAM reset method.
In addition, the embodiment of the application also provides an SRAM reset device, which can comprise an SRAM reset circuit described in the above embodiment.
The content of the SRAM reset circuit embodiment is applicable to the memory chip embodiment, and the functions of the memory chip embodiment are the same as those of the SRAM reset circuit embodiment, and the achieved beneficial effects are the same as those of the SRAM reset circuit embodiment.
Corresponding to the method of fig. 1, the embodiment of the present application further provides an SRAM reset apparatus, with reference to fig. 4, which includes:
at least one processor;
at least one memory for storing at least one program;
when the at least one program is executed by the at least one processor, the at least one processor is caused to implement the SRAM reset method.
The content in the method embodiment is applicable to the embodiment of the device, and the functions specifically realized by the embodiment of the device are the same as those of the method embodiment, and the obtained beneficial effects are the same as those of the method embodiment.
Corresponding to the method of fig. 1, an embodiment of the present application also provides a storage medium having stored therein processor-executable instructions which, when executed by a processor, are adapted to carry out the SRAM reset method.
The content of the above-mentioned SRAM resetting method embodiment is applicable to the present storage medium embodiment, and the functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned SRAM resetting method embodiment, and the beneficial effects achieved by the above-mentioned SRAM resetting method embodiment are the same as those achieved by the above-mentioned SRAM resetting method embodiment.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present application are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the application is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the functions and/or features may be integrated in a single physical device and/or software module or may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the application as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the application, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, including several programs for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable programs for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with a program execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the programs from the program execution system, apparatus, or device and execute the programs. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the program execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the embodiments described above, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (6)
1. An SRAM resetting method is characterized by being used for resetting an SRAM through an SRAM peripheral circuit; the SRAM peripheral circuit comprises a plurality of registers; the number of the registers is equal to the number of the addresses of the SRAM; any one address of the SRAM corresponds to any one register, and the reset method comprises the following steps:
resetting each register to a first preset value in response to the received reset signal;
determining a write circuit to write first data to any one address in the SRAM, and setting the register corresponding to any one address in the SRAM as a second preset value;
when the reading circuit reads data from any one address in the SRAM, the reading data of the reading circuit is adjusted according to the first preset value and the second preset value; wherein the step of adjusting the read data of the read circuit according to the first preset value and the second preset value comprises the steps of:
determining that the register corresponding to any one address in the SRAM is a first preset value, and adjusting the read data of the read circuit to be reset data; wherein the reset data is that each bit area corresponding to any address in the SRAM is 1 or each bit area corresponding to any address is 0;
and determining the register corresponding to any one address in the SRAM as a second preset value, and adjusting the read data of the read circuit to be first data.
2. The method of claim 1, wherein the first predetermined value is 0 and the second predetermined value is 1.
3. An SRAM reset circuit for performing the SRAM reset method of any one of claims 1-2, comprising:
a write circuit, a read circuit, an SRAM, and a plurality of registers; the write circuit is connected with the SRAM; the reading circuit is connected with the SRAM and the plurality of registers; the number of registers is the same as the number of addresses of the SRAM.
4. A memory chip comprising the SRAM reset circuit of claim 3.
5. An SRAM reset apparatus, comprising:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement the SRAM reset method of any one of claims 1-2.
6. A storage medium having stored therein processor-executable instructions which, when executed by a processor, are for performing the SRAM reset method of any one of claims 1-2.
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| JP2018160029A (en) * | 2017-03-22 | 2018-10-11 | 株式会社東芝 | Semiconductor integrated circuit |
| FR3128570B1 (en) * | 2021-10-25 | 2023-10-27 | Commissariat Energie Atomique | SRAM WITH RECONFIGURABLE INITIALIZATION |
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