CN112420115B - Fault detection method for dynamic random access memory - Google Patents
Fault detection method for dynamic random access memory Download PDFInfo
- Publication number
- CN112420115B CN112420115B CN202011224484.XA CN202011224484A CN112420115B CN 112420115 B CN112420115 B CN 112420115B CN 202011224484 A CN202011224484 A CN 202011224484A CN 112420115 B CN112420115 B CN 112420115B
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- sub
- random access
- dynamic random
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 104
- 230000015654 memory Effects 0.000 claims abstract description 103
- 238000003860 storage Methods 0.000 claims abstract description 93
- 238000000034 method Methods 0.000 claims abstract description 36
- 238000012545 processing Methods 0.000 claims description 29
- 238000004590 computer program Methods 0.000 claims description 24
- 238000006243 chemical reaction Methods 0.000 claims description 13
- 230000008878 coupling Effects 0.000 claims description 13
- 238000010168 coupling process Methods 0.000 claims description 13
- 238000005859 coupling reaction Methods 0.000 claims description 13
- 125000004122 cyclic group Chemical group 0.000 claims description 5
- 230000006870 function Effects 0.000 description 7
- 230000007704 transition Effects 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 101100241173 Caenorhabditis elegans dat-1 gene Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application is applicable to the technical field of memories, and provides a fault detection method of a dynamic random access memory, which comprises the following steps: dividing the memory space of a Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules; reading first data from the storage block; and if the first data is inconsistent with the original detection data, judging that the DRAM fails. According to the method, judgment is not needed to be carried out byte by byte, detection time is saved, possible faults can be effectively caught, and detection accuracy is improved.
Description
Technical Field
The application belongs to the technical field of memories, and particularly relates to a fault detection method of a dynamic random access memory.
Background
With the improvement of the design capability and the progress of the manufacturing process of the dynamic random access memory, the speed and the capacity of the dynamic random access memory are rapidly increased, and the more fault types the dynamic random access memory may have originally. The existing fault detection method of the dynamic random access memory mainly comprises the following steps: judging whether the dynamic random access memory fails or not by the bytes in the memory block. However, such a judgment method requires byte-by-byte judgment, the detection time is long, and the detection result is not accurate enough.
Disclosure of Invention
The embodiment of the application provides a fault detection method of a dynamic random access memory, which can solve the problems that the existing fault detection method of the dynamic random access memory has long detection time and inaccurate detection result.
In a first aspect, an embodiment of the present application provides a method for detecting a failure of a dynamic random access memory, including:
Dividing the memory space of a Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules;
Reading first data from the storage block;
And if the first data is inconsistent with the original detection data, judging that the DRAM fails.
Further, the raw detection data at least includes: a first set of data and a second set of data; wherein the second set of data is determined from the first set of data by bit-wise inversion.
Further, the preset writing rule includes: the data written in n storage blocks are determined by carrying out cyclic shift processing with carry on the data written in the n-1 storage blocks; wherein n is a positive integer greater than or equal to 2.
Further, after the determining that the DRAM fails if the first data is inconsistent with the original detected data, the method further includes:
And detecting the DRAM according to a preset detection rule to obtain a fault type.
Further, the detecting the DRAM according to a preset detection rule to obtain a fault type includes:
Dividing the storage blocks into a second preset number of first sub-storage blocks on average;
Replacing and storing second data stored in the first sub-storage block with third data;
And if the third data is stored, judging that a fixed fault occurs.
Further, the detecting the DRAM according to a preset detection rule to obtain a fault type includes:
Dividing the storage block into a third preset number of second sub-storage blocks; the third preset number is greater than 2;
According to a preset movement strategy, moving the fourth data stored in the second sub-storage block to other second sub-storage blocks;
Comparing the logic value before the second sub memory block moves the fourth data with the logic value after the fourth data is moved;
And if the logic value before the fourth data is moved is consistent with the logic value after the fourth data is moved, judging that a conversion fault occurs.
Further, after the moving the fourth data stored in the second sub-storage block to the other second sub-storage block, the method further includes:
If the movement fails, the addressing failure is judged.
Further, the moving the fourth data stored in the second sub-storage block to other second sub-storage blocks according to a preset movement policy includes:
And if the fourth data in the second sub-storage block is not moved and the logic value of the second sub-storage block is changed, judging that the coupling fault occurs.
Further, after the determining that the DRAM fails if the first data is inconsistent with the original detected data, the method further includes:
Stopping detecting whether the first data is consistent with the original detection data.
In a second aspect, an embodiment of the present application provides a fault detection device for a dynamic random access memory, including:
The first processing unit is used for dividing the memory space of the Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules;
a reading unit for reading out the first data from the memory block;
and the second processing unit is used for judging that the DRAM fails if the first data is inconsistent with the original detection data.
Further, the raw detection data at least includes: a first set of data and a second set of data; wherein the second set of data is determined from the first set of data by bit-wise inversion.
Further, the preset writing rule includes: the data written in n storage blocks are determined by carrying out cyclic shift processing with carry on the data written in the n-1 storage blocks; wherein n is a positive integer greater than or equal to 2.
Further, the fault detection device of the dynamic random access memory further includes:
and the third processing unit is used for detecting the DRAM according to a preset detection rule to obtain a fault type.
Further, the third processing unit is specifically configured to:
Dividing the storage blocks into a second preset number of first sub-storage blocks on average;
Replacing and storing second data stored in the first sub-storage block with third data;
And if the third data is stored, judging that a fixed fault occurs.
Further, the third processing unit is specifically configured to:
Dividing the storage block into a third preset number of second sub-storage blocks; the third preset number is greater than 2;
According to a preset movement strategy, moving the fourth data stored in the second sub-storage block to other second sub-storage blocks;
Comparing the logic value before the second sub memory block moves the fourth data with the logic value after the fourth data is moved;
And if the logic value before the fourth data is moved is consistent with the logic value after the fourth data is moved, judging that a conversion fault occurs.
Further, the third processing unit is specifically further configured to:
If the movement fails, the addressing failure is judged.
Further, the third processing unit is specifically configured to:
And if the fourth data in the second sub-storage block is not moved and the logic value of the second sub-storage block is changed, judging that the coupling fault occurs.
Further, the fault detection device of the dynamic random access memory further includes:
And the fourth processing unit is used for stopping detecting whether the first data are consistent with the original detection data or not.
In a third aspect, an embodiment of the present application provides a fault detection device for a dynamic random access memory, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the fault detection method for a dynamic random access memory according to the first aspect when the processor executes the computer program.
In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, where a computer program is stored, where the computer program is executed by a processor to implement the method for detecting a failure of a dynamic random access memory according to the first aspect.
Compared with the prior art, the embodiment of the application has the beneficial effects that: dividing the memory space of a Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules; reading first data from the storage block; and if the first data is inconsistent with the original detection data, judging that the DRAM fails. According to the method, judgment is not needed to be carried out byte by byte, detection time is saved, possible faults can be effectively caught, and detection accuracy is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for detecting faults of a dynamic random access memory according to a first embodiment of the present application;
fig. 2 is a schematic flowchart of refinement of S104 in a fault detection method of a dynamic random access memory according to a first embodiment of the present application;
fig. 3 is a schematic flowchart of refinement of S104 in a fault detection method of a dynamic random access memory according to a first embodiment of the present application;
FIG. 4 is a schematic diagram of a fault detection device of a DRAM according to a second embodiment of the present application;
fig. 5 is a schematic diagram of a fault detection device for a dynamic random access memory according to a third embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As used in the present description and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
Furthermore, the terms "first," "second," "third," and the like in the description of the present specification and in the appended claims, are used for distinguishing between descriptions and not necessarily for indicating or implying a relative importance.
Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.
A dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory, and the main principle of operation is to use the amount of stored charge in a capacitor to represent whether a binary bit (bit) is a1 or a 0.DRAM is typically arranged in a two-dimensional matrix with one capacitor and one transistor as one cell. The basic operation mechanism is divided into reading (Read) and writing (Write), wherein the Bit (BL) is firstly charged to half of the operation voltage when the Read is performed, then the transistor is turned on to enable the BL and the capacitor to generate a charge sharing phenomenon, if the value stored in the BL is 1, the voltage of the BL is raised to be higher than half of the operation voltage by the charge sharing, otherwise, if the value stored in the BL is 0, the voltage of the BL is pulled down to be lower than half of the operation voltage, and after the voltage of the BL is obtained, the internal values are judged to be 0 and 1 through an amplifier.
The memory circuit comprises a plurality of memory cell arrays with regular structures, a large number of analog devices are arranged in the memory circuit, and the components in the memory circuit cannot be directly read. When the DRAM fails, an indirect test method is needed to test, and the existing fault detection method of the dynamic random access memory mainly compares adjacent bytes in the sub memory blocks to judge whether errors occur or not, so as to judge whether the DRAM fails or not. However, this method requires a long detection time, and may cause a missing detection. Therefore, the present embodiment proposes a method for detecting a failure of a dynamic random access memory.
Referring to fig. 1, fig. 1 is a schematic flow chart of a fault detection method of a dynamic random access memory according to a first embodiment of the present application. The main execution body of a fault detection method for a dynamic random access memory in this embodiment is a device having a fault detection function for a dynamic random access memory, for example, a server or the like. The fault detection method of the dynamic random access memory as shown in fig. 1 may include:
S101: dividing the memory space of the DRAM to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules.
In this embodiment, the device stores original detection data in advance, where the original detection data is used to detect whether the DRAM of the dynamic random access memory has failed, and the device needs to write the original detection data into the DRAM to be detected. The device divides the memory space of the DRAM to be detected into a first preset number of memory blocks, and the length of each memory block is not limited, for example, the device may divide the memory space of the DRAM to be detected into 4 memory blocks, and the length of each memory block is 32 bytes.
Further, in order to improve the accuracy of the detection, the original test data may be set to be more complex, and the original test data may include at least two sets of data: a first set of data and a second set of data; wherein the second set of data is determined from the first set of data by bit-wise inversion. For example, the first set of Data 1=0x00000001, the second set of Data 2=0xfffffffffe, and Data2 is Data1 inverted by bits.
And storing a preset writing rule in the device, and writing the original detection data into the divided storage blocks by the device according to the preset writing rule. The preset writing rule is set to further improve the complexity of writing data, so that the detection accuracy is improved. In the present embodiment, the preset writing rule is not particularly limited.
The preset writing rule may include: the data written in n storage blocks are determined by carrying out cyclic shift processing with carry on the data written in the n-1 storage blocks; wherein n is a positive integer greater than or equal to 2. For example, the device may divide the memory space of the DRAM to be tested into 4 memory blocks, each of which is 32 bytes in length. The first group of Data Dat1=0x00000001, the second group of Data Dat2=0xfffffffffe, write Data1 to byte0-7, byte16-23, write Data2 to byte8-15, byte24-31, then the Data written into the first memory block is: 0x00000001 0xfffffffe 0x00000001 0xfffffffe 0x00000001 0xfffffffe 0x00000001 0xfffffffe. The device carries out carry circulation left shift processing on the data in the first storage block, and the obtained data written into the second storage block is: 0x00000002 0xfffffffd 0 0x00000002 0xfffffffd 0x00000002 0xfffffffd 0 0x00000002 0xfffffffd; and so on, sequentially writing n memory blocks.
S102: and reading the first data from the storage block.
The device reads the first data from the memory blocks, and when reading, the device can start reading from the first memory block until the last memory block is finished, and each memory block is sequentially read according to the writing sequence to obtain the first data.
S103: and if the first data is inconsistent with the original detection data, judging that the DRAM fails.
After the device acquires the first data, the device needs to be compared with the original detection data, whether the DRAM has a problem during writing and reading is detected, and whether the DRAM has a fault is judged. By performing multiple read/write operations on the chip, the amount of charge in the chip is reduced, which is indicative of data loss, which is detected when the data is read again. The original detection data are stored in a register corresponding to the storage block, the device compares whether the first data are consistent with the original detection data, and if the first data are inconsistent with the original detection data, the device judges that the DRAM fails.
Further, after judging that the DRAM fails, the detection of whether the first data is consistent with the original detection data or not can be stopped, comparison is not continued, and system resources are saved.
Since each memory cell may have a different state, different fault types may occur, and for these fault types, there are fault types where some main flows occur, such as a fixed fault (SAF-at faults, SAF), and the value of one memory cell is fixed at 0 or fixed at 1, and not changed. A transition failure (Transition faults, TF) one storage unit in the memory array cannot make a 0- >1 or 1- >0 transition. A coupling failure (Coupling faults, CF), a short circuit and coupling between memory cells, results in a change to one memory cell necessarily causing a change in the state of the other memory cell. Addressing the fault (Adress decoder faults, AF) does not allow the corresponding address to be found correctly. In this embodiment, detection methods are also provided for these relatively common types.
Specifically, S104 is further included after S103: and detecting the DRAM according to a preset detection rule to obtain a fault type. In the implementation, the fault problem of the DRAM unit is mapped into a logic fault model, so that storage faults such as AF, SAF, TF, CF and the like can be detected, and other faults can be detected.
In one embodiment, the device determines whether a fixing failure occurs, S104 may include S1041 to S1043, as shown in fig. 2, and S1041 to S1043 are specifically as follows:
S1041: and dividing the storage block into a second preset number of first sub-storage blocks on average.
The device divides the memory blocks equally into a second preset number of first sub-memory blocks, e.g. each memory block having a length of 32 bytes, and divides each memory block by 8 equal parts, each sub-memory block being 4 bytes.
S1042: and replacing and storing the second data stored in the first sub-storage block with the third data.
In this embodiment, the second data is stored in the first sub-memory block, and in order to detect whether there is a fixing failure, the fixing failure is that the value of one memory cell is fixed at 0 or fixed at 1, and is not changed. Therefore, data movement is required during detection, and the purpose of the data movement is to detect the validity of different data stored in the same storage address, and to test whether the storage address can not store certain specific data or store the specific data for a long time. Therefore, to determine whether a fixed failure occurs, it is necessary to determine whether a certain memory cell is capable of storing only data 1, but not data 0. The apparatus replaces the second data stored in the first sub-memory block with the third data to determine whether the first sub-memory block can store the third data.
In this case, when the third data is replaced with the second data stored in the first sub-memory block, a certain movement rule may be followed, for example, the data in each first sub-memory block is sequentially moved backward by m bytes, etc. When there are n memory blocks, each memory block is equally divided into 8 first sub-memory blocks, and then moved 8*m times in total.
S1043: and if the third data is stored, judging that a fixed fault occurs.
When the device stores the third data, if a storage error occurs, the first sub-storage block cannot normally store the third data, which means that the current first sub-storage block can only store the second data and cannot store the third data, and the first sub-storage block does not have effective storage capacity and determines that a fixed fault occurs.
In one embodiment, the device determines whether a transition fault occurs, S104 may include S1044 to S1047, as shown in fig. 3, and S1044 to S1047 are specifically as follows:
S1044: dividing the storage block into a third preset number of second sub-storage blocks; the third preset number is greater than 2.
The device divides the memory block into a third preset number of second sub memory blocks, wherein the third preset number is greater than 2. For example, each memory block is 32 bytes in length, and then each memory block is divided into 4 second sub-memory blocks.
S1045: and moving the fourth data stored in the second sub-storage block to other second sub-storage blocks according to a preset movement strategy.
In this embodiment, a transition failure is detected, wherein a single storage unit in the memory array cannot perform a transition of 0- >1 or 1- > 0. When the data is moved, the storage unit performs 0- (1) or 1- (0) conversion, so in this embodiment, the data is moved according to a predetermined movement policy, and it is detected whether the storage unit performs 0- (1) or 1- (0) conversion.
When moving, the device moves the fourth data stored in the second sub-memory block to other second sub-memory blocks, and judges whether the second sub-memory block will perform 0- (1) or 1- (0) conversion. Specifically, in this embodiment, the preset movement policy is not specifically limited, and only the fourth data stored in the second sub-storage block may be moved to other second sub-storage blocks. For example, a memory block is divided into 4 second sub-memory blocks: the device may move fourth data in the second sub memory block a to the second sub memory block D and fourth data in the second sub memory block B to the second sub memory block C. Further, the movement may be continued, and the device may move the fourth data in the moved second sub-memory block a to the second sub-memory block D and the fourth data in the moved second sub-memory block B to the second sub-memory block C.
After the fourth data stored in the second sub-memory block is moved to the other second sub-memory block, if the movement fails, which means that the corresponding address cannot be found correctly according to the address of the existing memory cell, it is determined that the addressing failure occurs.
During the movement, it is possible to detect whether there is a coupling failure by means of a constant movement. If a memory cell is shorted and coupled to another memory cell, the resulting change to one memory cell necessarily causes a state change to the other memory cell. If the fourth data in the second sub memory block is not moved and the logic value of the second sub memory block is changed, the data change is caused by the influence of the memory cell in operation on the static memory cell, and the coupling fault is judged. Wherein the coupling failure may be either cell-to-cell or intra-cell bit-to-bit.
S1046: and comparing the logic value before the second sub memory block moves the fourth data with the logic value after the fourth data is moved.
The device compares the logical value before the second sub-memory block is moved by the fourth data with the logical value after the fourth data is moved. And judging whether the logic value before moving the fourth data is consistent with the logic value after moving the fourth data, thereby judging whether a conversion fault occurs. If the data are consistent, the storage unit cannot convert the logic value when the data are moved, and judging that a conversion fault occurs; if the data are inconsistent, the storage unit can normally perform conversion of the logic value when the data are moved, and the conversion failure is judged not to occur.
S1047: and if the logic value before the fourth data is moved is consistent with the logic value after the fourth data is moved, judging that a conversion fault occurs.
The device judges whether the logic value before moving the fourth data is consistent with the logic value after moving the fourth data, and judges that a conversion fault occurs if the logic value before moving the fourth data is consistent with the logic value after moving the fourth data.
Compared with the prior art, the embodiment of the application has the beneficial effects that: dividing the memory space of a Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules; reading first data from the storage block; and if the first data is inconsistent with the original detection data, judging that the DRAM fails. According to the method, judgment is not needed to be carried out byte by byte, detection time is saved, possible faults can be effectively caught, and detection accuracy is improved.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present application.
Referring to fig. 4, fig. 4 is a schematic diagram of a fault detection apparatus for a dram according to a second embodiment of the present application. The units included are used to perform the steps in the corresponding embodiments of fig. 1-3. Refer specifically to the related descriptions in the respective embodiments of fig. 1 to 3. For convenience of explanation, only the portions related to the present embodiment are shown. Referring to fig. 4, the fault detection device 4 of the dynamic random access memory includes:
The first processing unit 410 is configured to divide a memory space of the DRAM to be detected into a first preset number of memory blocks, and write original detection data into the memory blocks according to a preset writing rule;
a reading unit 420, configured to read the first data from the storage block;
The second processing unit 430 is configured to determine that the DRAM fails if the first data is inconsistent with the original detected data.
Further, the raw detection data at least includes: a first set of data and a second set of data; wherein the second set of data is determined from the first set of data by bit-wise inversion.
Further, the preset writing rule includes: the data written in n storage blocks are determined by carrying out cyclic shift processing with carry on the data written in the n-1 storage blocks; wherein n is a positive integer greater than or equal to 2.
Further, the fault detection device 4 of the dynamic random access memory further includes:
and the third processing unit is used for detecting the DRAM according to a preset detection rule to obtain a fault type.
Further, the third processing unit is specifically configured to:
Dividing the storage blocks into a second preset number of first sub-storage blocks on average;
Replacing and storing second data stored in the first sub-storage block with third data;
And if the third data is stored, judging that a fixed fault occurs.
Further, the third processing unit is specifically configured to:
Dividing the storage block into a third preset number of second sub-storage blocks; the third preset number is greater than 2;
According to a preset movement strategy, moving the fourth data stored in the second sub-storage block to other second sub-storage blocks;
Comparing the logic value before the second sub memory block moves the fourth data with the logic value after the fourth data is moved;
And if the logic value before the fourth data is moved is consistent with the logic value after the fourth data is moved, judging that a conversion fault occurs.
Further, the third processing unit is specifically further configured to:
If the movement fails, the addressing failure is judged.
Further, the third processing unit is specifically configured to:
And if the fourth data in the second sub-storage block is not moved and the logic value of the second sub-storage block is changed, judging that the coupling fault occurs.
Further, the fault detection device 4 of the dynamic random access memory further includes:
And the fourth processing unit is used for stopping detecting whether the first data are consistent with the original detection data or not.
Fig. 5 is a schematic diagram of a fault detection device for a dynamic random access memory according to a third embodiment of the present application. As shown in fig. 5, the failure detection apparatus 5 of the dynamic random access memory of this embodiment includes: a processor 50, a memory 51 and a computer program 52 stored in the memory 51 and executable on the processor 50, such as a fault detection program for a dynamic random access memory. The processor 50, when executing the computer program 52, implements the steps of the embodiments of the fault detection method for each of the dynamic random access memories described above, such as steps 101 to 102 shown in fig. 1. Or the processor 50, when executing the computer program 52, performs the functions of the modules/units of the apparatus embodiments described above, such as the functions of the modules 410-430 shown in fig. 4.
By way of example, the computer program 52 may be partitioned into one or more modules/units that are stored in the memory 51 and executed by the processor 50 to complete the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing a specific function for describing the execution of the computer program 52 in the fault detection device 5 of the dynamic random access memory. For example, the computer program 52 may be divided into a first processing unit, a reading unit, and a second processing unit, each unit specifically functioning as follows:
The first processing unit is used for dividing the memory space of the Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules;
a reading unit for reading out the first data from the memory block;
and the second processing unit is used for judging that the DRAM fails if the first data is inconsistent with the original detection data.
The fault detection device of the dynamic random access memory may include, but is not limited to, a processor 50, a memory 51. It will be appreciated by those skilled in the art that fig. 5 is merely an example of a dynamic random access memory failure detection device 5, and is not meant to be limiting as to the dynamic random access memory failure detection device 5, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the dynamic random access memory failure detection device may further include an input output device, a network access device, a bus, etc.
The Processor 50 may be a central processing unit (Central Processing Unit, CPU), other general purpose Processor, digital signal Processor (DIGITAL SIGNAL Processor, DSP), application SPECIFIC INTEGRATED Circuit (ASIC), off-the-shelf Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 51 may be an internal storage unit of the fault detection device 5 of the dynamic random access memory, for example a hard disk or a memory of the fault detection device 5 of the dynamic random access memory. The memory 51 may also be an external storage device of the fault detection device 5 of the dynamic random access memory, for example, a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the fault detection device 5 of the dynamic random access memory. Further, the fault detection device 5 of the dynamic random access memory may further include both an internal storage unit and an external storage device of the fault detection device 5 of the dynamic random access memory. The memory 51 is used for storing the computer program and other programs and data required for the fault detection device of the dynamic random access memory. The memory 51 may also be used to temporarily store data that has been output or is to be output.
It should be noted that, because the content of information interaction and execution process between the above devices/units is based on the same concept as the method embodiment of the present application, specific functions and technical effects thereof may be referred to in the method embodiment section, and will not be described herein.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
The embodiment of the application also provides a network device, which comprises: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, which when executed by the processor performs the steps of any of the various method embodiments described above.
Embodiments of the present application also provide a computer readable storage medium storing a computer program which, when executed by a processor, implements steps for implementing the various method embodiments described above.
Embodiments of the present application provide a computer program product which, when run on a mobile terminal, causes the mobile terminal to perform steps that enable the implementation of the method embodiments described above.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiments, and may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to a photographing device/terminal apparatus, recording medium, computer Memory, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), electrical carrier signals, telecommunications signals, and software distribution media. Such as a U-disk, removable hard disk, magnetic or optical disk, etc. In some jurisdictions, computer readable media may not be electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/network device and method may be implemented in other manners. For example, the apparatus/network device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (7)
1. A method for detecting a fault in a dynamic random access memory, comprising:
Dividing the memory space of a Dynamic Random Access Memory (DRAM) to be detected into a first preset number of memory blocks, and writing original detection data into the memory blocks according to preset writing rules;
Reading first data from the storage block;
if the first data is inconsistent with the original detection data, judging that the DRAM fails;
the raw detection data at least comprises: a first set of data and a second set of data; wherein the second set of data is determined from the first set of data by bit-wise negation;
After the first data is inconsistent with the original detection data, determining that the DRAM fails, the method further includes:
Detecting the DRAM according to a preset detection rule to obtain a fault type;
The step of detecting the DRAM according to a preset detection rule to obtain a fault type comprises the following steps:
Dividing the storage blocks into a second preset number of first sub-storage blocks on average;
replacing and storing the second data stored in the first sub-storage block with third data according to a movement rule;
And if the third data is stored, judging that a fixed fault occurs.
2. The method for detecting a fault in a dynamic random access memory as claimed in claim 1, wherein the preset writing rule comprises: the data written in n storage blocks are determined by carrying out cyclic shift processing with carry on the data written in the n-1 storage blocks; wherein n is a positive integer greater than or equal to 2.
3. The method for detecting a fault in a dynamic random access memory according to claim 1, wherein the detecting the DRAM according to a predetermined detection rule to obtain a fault type comprises:
Dividing the storage block into a third preset number of second sub-storage blocks; the third preset number is greater than 2;
According to a preset movement strategy, moving the fourth data stored in the second sub-storage block to other second sub-storage blocks;
Comparing the logic value before the second sub memory block moves the fourth data with the logic value after the fourth data is moved;
And if the logic value before the fourth data is moved is consistent with the logic value after the fourth data is moved, judging that a conversion fault occurs.
4. The method for detecting a failure of a dynamic random access memory according to claim 3, further comprising, after said moving the fourth data stored in the second sub-memory block to the other second sub-memory block:
If the movement fails, the addressing failure is judged.
5. The method for detecting a fault in a dynamic random access memory as claimed in claim 3, wherein said moving the fourth data stored in the second sub-memory block to other second sub-memory blocks according to a preset movement policy comprises:
and if the fourth data in the second sub-storage block is not moved and the logic value of the second sub-storage block is changed, judging that the coupling fault occurs.
6. The method for detecting a failure of a dynamic random access memory according to claim 1, further comprising, after said determining that said DRAM failed if said first data does not match said original detected data:
Stopping detecting whether the first data is consistent with the original detection data.
7. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011224484.XA CN112420115B (en) | 2020-11-05 | 2020-11-05 | Fault detection method for dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011224484.XA CN112420115B (en) | 2020-11-05 | 2020-11-05 | Fault detection method for dynamic random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112420115A CN112420115A (en) | 2021-02-26 |
| CN112420115B true CN112420115B (en) | 2024-05-10 |
Family
ID=74826947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011224484.XA Active CN112420115B (en) | 2020-11-05 | 2020-11-05 | Fault detection method for dynamic random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112420115B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253479B (en) * | 2021-12-20 | 2023-06-20 | 国汽(北京)智能网联汽车研究院有限公司 | CAN bus intrusion detection method and system |
| CN114446374A (en) * | 2021-12-27 | 2022-05-06 | 深圳市晶存科技有限公司 | Test method of dynamic random access memory and storage medium |
| CN114464242B (en) * | 2022-01-13 | 2024-06-14 | 深圳市金泰克半导体有限公司 | DDR test method, device, controller and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853198A (en) * | 2010-05-11 | 2010-10-06 | 福建星网锐捷网络有限公司 | Detection method, equipment and system of address bus |
| CN103310848A (en) * | 2012-03-08 | 2013-09-18 | 鼎桥通信技术有限公司 | Method and apparatus using memory |
| CN108134717A (en) * | 2017-10-26 | 2018-06-08 | 同济大学 | Network-on-chip stuck-at fault on-line testing method based on bounded model checking |
| CN108335721A (en) * | 2018-03-14 | 2018-07-27 | 烽火通信科技股份有限公司 | A kind of method and system of real-time detection of random access memory address line failure |
| CN108694985A (en) * | 2017-04-06 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | Test method and test circuit for detecting storage failure |
| CN109243519A (en) * | 2017-07-11 | 2019-01-18 | 恩智浦有限公司 | Fault of Integrated Circuits detection |
| CN111627490A (en) * | 2020-05-22 | 2020-09-04 | 浙江大华技术股份有限公司 | Synchronous dynamic random access memory testing method and device |
| CN111863111A (en) * | 2020-07-10 | 2020-10-30 | 深圳佰维存储科技股份有限公司 | DRAM testing method and device, computer readable storage medium and electronic equipment |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2465370A (en) * | 2008-11-13 | 2010-05-19 | Ingenia Holdings | Magnetic data storage comprising a synthetic anti-ferromagnetic stack arranged to maintain solitons |
-
2020
- 2020-11-05 CN CN202011224484.XA patent/CN112420115B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853198A (en) * | 2010-05-11 | 2010-10-06 | 福建星网锐捷网络有限公司 | Detection method, equipment and system of address bus |
| CN103310848A (en) * | 2012-03-08 | 2013-09-18 | 鼎桥通信技术有限公司 | Method and apparatus using memory |
| CN108694985A (en) * | 2017-04-06 | 2018-10-23 | 中芯国际集成电路制造(北京)有限公司 | Test method and test circuit for detecting storage failure |
| CN109243519A (en) * | 2017-07-11 | 2019-01-18 | 恩智浦有限公司 | Fault of Integrated Circuits detection |
| CN108134717A (en) * | 2017-10-26 | 2018-06-08 | 同济大学 | Network-on-chip stuck-at fault on-line testing method based on bounded model checking |
| CN108335721A (en) * | 2018-03-14 | 2018-07-27 | 烽火通信科技股份有限公司 | A kind of method and system of real-time detection of random access memory address line failure |
| CN111627490A (en) * | 2020-05-22 | 2020-09-04 | 浙江大华技术股份有限公司 | Synchronous dynamic random access memory testing method and device |
| CN111863111A (en) * | 2020-07-10 | 2020-10-30 | 深圳佰维存储科技股份有限公司 | DRAM testing method and device, computer readable storage medium and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112420115A (en) | 2021-02-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112420115B (en) | Fault detection method for dynamic random access memory | |
| EP2686850B1 (en) | Methods, devices, and systems for data sensing | |
| US11043275B2 (en) | Memory system, read method, program, and memory controller | |
| CN112181714B (en) | Error correction method and device for solid state disk, storage equipment and storage medium | |
| WO2016053985A1 (en) | Short detection and inversion | |
| CN112347007B (en) | Flash memory data protection method and device, electronic equipment and storage medium | |
| US8169829B2 (en) | Memory controller, memory system, recording and reproducing method for memory system, and recording apparatus | |
| US20230376226A1 (en) | Storage block management information synchronous recording method and system, and terminal and storage medium | |
| CN103902419A (en) | Method and device for testing caches | |
| CN115509466B (en) | Data management method and device, electronic equipment and storage medium | |
| EP3404662B1 (en) | A method and system for implementing a non-volatile counter using non-volatile memory | |
| CN112216333B (en) | Chip testing method and device | |
| CN106158031B (en) | Semiconductor memory and data writing method | |
| CN109710445B (en) | Memory correction method and electronic equipment | |
| CN115705914A (en) | Method and device for detecting bad block of flash memory and computer storage medium | |
| CN116665749A (en) | Method and device for testing memory chip | |
| CN111427756A (en) | Method, system, equipment and medium for carrying out mixed pressure test on single hard disk | |
| CN117079703B (en) | Method and device for testing embedded memory of chip and electronic equipment | |
| US10170200B2 (en) | Memory device and method for testing a memory device | |
| CN116312671B (en) | SRAM resetting method, circuit, chip, device and medium | |
| CN116072206B (en) | Method and device for testing flash memory error number, electronic equipment and storage medium | |
| CN115469799B (en) | Data storage method, storage device and computer readable storage device | |
| CN116665745A (en) | Flash memory reading method and device | |
| US11978490B2 (en) | Back pattern counter measure for solid state drives | |
| CN112540866B (en) | Memory device and data access method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |