CN113641626A - SRAM read-write control method and line buffer controller - Google Patents
SRAM read-write control method and line buffer controller Download PDFInfo
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Abstract
The invention is suitable for the technical field of SOC, and provides an SRAM read-write control method and a line buffer controller, wherein the method comprises the following steps: setting an access domain and a read-write strategy in a strategy register; monitoring an SRAM read-write address from a storage access controller through a distributor, and sending a data read-write instruction according to the SRAM read-write address; and adjusting a line replacement strategy through the line buffer register group according to the data read-write instruction, and performing data read-out or/and write-in operation according to the line replacement strategy. The invention reduces the dynamic power consumption generated in the SRAM reading and writing process through a novel line buffer controller.
Description
Technical Field
The invention belongs to the technical field of SOC (system on chip), and particularly relates to an SRAM (static random access memory) read-write control method and a line buffer controller.
Background
In a low power consumption embedded System On Chip (SOC), a large dynamic power consumption is caused by a read-write Access operation of a Static Random-Access Memory (SRAM). Referring to fig. 1, in related researches, a latest scheme for controlling Memory Access power consumption is to use spatial locality and temporal locality of Memory Access, temporarily store line data read out from a Dynamic Random Access Memory (DRAM) Access in a line Buffer Cache (Row Buffer Cache) for specially buffering the line data, and integrate the line Buffer Cache, a line Buffer conflict detector (Row Buffer conflict detector), a line Buffer local predictor (Row Buffer local predictor), a fair allocator (fair allocator), and related circuits such as the line Buffer Cache, the line Buffer conflict detector, the line Buffer local predictor, and the fair allocator into a Memory Access Controller (Memory Controller), when the Memory Access Controller reads data from the Memory, it is first checked whether there is pre-stored line data in the line Buffer Cache, and if there is, the Memory Access Controller directly reads the line data from the line Buffer Controller without reading a Bank array of the Memory itself, thereby improving access speed and reducing dynamic power consumption.
The problem of the above scheme is that the line buffer Cache itself also contains an SRAM memory, so that the line buffer Cache has a larger circuit scale, and the read-write operation of the line buffer Cache itself can also cause an increase in dynamic power consumption; secondly, the line buffer Cache is integrated in the storage access controller, and if the read-write of the storage access controller does not hit the Cache content of the line buffer Cache, the line buffer Cache is updated through extra operation, so that the dynamic power consumption is increased; in the SOC design, an on-chip SRAM is mostly adopted as a memory, and a row buffer Cache integrated in a memory access controller cannot be used for reducing the power consumption of on-chip SRAM reading and writing.
Disclosure of Invention
The embodiment of the invention provides an SRAM read-write control method and a line buffer controller, and aims to solve the problem that dynamic power consumption is too high when the line buffer controller in the prior art reads and writes.
In a first aspect, an embodiment of the present invention provides a method for controlling read and write of an SRAM, including the following steps:
setting an access domain and a read-write strategy in a strategy register;
monitoring an SRAM read-write address from a storage access controller through a distributor, and sending a data read-write instruction according to the SRAM read-write address;
and adjusting a line replacement strategy through a line buffer register group according to the data read-write instruction, and performing data read-out or/and write-in operation according to the line replacement strategy.
Further, the step of setting the access domain and the read-write policy in the policy register includes the following substeps:
the policy register receives the access operation of the CPU and acquires assignment;
and setting the access domain of the policy register to be associated with a storage address in the SRAM according to the assignment, and setting the read-write policy.
Still further, the read-write strategy includes at least one of FIFO, FILO, LRU, NMRU.
Furthermore, the step of monitoring the SRAM read-write address from the storage access controller by the distributor and issuing a data read-write instruction according to the SRAM read-write address includes the following substeps:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the strategy register are in the same address space;
if the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
Furthermore, the line buffer register group is a line structure organized by lines, wherein the structure of each line comprises valid values, Bank line numbers, access times and Bank line data.
Furthermore, the step of adjusting the line replacement policy according to the data read-write instruction by the line buffer register group and performing data read-out or/and write-in operation according to the line replacement policy includes the following steps:
if the read-write strategy corresponding to the data read-write instruction is LRU, the line buffer register group performs data read-write operation according to the line replacement strategy in the LRU mode, wherein the line buffer register group is a concurrent read-write mode, and the line buffer register group performs the LRU algorithm according to the hit condition of the data read-write instruction to perform read-out or/and write-in operation of data in the SRAM;
if the read-write strategy corresponding to the data read-write instruction is an NMRU, the line buffer register group executes data read-write operation according to the line replacement strategy in an NMRU mode, wherein the line buffer register group is in a concurrent read-write mode, and executes an NMRU algorithm according to the hit condition of the data read-write instruction to read or/and write data in an SRAM (static random access memory);
if the read-write strategy corresponding to the data read-write instruction is FIFO, the line buffer register group performs data read-write operation according to the line replacement strategy in an FIFO mode, wherein the line buffer register group is in a loop sequence read-write mode, and the line buffer register group performs FIFO algorithm by using a loop queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM;
and if the read-write strategy corresponding to the data read-write instruction is FILO, the line buffer register group executes data read-write operation according to the line replacement strategy in the FILO mode, wherein the line buffer register group is in a ring sequence read-write mode, and executes a FILO algorithm by using a ring queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM.
In a second aspect, an embodiment of the present invention further provides a line buffer controller, including:
the strategy register is used for setting an access domain and a read-write strategy;
the distributor is used for monitoring the SRAM read-write address from the storage access controller and sending a data read-write instruction according to the SRAM read-write address;
and the line buffer register group is used for adjusting a line replacement strategy according to the data reading and writing instruction and performing data reading or/and writing operation according to the line replacement strategy.
Furthermore, the read-write strategy comprises at least one of FIFO, FILO, LRU and NMRU, and the step of monitoring the SRAM read-write address from the memory access controller and issuing a data read-write instruction according to the SRAM read-write address comprises the following sub-steps:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space:
if the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
In a third aspect, an embodiment of the present invention further provides a computer device, including: the SRAM read-write control method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps in the SRAM read-write control method according to any one of the above embodiments when executing the computer program.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the SRAM read-write control method described in any one of the above embodiments are implemented.
The invention has the advantages that the line buffer controller does not comprise the SRAM and is arranged between the memory access controller and the structure of the SRAM Bank, so that the circuit scale of the memory unit can be reduced, the extra operation caused by memory miss can be reduced, the power consumption of on-chip SRAM cache reading and writing can be reduced, and meanwhile, more refined dynamic power consumption control can be realized through a controllable reading and writing strategy.
Drawings
FIG. 1 is a schematic diagram of a line buffer controller provided in the prior art;
FIG. 2 is a schematic diagram of an SRAM read/write control method according to an embodiment of the present invention;
FIG. 3 is a flow chart of a method for controlling SRAM read/write according to an embodiment of the present invention;
FIG. 4 is a block diagram of a sub-flow of step S102 in the SRAM read/write control method according to an embodiment of the present invention;
FIG. 5 is a block diagram of a row buffer controller according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 2, fig. 2 is a schematic diagram of an SRAM read/write control method according to an embodiment of the present invention, in the embodiment of the present invention, a line buffer controller is not integrated in a memory access controller, but is dispersed in a structure of an SRAM Bank, generally, the SRAM includes a plurality of banks, a Bank is defined as a last structure before a memory grain is stored in a computer, that is, a Bank structure divides the memory grain into block-type memory cells with staggered rows and columns, and correspondingly, the memory cells are divided in different n banks according to different memory addresses in the SRAM, where n is a natural number; the line buffer controllers provided in the embodiments of the present invention also include a plurality of line buffer controllers in one storage system, where one line buffer controller corresponds to k Bank structures, k is a positive integer, the minimum value of k may be 1, the selection of the value of k is selected according to the access frequency of a CPU in an embedded system to an SRAM and the actual data hit rate of the line buffer controller, and all the line buffer controllers correspond to the same storage access controller. In the read-write process of the SRAM, the CPU firstly issues an instruction containing the read-write address of the SRAM to the storage access controller, and then passes through one of the line buffer controllers correspondingly containing the read-write address of the SRAM, and the line buffer controller reads data corresponding to the read-write address of the SRAM from a cache of the line buffer controller or a corresponding Bank and feeds the data back to the storage access controller, so that the CPU obtains the required data.
Referring to fig. 3, fig. 3 is a flow chart of an SRAM read/write control method according to an embodiment of the present invention, which specifically includes the following steps:
s101, setting an access domain and a read-write strategy in a strategy register.
In an embodiment of the present invention, the policy register includes the access field and the read-write policy, where the access field refers to a storage address space of a storage grain in the SRAM Bank corresponding to the line buffer controller, the read-write policy is a rule for the line buffer controller to read and write the SRAM Bank as a whole, and specifically, the policy register is also a storage unit accessible by an address, and the CPU issues an editable instruction to the policy register in an address access manner to assign a value, so as to change the access field of the policy register and the read-write policy, where the read-write policy includes First-in First-out (FIFO), First-in Last-out (FILO), Least recently Used (Least recently-Used, LRU), non-Least recently Used (Not Most-Used, NMRU), and other types of the read-write strategies can be added according to different actual needs. For different selected read-write strategies, the structures of the line buffer register groups in the line buffer controller and the reading modes of the SRAM are different.
Preferably, in the embodiment of the present invention, at least one shadow policy register is further disposed corresponding to the policy register, and at this time, the strategy register is regarded as a main strategy register of the shadow strategy register, when the main strategy register sets the access domain and the read-write strategy through a CPU, the shadow strategy register sets the independent access domain and the read-write strategy through the CPU, the access domain and the read-write policy of the shadow policy register are not necessarily the same as the master policy register, the shadow register is in a sleep state when the master policy register is operating, when the CPU does not work by performing access operation on the main strategy register to modify the access domain or the read-write strategy, the shadow policy register is activated to assume work as the new master policy register. Through the design, the CPU can conveniently access the strategy register, so that the access domain and the read-write strategy can be set as required.
S102, monitoring the SRAM read-write address from the storage access controller through the distributor, and sending a data read-write instruction according to the SRAM read-write address.
Referring to fig. 4, fig. 4 is a sub-flow diagram of step S102 in the SRAM read/write control method according to the embodiment of the present invention, which specifically includes the following sub-steps:
s1021, the distributor monitors the SRAM read-write address from the storage access controller, and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space.
In a storage system, a CPU firstly generates an instruction for acquiring certain data, and then sends the instruction to a storage access controller, and the storage access controller reads and writes data to a specific address in an SRAM according to the instruction. In this embodiment of the present invention, the line buffer controller is disposed between an SRAM and the storage access controller, wherein the allocator is configured to receive the SRAM read-write address for reading a certain data from the storage access controller, the policy register in the line buffer controller sets the access field and the cache policy in advance, and more specifically, after acquiring a specific SRAM read-write address, the allocator compares an address range of the access field in the main policy register with the SRAM read-write address to perform a next operation.
S1022a, if the SRAM read-write address is in the same address space as the access domain of the policy register, the distributor generates the data read-write instruction according to the SRAM read-write address, and sends the data read-write instruction to the line buffer register set.
If the SRAM read-write address and the access domain of the policy register are in the same address space, that is, the SRAM read-write address is just in the address area of the SRAM Bank corresponding to the line buffer controller, the distributor generates the instruction for controlling the line replacement policy of the line buffer register group according to the SRAM read-write address and the read-write policy corresponding to the main policy register, and sends the instruction to the line buffer controller.
S1022b, if the SRAM read/write address and the access domain of the policy register are not in the same address space, the allocator does not perform any processing.
And if the SRAM read-write address and the access domain of the policy register are not in the same address space, namely the SRAM read-write address is not in the address area of the SRAM Bank corresponding to the current line buffer controller, the distributor does not process the SRAM read-write address.
S103, adjusting a line replacement strategy through a line buffer register group according to the data read-write instruction, and performing data read-out or/and write-in operation according to the line replacement strategy.
In this embodiment of the present invention, the line buffer register group is a storage unit formed by a line structure organized by lines, and the line structure includes a valid value, a Bank line number, an access number, and Bank line data, where the valid value refers to validity of a certain line of data in the line buffer register group, the Bank line number is a specific position of the data buffered by the line structure in a Bank line structure, the access number is an accumulated number of times that the line structure is read, and the Bank line data is specific data stored in a Bank corresponding to the Bank line number. The line buffer register group sets the line structure to a concurrent read-write mode or a loop sequence read-write mode through the line replacement policy, and performs data update and write-in on the line structure according to different line replacement policies, specifically, in this embodiment, according to the read-write policy set in the policy register, the manner in which the distributor acquires data from the line buffer register group is divided into the following four manners:
a. and if the read-write strategy corresponding to the data read-write instruction is LRU, the line buffer register group executes data read-write operation according to the line replacement strategy in the LRU mode.
In the LRU mode, the line buffer register group is in a concurrent read-write mode, the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, and when the instruction is read data, whether the corresponding Bank line number in the line structure is matched with the SRAM read-write address is checked in a concurrent mode. In a memory system, the data read and write addresses correspond to data in the cache, referred to as hits.
And if the data hit occurs, the line buffer register group immediately returns the corresponding Bank row data without triggering SRAM Bank read operation, and simultaneously, the value of the access times is added with 1 to record 1 line read operation. That is, if the Bank line number corresponding to a certain line structure in the line buffer register group corresponds to the SRAM read/write address, the Bank line data corresponding to the Bank line number is the data hit by this read/write, at this time, the line buffer register group immediately returns to the memory access controller to hit the Bank line data, and at the same time, the value of the access frequency corresponding to the hit line structure is added by 1, corresponding to 1 read operation of the Bank line data.
If all the banked data cached in the line buffer register group is not hit, that is, the line buffer register group does not cache data corresponding to the SRAM read-write address, then according to the line replacement policy in the LRU mode, the line buffer register group reads corresponding data from the SRAM Bank corresponding to the SRAM read-write address, and at the same time, the distributor checks the valid value of the line structure in a concurrent manner, where:
if the effective value of one line structure is 0, the current line structure is not occupied, the read data is stored in the line structure, correspondingly, the access times of the line structure are increased by 2, and the updating and reading of the Bank line data are performed for 2 times;
and if the effective value of any line structure is not 0, indicating that all the current line structures are occupied, selecting the corresponding line structure for data updating by taking the access times as an LRU calculation object according to an LRU algorithm, updating the data read out at this time into the line structure, correspondingly assigning the access times of the line structure to be 2, and corresponding to the updating and reading of the Bank data for 2 times.
The distributor sends the instruction to the line buffer register group according to the SRAM read-write address, when the instruction is write-in data, the corresponding data in the instruction is directly written into an SRAM Bank corresponding to the SRAM read-write address, meanwhile, if the data corresponding to the SRAM read-write address exists in the line buffer register group, namely when Bank row data in a certain line structure hit, the data written into the SRAM Bank is written into the line structure, and the access times of the line structure are added by 1, so that 1 time of write-in operation of the Bank row data is corresponded.
b. And if the read-write strategy corresponding to the data read-write instruction is an NMRU, the line buffer register group executes data read-write operation according to the line replacement strategy in an NMRU mode.
In the NMRU mode, the line buffer controller is in a concurrent read-write mode, and when the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, and the instruction is read data, the line buffer controller in the NMRU mode is consistent with an operation in the LRU mode in the case of data hit.
If all the banked data cached in the line buffer register group is not hit, that is, the line buffer register group does not cache data corresponding to the SRAM read-write address, then according to the line replacement policy in the NMRU mode, the line buffer register group reads corresponding data from the SRAM Bank corresponding to the SRAM read-write address, and at the same time, the distributor checks the effective value of the line structure in a concurrent manner, where:
if the effective value of one line structure is 0, the current line structure is not occupied, the read data is stored in the line structure, correspondingly, the access times of the line structure are increased by 2, and the updating and reading of the Bank line data are performed for 2 times;
and if the effective value of any one of the line structures is not 0, indicating that all the current line structures are occupied, selecting the corresponding line structure for data updating by taking the access times as an NMRU calculation object according to an NMRU algorithm, updating the data read out at this time into the line structure, correspondingly assigning the access times of the line structure to be 2, and corresponding to the updating and reading of the Bank data for 2 times.
And the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, and when the instruction is write data, the operation of the line buffer register group is consistent with the operation in the LRU mode.
c. And if the read-write strategy corresponding to the data read-write instruction is FIFO, the line buffer register group executes data read-write operation according to the line replacement strategy in an FIFO mode.
In FIFO mode, the line buffer controller is in read-write mode, and the line structure in the line buffer register set is additionally given from 0 to
The number of the row of (a),
m of (1) is positively correlated with the module size of the line buffer register set,
the design of the line number can ensure that the reading and writing mode of the ring sequence is established, and the ring sequence formed by the line structures also comprises a head pointer and a tail pointerThe initial value of the head pointer of the pointer and the initial value of the tail pointer of the ring sequence queue are 1 and 0, and the values of the access times in the row structure are all subjected to zero clearing treatment in a ring sequence read-write mode.
And the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, when the instruction is read data, firstly, whether the corresponding Bank line number in the line structure is matched with the SRAM read-write address is checked according to a loop sequence, and if the Bank line data corresponding to the Bank line number is hit, the Bank line data is returned to the memory access controller between the line buffer register groups.
If all the banked data cached in the line buffer register group are not hit, the line buffer register group reads out corresponding data from the SRAM Bank corresponding to the SRAM read-write address according to the line replacement strategy in the FIFO mode, and simultaneously, the data read out this time is added into the annular queue. More specifically, when writing the read data into the line buffer register group, the following operations are further performed according to whether the ring queue formed by the line structures of the line buffer register group is full:
if the circular queue is full, that is, the value of the head pointer is equal to the value of the tail pointer, adding the read data to the row structure pointed by the head pointer at the moment, adding 1 to the value of the head pointer, and adding 1 to the value of the tail pointer;
if the circular queue is not full, i.e., the value of the head pointer is not equal to the value of the tail pointer, then the read data is added to the row structure pointed to by the head pointer at that time, and the value of the head pointer is added by 1.
And the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, when the instruction is write-in data, the corresponding data in the instruction is directly written into an SRAM Bank corresponding to the SRAM read-write address, and meanwhile, if the data corresponding to the SRAM read-write address exists in the line buffer register group, the Bank row data corresponding to the SRAM read-write address in a line structure is updated, the data written into the SRAM Bank is written into the line structure, but the values of the head pointer and the tail pointer are not changed.
d, if the read-write strategy corresponding to the data read-write instruction is FILO, the line buffer register group executes data read-write operation according to the line replacement strategy in the FILO mode.
In the FILO mode, the line buffer controller is in a ring sequence read-write mode, and when the distributor sends the instruction to the line buffer register group according to the SRAM read-write address and the instruction is read data, the line buffer controller in the FILO mode is consistent with the operation in the FIFO mode under the condition of data hit.
If all the banked data cached in the line buffer register group is not hit, that is, the line buffer register group does not cache the data corresponding to the SRAM read-write address, then according to the line replacement policy in FILO mode, the line buffer register group reads the corresponding data from the SRAM Bank corresponding to the SRAM read-write address, and at the same time, writes the read data into the line buffer register group, and according to the condition that whether the ring queue formed by the line structures of the line buffer register group is full, the following operations are further divided into:
if the circular queue is full, i.e. the value of the head pointer equals the value of the tail pointer, then the read data is added to the row structure pointed to by the head pointer at that time;
if the circular queue is not full, i.e., the value of the head pointer is not equal to the value of the tail pointer, then the read data is added to the row structure pointed to by the head pointer at that time, and the value of the head pointer is added by 1.
And the distributor sends the instruction to the line buffer register group according to the SRAM read-write address, and when the instruction is write data, the operation of the line buffer register group is consistent with the operation in the FLFO mode.
Preferably, the read-write strategy used in the embodiment of the present invention, that is, the queue control method of LRU, NMRU, FIFO, FILO, is implemented by changing the assignment of the read-write strategy in the policy register through an instruction issued by the CPU, and in addition, the read-write strategy can implement, through programming, the four queue control methods including but not limited to the above four queue control methods to implement a more refined read-write strategy, so that the line buffer register group can implement reading and writing of the SRAM Bank through different line replacement strategies.
The invention has the advantages that the line buffer controller does not comprise the SRAM and is arranged between the memory access controller and the structure of the SRAM Bank, so that the circuit scale of the memory unit can be reduced, the extra operation caused by memory miss can be reduced, the power consumption of on-chip SRAM cache reading and writing can be reduced, and meanwhile, more refined dynamic power consumption control can be realized through a controllable reading and writing strategy.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a line buffer controller according to an embodiment of the present invention, in the embodiment of the present invention, the line buffer controller 200 includes a policy register 201, a distributor 202, and a line buffer register set 203, where:
the policy register 201 is used for setting an access domain and a read-write policy;
the distributor 202 is configured to monitor an SRAM read-write address from the storage access controller, and issue a data read-write instruction according to the SRAM read-write address;
the line buffer register group 203 is configured to adjust a line replacement policy according to the data read-write instruction, and perform read-out or/and write-in operations of data according to the line replacement policy.
Furthermore, the read-write strategy comprises at least one of FIFO, FILO, LRU and NMRU, and the step of monitoring the SRAM read-write address from the memory access controller and issuing a data read-write instruction according to the SRAM read-write address comprises the following sub-steps:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space:
if the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
The line buffer controller 200 provided in the embodiment of the present invention can implement the steps in the SRAM read/write control method mentioned in the above embodiment, and can implement the same technical effects, and for avoiding repetition, the descriptions in the above embodiment are referred to, and are not repeated here.
An embodiment of the present invention further provides a computer device, and fig. 6 is a schematic structural diagram of a computer device provided in an embodiment of the present invention, where the computer device 300 includes: a memory 302, a processor 301, and a computer program stored on the memory 302 and executable on the processor 301.
The processor 301 calls the computer program stored in the memory 302 to execute the steps in the SRAM read/write control method according to the embodiment of the present invention, and with reference to fig. 1, the method specifically includes:
s101, setting an access domain and a read-write strategy in a strategy register;
further, the step of setting the access domain and the read-write policy in the policy register includes the following substeps:
the policy register receives the access operation of the CPU and acquires assignment;
and setting the access domain of the policy register to be associated with a storage address in the SRAM according to the assignment, and setting the read-write policy.
The read-write strategy comprises at least one of FIFO, FILO, LRU and NMRU.
S102, monitoring an SRAM read-write address from a storage access controller through a distributor, and sending a data read-write instruction according to the SRAM read-write address;
furthermore, the step of monitoring the SRAM read-write address from the storage access controller by the distributor and issuing a data read-write instruction according to the SRAM read-write address includes the following substeps:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space: (ii) a
If the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
Furthermore, the line buffer register group is a line structure organized by lines, wherein the structure of each line comprises valid values, Bank line numbers, access times and Bank line data.
S103, adjusting a line replacement strategy through a line buffer register group according to the data read-write instruction, and performing data read-out or/and write-in operation according to the line replacement strategy.
Furthermore, the step of adjusting the line replacement policy according to the data read-write instruction by the line buffer register group and performing data read-out or/and write-in operation according to the line replacement policy includes the following steps:
if the read-write strategy corresponding to the data read-write instruction is LRU, the line buffer register group performs data read-write operation according to the line replacement strategy in the LRU mode, wherein the line buffer register group is a concurrent read-write mode, and the line buffer register group performs the LRU algorithm according to the hit condition of the data read-write instruction to perform read-out or/and write-in operation of data in the SRAM;
if the read-write strategy corresponding to the data read-write instruction is an NMRU, the line buffer register group executes data read-write operation according to the line replacement strategy in an NMRU mode, wherein the line buffer register group is in a concurrent read-write mode, and executes an NMRU algorithm according to the hit condition of the data read-write instruction to read or/and write data in an SRAM (static random access memory);
if the read-write strategy corresponding to the data read-write instruction is FIFO, the line buffer register group performs data read-write operation according to the line replacement strategy in an FIFO mode, wherein the line buffer register group is in a loop sequence read-write mode, and the line buffer register group performs FIFO algorithm by using a loop queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM;
and if the read-write strategy corresponding to the data read-write instruction is FILO, the line buffer register group executes data read-write operation according to the line replacement strategy in the FILO mode, wherein the line buffer register group is in a ring sequence read-write mode, and executes a FILO algorithm by using a ring queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM.
The computer device 300 provided in the embodiment of the present invention can implement the steps in the SRAM read/write control method mentioned in the above embodiment, and can implement the same technical effects, and for avoiding repetition, reference is made to the description in the above embodiment, and details are not repeated here.
The embodiment of the present invention further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements each process and step in the SRAM read-write control method provided in the embodiment of the present invention, and can implement the same technical effect, and in order to avoid repetition, details are not repeated here.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, which are illustrative, but not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An SRAM read-write control method is characterized by comprising the following steps:
setting an access domain and a read-write strategy in a strategy register;
monitoring an SRAM read-write address from a storage access controller through a distributor, and sending a data read-write instruction according to the SRAM read-write address;
and adjusting a line replacement strategy through a line buffer register group according to the data read-write instruction, and performing data read-out or/and write-in operation according to the line replacement strategy.
2. The SRAM read-write control method of claim 1, wherein the step of setting the access field and the read-write policy in the policy register comprises the substeps of:
the policy register receives the access operation of the CPU and acquires assignment;
and setting the access domain of the policy register to be associated with a storage address in an SRAM according to the assignment, and setting the read-write policy.
3. The SRAM read-write control method of claim 2, wherein the read-write policy comprises at least one of FIFO, FILO, LRU, NMRU.
4. The SRAM read-write control method of claim 1, wherein the step of monitoring the SRAM read-write address from the memory access controller by the allocator and issuing a data read-write command according to the SRAM read-write address comprises the substeps of:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space:
if the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
5. The SRAM read-write control method of claim 3, wherein the line buffer register group is a line structure organized by lines, wherein a structure of each line includes valid values, Bank line numbers, access times, Bank row data.
6. The method for controlling read/write of SRAM as claimed in claim 5, wherein the step of adjusting a row replacement policy according to the data read/write command by a row buffer register set and performing data read or/and write operations according to the row replacement policy comprises the steps of:
if the read-write strategy corresponding to the data read-write instruction is LRU, the line buffer register group performs data read-write operation according to the line replacement strategy in the LRU mode, wherein the line buffer register group is a concurrent read-write mode, and the line buffer register group performs the LRU algorithm according to the hit condition of the data read-write instruction to perform read-out or/and write-in operation of data in the SRAM;
if the read-write strategy corresponding to the data read-write instruction is an NMRU, the line buffer register group executes data read-write operation according to the line replacement strategy in an NMRU mode, wherein the line buffer register group is in a concurrent read-write mode, and executes an NMRU algorithm according to the hit condition of the data read-write instruction to read or/and write data in an SRAM (static random access memory);
if the read-write strategy corresponding to the data read-write instruction is FIFO, the line buffer register group performs data read-write operation according to the line replacement strategy in an FIFO mode, wherein the line buffer register group is in a loop sequence read-write mode, and the line buffer register group performs FIFO algorithm by using a loop queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM;
and if the read-write strategy corresponding to the data read-write instruction is FILO, the line buffer register group executes data read-write operation according to the line replacement strategy in the FILO mode, wherein the line buffer register group is in a ring sequence read-write mode, and executes a FILO algorithm by using a ring queue according to the hit condition of the data read-write instruction to read or/and write data in the SRAM.
7. A line buffer controller, comprising:
the strategy register is used for setting an access domain and a read-write strategy;
the distributor is used for monitoring the SRAM read-write address from the storage access controller and sending a data read-write instruction according to the SRAM read-write address;
and the line buffer register group is used for adjusting a line replacement strategy according to the data reading and writing instruction and performing data reading or/and writing operation according to the line replacement strategy.
8. The line buffer controller of claim 7, wherein the read-write strategy comprises at least one of FIFO, FILO, LRU, NMRU, and wherein the step of monitoring the SRAM read-write address from the memory access controller and issuing a data read-write command based on the SRAM read-write address comprises the sub-steps of:
the distributor monitors the SRAM read-write address from the storage access controller and judges whether the SRAM read-write address and the access domain of the policy register are in the same address space:
if the SRAM read-write address and the access domain of the policy register are in the same address space, the distributor generates the data read-write instruction according to the SRAM read-write address and sends the data read-write instruction to the line buffer register group;
and if the SRAM read-write address and the access domain of the strategy register are not in the same address space, the distributor does not perform any processing.
9. A computer device, comprising: memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps in the SRAM read-write control method according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program, which when executed by a processor implements the steps in the SRAM read-write control method according to any one of claims 1 to 6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116312671A (en) * | 2023-05-19 | 2023-06-23 | 珠海妙存科技有限公司 | SRAM resetting method, circuit, chip, device and medium |
| CN117917735A (en) * | 2024-03-20 | 2024-04-23 | 北京微核芯科技有限公司 | Read-write control method and device of pseudo-dual-port SRAM |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107491397A (en) * | 2016-06-08 | 2017-12-19 | 三星电子株式会社 | The operating method of storage device, memory module and storage device |
| JP2018032256A (en) * | 2016-08-25 | 2018-03-01 | 東芝メモリ株式会社 | Memory system and processor system |
| US20190243760A1 (en) * | 2017-01-18 | 2019-08-08 | Intel Corporation | Memory-efficient last level cache architecture |
| US20190384718A1 (en) * | 2016-11-29 | 2019-12-19 | Arm Limited | Storage circuitry responsive to a tag-matching command |
| WO2020132434A1 (en) * | 2018-12-21 | 2020-06-25 | Micron Technology, Inc. | Signal development caching in a memory device |
| CN111381772A (en) * | 2018-12-28 | 2020-07-07 | 爱思开海力士有限公司 | Controller of semiconductor memory device and method of operating the same |
| CN112306387A (en) * | 2019-07-24 | 2021-02-02 | 爱思开海力士有限公司 | Memory system, memory controller and method of operating memory system |
-
2021
- 2021-10-18 CN CN202111207496.6A patent/CN113641626B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107491397A (en) * | 2016-06-08 | 2017-12-19 | 三星电子株式会社 | The operating method of storage device, memory module and storage device |
| JP2018032256A (en) * | 2016-08-25 | 2018-03-01 | 東芝メモリ株式会社 | Memory system and processor system |
| US20190384718A1 (en) * | 2016-11-29 | 2019-12-19 | Arm Limited | Storage circuitry responsive to a tag-matching command |
| US20190243760A1 (en) * | 2017-01-18 | 2019-08-08 | Intel Corporation | Memory-efficient last level cache architecture |
| WO2020132434A1 (en) * | 2018-12-21 | 2020-06-25 | Micron Technology, Inc. | Signal development caching in a memory device |
| WO2020132430A1 (en) * | 2018-12-21 | 2020-06-25 | Micron Technology, Inc. | Page policies for signal development caching in a memory device |
| CN113196248A (en) * | 2018-12-21 | 2021-07-30 | 美光科技公司 | Page policy for signal development caching in memory devices |
| CN111381772A (en) * | 2018-12-28 | 2020-07-07 | 爱思开海力士有限公司 | Controller of semiconductor memory device and method of operating the same |
| CN112306387A (en) * | 2019-07-24 | 2021-02-02 | 爱思开海力士有限公司 | Memory system, memory controller and method of operating memory system |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116312671A (en) * | 2023-05-19 | 2023-06-23 | 珠海妙存科技有限公司 | SRAM resetting method, circuit, chip, device and medium |
| CN116312671B (en) * | 2023-05-19 | 2023-08-29 | 珠海妙存科技有限公司 | SRAM resetting method, circuit, chip, device and medium |
| CN117917735A (en) * | 2024-03-20 | 2024-04-23 | 北京微核芯科技有限公司 | Read-write control method and device of pseudo-dual-port SRAM |
| CN117917735B (en) * | 2024-03-20 | 2024-05-31 | 北京微核芯科技有限公司 | Read-write control method and device of pseudo-dual-port SRAM |
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|---|---|
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