CN110707187A - Epitaxial wafer of small-spacing light-emitting diode and manufacturing method thereof - Google Patents
Epitaxial wafer of small-spacing light-emitting diode and manufacturing method thereof Download PDFInfo
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- CN110707187A CN110707187A CN201910773000.8A CN201910773000A CN110707187A CN 110707187 A CN110707187 A CN 110707187A CN 201910773000 A CN201910773000 A CN 201910773000A CN 110707187 A CN110707187 A CN 110707187A
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
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Abstract
The invention discloses an epitaxial wafer of a small-spacing light-emitting diode and a manufacturing method thereof, belonging to the technical field of semiconductors. The epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are sequentially stacked, wherein the active layer comprises a first superlattice structure and a second superlattice structure which are sequentially stacked, and the material of a quantum well in the first superlattice structure and the second superlattice structure adopts indium gallium nitride; the quantum barrier in the second superlattice structure comprises (n +1) first sub-layers and n second sub-layers which are alternately stacked, wherein n is a positive integer, and the materials of the quantum barrier in the first sub-layers, the second sub-layers and the first superlattice structure adopt gallium nitride doped with silicon; the doping concentration of silicon in the first sub-layer and the doping concentration of silicon in the second sub-layer are respectively 11-20 times and 5-10 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure. The invention has small variation amplitude of the luminous wavelength under different currents, and can meet the display requirement of the HDR of the cinema.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an epitaxial wafer of a small-spacing light-emitting diode and a manufacturing method thereof.
Background
A Light Emitting Diode (LED) is a semiconductor electronic component capable of Emitting Light. As a new solid-state light source with high efficiency, environmental protection and green, LEDs are not only widely used in lighting fields such as traffic lights, interior and exterior lights of automobiles, and urban landscapes, but also being used in display fields such as indoor and outdoor display screens and small-pitch display screens.
The small-distance display screen is an indoor LED display screen with the LED point distance below P2.5, and the state control of the reducibility and the uniformity of the brightness and the color of a display screen pixel unit is realized by adopting a pixel-level point control technology. The most competitive power of the small-space display screen lies in that the display screen is completely seamless and displays natural and real colors, and can be used for displaying high-dynamic range (HDR) images played in a cinema, and the variation range of the light-emitting wavelength is required to be small and relatively stable in the process of injecting currents with different sizes to realize the light-emitting intensity.
The epitaxial wafer is a primary finished product in the LED manufacturing process. The conventional LED epitaxial wafer comprises a substrate, a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer, wherein the buffer layer, the N-type semiconductor layer, the active layer and the P-type semiconductor layer are sequentially laminated on the substrate. The substrate is used for providing an epitaxial growth surface, the buffer layer is used for providing a nucleation center of epitaxial growth, the N-type semiconductor layer is used for providing electrons of composite luminescence, the P-type semiconductor layer is used for providing holes of the composite luminescence, and the active layer is used for carrying out the composite luminescence of the electrons and the holes. The active layer comprises a plurality of quantum well layers and a plurality of quantum barrier layers, and the quantum well layers and the quantum barrier layers are alternately laminated; the quantum barrier layer limits electrons and holes injected into the active layer in the quantum well layer to carry out composite light emission.
In the process of implementing the invention, the inventor finds that the prior art has at least the following problems:
the quantum well layer is made of indium gallium nitride (InGaN), and the quantum barrier layer is made of undoped gallium nitride (GaN). The quantum well layer and the quantum barrier layer are made of different materials, and lattice mismatch exists between the quantum well layer and the quantum barrier layer. The lattice mismatch causes piezoelectric polarization in the active layer, which generates a quantum-confined starkeeffect (QCSE), causing a shift in the emission wavelength of the active layer. When the light emitting intensity of the active layer is changed by changing the magnitude of the injected current, the offset of the light emitting wavelength of the active layer is different, so that the light emitting wavelength of the active layer is greatly changed, the display effect of the HDR of the cinema is influenced, and the application requirement of a small-distance display screen cannot be met.
Disclosure of Invention
The embodiment of the invention provides an epitaxial wafer of a small-spacing light-emitting diode and a manufacturing method thereof, which can reduce piezoelectric polarization in an active layer and solve the problem that the light-emitting wavelength of the active layer in the prior art greatly fluctuates in the change process of light-emitting intensity. The technical scheme is as follows:
in one aspect, an embodiment of the present invention provides an epitaxial wafer of a small-pitch light emitting diode, where the epitaxial wafer includes a substrate, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer, and the buffer layer, the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are sequentially stacked on the substrate; the active layer comprises a first superlattice structure and a second superlattice structure which are sequentially stacked, and the first superlattice structure and the second superlattice structure both comprise a plurality of quantum wells and a plurality of quantum barriers which are alternately stacked; the quantum well in the first superlattice structure and the second superlattice structure is made of indium gallium nitride; the quantum barrier in the second superlattice structure comprises (n +1) first sub-layers and n second sub-layers which are alternately stacked, n is a positive integer, and the materials of the quantum barrier in the first sub-layers, the second sub-layers and the first superlattice structure adopt gallium nitride doped with silicon; the doping concentration of silicon in the first sub-layer is 11-20 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure, and the doping concentration of silicon in the second sub-layer is 5-10 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure.
Optionally, the doping concentration of silicon in the first sub-layer gradually increases along the stacking direction of the active layer.
Further, the doping concentration of silicon in the second sub-layer gradually decreases along the stacking direction of the active layer.
Optionally, the content of the indium component in the quantum well in the second superlattice structure is 0.3-0.4, the thickness of the quantum barrier in the second superlattice structure is 51-60 times that of the quantum well, and the doping concentration of silicon in the first sub-layer is 5 x 1018/cm3～2*1019/cm3The doping concentration of silicon in the second sublayer is 2.5 x 1018/cm3～1019/cm3。
Further, the content of the indium component in the quantum well in the second superlattice structure is 0.3, the thickness of the quantum barrier in the second superlattice structure is 60 times that of the quantum well, and the doping concentration of silicon in the first sub-layer is from 10 in the stacking direction of the active layer19/cm3Gradually increase to 2 x 1019/cm3The doping concentration of silicon in the second sublayer is from 7.5 x 10 along the stacking direction of the active layer18/cm3Gradually decrease to 5 x 1018/cm3。
Optionally, the number of quantum barriers in the second superlattice structure is less than the number of quantum barriers in the first superlattice structure.
Further, the number of quantum barriers in the second superlattice structure is three.
Optionally, n is 2.
In another aspect, an embodiment of the present invention provides a method for manufacturing an epitaxial wafer of a small-pitch light emitting diode, where the method includes:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
wherein the active layer includes a first superlattice structure and a second superlattice structure stacked in sequence, and the first superlattice structure and the second superlattice structure each include a plurality of quantum wells and a plurality of quantum barriers stacked alternately; the quantum well in the first superlattice structure and the second superlattice structure is made of indium gallium nitride; the quantum barrier in the second superlattice structure comprises (n +1) first sub-layers and n second sub-layers which are alternately stacked, n is a positive integer, and the materials of the quantum barrier in the first sub-layers, the second sub-layers and the first superlattice structure adopt gallium nitride doped with silicon; the doping concentration of silicon in the first sub-layer is 11-20 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure, and the doping concentration of silicon in the second sub-layer is 5-10 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure.
Optionally, the growth conditions of the quantum barriers in the first sub-layer, the second sub-layer and the first superlattice structure are the same, and the growth conditions include growth temperature and growth pressure.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
along with the growth of the active layer, the degree of lattice mismatch is larger and larger, so that the piezoelectric polarization of the part, close to the P-type semiconductor layer, in the active layer is worse than that of the part, close to the N-type semiconductor layer, in the active layer, and meanwhile, the part, close to the P-type semiconductor layer, in the active layer is a main light emitting area because the mobility and the migration rate of holes are poorer than those of electrons. According to the embodiment of the invention, the silicon impurities far more than the quantum barriers close to the N-type semiconductor layer are doped in the quantum barriers close to the P-type semiconductor layer in the active layer, the epitaxial growth mode is changed into spiral growth by utilizing the silicon impurities, and the high-density nano island-shaped structure is formed, so that the band gap fluctuation can be effectively inhibited, the electric field generated by piezoelectric polarization is shielded, the light-emitting wavelength of the active layer is kept as stable as possible in the variation process of the light-emitting intensity, and the application requirement of the small-spacing display screen is met. And a sub-layer with low doping concentration of silicon is inserted into the quantum barrier close to the P-type semiconductor layer in the active layer, so that on one hand, the situation that the overall lattice integrity of the epitaxial wafer is influenced due to too much increased doping concentration of silicon can be avoided, on the other hand, electrons and holes are limited in the quantum well to carry out compound luminescence, and the quantum barrier plays a role.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an epitaxial wafer of a small-pitch light emitting diode according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an active layer provided in an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a small-pitch light emitting diode according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The embodiment of the invention provides an epitaxial wafer of a small-spacing light-emitting diode. Fig. 1 is a schematic structural diagram of an epitaxial wafer of a small-pitch light emitting diode according to an embodiment of the present invention. Referring to fig. 1, the epitaxial wafer includes a substrate 10, a buffer layer 20, an N-type semiconductor layer 30, an active layer 40, and a P-type semiconductor layer 50, and the buffer layer 20, the N-type semiconductor layer 30, the active layer 40, and the P-type semiconductor layer 50 are sequentially stacked on the substrate 10.
Fig. 2 is a schematic structural diagram of an active layer according to an embodiment of the present invention. Referring to fig. 2, in the present embodiment, the active layer 40 includes a first superlattice structure 41 and a second superlattice structure 42 that are sequentially stacked, and each of the first superlattice structure 41 and the second superlattice structure 42 includes a plurality of quantum wells 43 and a plurality of quantum barriers 44 that are alternately stacked. The material of the quantum well 43 in the first superlattice structure 41 and the second superlattice structure 42 is indium gallium nitride. The quantum barrier 44 in the second superlattice structure 42 includes (n +1) first sub-layers 441 and n second sub-layers 442 which are alternately stacked, n is a positive integer, and the materials of the first sub-layers 441, the second sub-layers 442 and the quantum barrier 44 in the first superlattice structure 41 adopt gallium nitride doped with silicon. The doping concentration of silicon in the first sub-layer 441 is 11 to 20 times that of silicon in the quantum barrier 44 in the first superlattice structure 41, and the doping concentration of silicon in the second sub-layer 442 is 5 to 10 times that of silicon in the quantum barrier 44 in the first superlattice structure 41.
Along with the growth of the active layer, the degree of lattice mismatch is larger and larger, so that the piezoelectric polarization of the part, close to the P-type semiconductor layer, in the active layer is worse than that of the part, close to the N-type semiconductor layer, in the active layer, and meanwhile, the part, close to the P-type semiconductor layer, in the active layer is a main light emitting area because the mobility and the migration rate of holes are poorer than those of electrons. According to the embodiment of the invention, the silicon impurities far more than the quantum barriers close to the N-type semiconductor layer are doped in the quantum barriers close to the P-type semiconductor layer in the active layer, the epitaxial growth mode is changed into spiral growth by utilizing the silicon impurities, and the high-density nano island-shaped structure is formed, so that the band gap fluctuation can be effectively inhibited, the electric field generated by piezoelectric polarization is shielded, the light-emitting wavelength of the active layer is kept as stable as possible in the variation process of the light-emitting intensity, and the application requirement of the small-spacing display screen is met. And a sub-layer with low doping concentration of silicon is inserted into the quantum barrier close to the P-type semiconductor layer in the active layer, so that on one hand, the situation that the overall lattice integrity of the epitaxial wafer is influenced due to too much increased doping concentration of silicon can be avoided, on the other hand, electrons and holes are limited in the quantum well to carry out compound luminescence, and the quantum barrier plays a role.
Alternatively, the doping concentration of silicon in the first sub-layer 441 may be gradually increased along the stacking direction of the active layer 40, so that the variation of the doping concentration of silicon in the first sub-layer matches the variation of the degree of lattice mismatch and the variation of the composite light emission ratio. The closer to the P-type semiconductor layer, the more serious the lattice mismatch effect accumulated between the quantum well and the quantum barrier, the more the number of holes for performing composite luminescence in the quantum well, and the higher the doping concentration of silicon in the first sub-layer, the more the piezoelectric polarization generated by lattice mismatch can be effectively shielded, which is more beneficial to maintaining the stability of the whole luminescence wavelength of the active layer in the change process of the luminescence intensity.
Further, the doping concentration of silicon in the second sub-layer 442 may gradually decrease along the stacking direction of the active layer 40, so that the variation of the doping concentration of silicon in the second sub-layer matches the variation of the doping concentration of silicon in the first sub-layer. The doping concentration of the silicon in the first sub-layer is higher and the doping concentration of the silicon in the second sub-layer is higher closer to the P-type semiconductor layer, so that the situation that the doping concentration of the silicon in the first sub-layer is increased too much to influence the integral crystal lattice integrity of the epitaxial wafer can be avoided, and the electron and the hole are limited in the quantum well to perform compound luminescence to play a role of a quantum barrier.
Optionally, the content of the indium component In the quantum well 43 In the second superlattice structure 42 may be 0.3-0.4, that is, the quantum well 43 In the second superlattice structure 42 is InxGa1-xX is more than or equal to 0.3 and less than or equal to 0.4; the thickness of the quantum barrier 44 in the second superlattice structure 42 may be 51-60 times the thickness of the quantum well 43; the doping concentration of silicon in the first sublayer 441 may be 5 x 1018/cm3～2*1019/cm3The doping concentration of silicon in the second sub-layer 442 may be 2.5 x 1018/cm3～1019/cm3。
According to the embodiment of the invention, the content of the indium component in the quantum well is reduced, the thickness ratio of the quantum barrier to the quantum well is increased, and the ratio is matched with the change of the silicon doping concentration in the quantum barrier, so that the piezoelectric polarization of the part, close to the P-type semiconductor layer, of the active layer is effectively shielded, and the stability of the whole light-emitting wavelength of the active layer is favorably maintained in the change process of the light-emitting intensity.
Further, the content of the indium component in the quantum well 43 in the second superlattice structure 42 may be 0.3, the thickness of the quantum barrier 44 in the second superlattice structure 42 may be 60 times the thickness of the quantum well 43, and the doping concentration of silicon in the first sub-layer 441 may be from 10 in the stacking direction of the active layer 4019/cm3Gradually increase to 2 x 1019/cm3The doping concentration of silicon in the second sub-layer 442 may be alongThe lamination direction of the active layer 40 is from 7.5 x 1018/cm3Gradually decrease to 5 x 1018/cm3。
Experiments show that under the conditions, when the current is increased from 1mA to 9mA, the variation range of the light-emitting wavelength of the whole active layer can be 4 nm-5 nm, and the stability of the light-emitting wavelength is greatly improved compared with the conventional variation range of 9 nm.
Correspondingly, the content of the indium component in the quantum well 43 in the first superlattice structure 41 can also be 0.3-0.4, and the thickness of the quantum barrier 44 in the first superlattice structure 41 can also be 51-60 times of the thickness of the quantum well 43, so that the piezoelectric polarization of the active layer close to the N-type semiconductor layer part is effectively shielded by reducing the content of the indium component in the quantum well and increasing the ratio of the thicknesses of the quantum barrier and the quantum well, and the whole light-emitting wavelength of the active layer is favorably kept stable in the variation process of the light-emitting intensity.
Illustratively, the quantum well 43 may have a thickness of 1.95nm, the quantum barrier 44 may have a thickness of 100nm, and the doping concentration of silicon in the first superlattice structure 41 may be 6 × 1019/cm3The piezoelectric polarization of the active layer part close to the N-type semiconductor layer part can be effectively shielded, and the whole light-emitting wavelength of the active layer is kept stable in the change process of the light-emitting intensity.
Alternatively, the number of quantum barriers 44 in the second superlattice structure 42 may be less than the number of quantum barriers 44 in the first superlattice structure 41. By improving the part which is not more than half of the active layer, the whole crystal lattice integrity of the epitaxial wafer is favorably maintained.
Further, the number of quantum barriers 44 in the second superlattice structure 42 may be three. Only the main light emitting area is improved, and under the condition of effectively maintaining the integral crystal lattice integrity of the epitaxial wafer, the complexity of implementation is reduced, and the implementation cost is reduced.
Accordingly, the number of quantum barriers 44 in the first superlattice structure 41 may be five.
Optionally, n is 2. Under the condition of effectively maintaining the integral crystal lattice integrity of the epitaxial wafer, the complexity of realization is reduced, and the realization cost is reduced.
Alternatively, the material of the substrate 10 may be sapphire (alumina is a main material), such as sapphire with a crystal orientation of [0001 ]. The buffer layer 20 may be made of undoped gallium nitride or aluminum nitride. The N-type semiconductor layer 30 may be N-type doped (e.g., silicon) gan. The P-type semiconductor layer 50 may be made of P-type doped (e.g., mg) gan.
Further, the thickness of the buffer layer 20 may be 15nm to 30nm, preferably 25 nm. The thickness of the N-type semiconductor layer 30 may be 2 to 3 μm, preferably 2.5 μm; the doping concentration of the N-type dopant in the N-type semiconductor layer 30 may be 1018cm-3～1019cm-3Preferably 5 x 1018cm-3. The thickness of the P-type semiconductor layer 50 may be 50nm to 80nm, preferably 65 nm; the doping concentration of the P-type dopant in the P-type semiconductor layer 50 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the epitaxial wafer may further include an undoped gallium nitride layer 60, where the undoped gallium nitride layer 60 is disposed between the buffer layer 20 and the N-type semiconductor layer 30 to relieve stress and defects caused by lattice mismatch between the substrate material and the gallium nitride, and provide a growth surface with good crystal quality for the main structure of the epitaxial wafer.
In a specific implementation, buffer layer 20 is a thin layer of gallium nitride that is first grown at low temperature on a patterned substrate, and is therefore also referred to as a low temperature buffer layer. Then, the longitudinal growth of gallium nitride is carried out on the low-temperature buffer layer, and a plurality of mutually independent three-dimensional island-shaped structures called three-dimensional nucleation layers can be formed; then, transverse growth of gallium nitride is carried out on all the three-dimensional island structures and among the three-dimensional island structures to form a two-dimensional plane structure which is called a two-dimensional recovery layer; and finally, growing a thicker gallium nitride layer called an intrinsic gallium nitride layer on the two-dimensional growth layer at a high temperature. The three-dimensional nucleation layer, two-dimensional recovery layer, and intrinsic gallium nitride layer are collectively referred to as undoped gallium nitride layer 60 in this embodiment.
Further, the thickness of the undoped gallium nitride layer 60 may be 2 μm to 3.5 μm, preferably 2.75 μm.
Optionally, the epitaxial wafer may further include a stress release layer 70, where the stress release layer 70 is disposed between the N-type semiconductor layer 30 and the active layer 40 to release stress generated by lattice mismatch between sapphire and gallium nitride, so as to improve crystal quality of the active layer, facilitate radiation recombination luminescence of electrons and holes in the active layer, improve internal quantum efficiency of the LED, and further improve luminous efficiency of the LED.
Optionally, as shown in fig. 1, the epitaxial wafer may further include an electron blocking layer 81, and the electron blocking layer 81 is disposed between the active layer 40 and the P-type semiconductor layer 50to prevent electrons from jumping into the P-type semiconductor layer to combine with holes in a non-radiative manner, thereby reducing the light emitting efficiency of the LED.
Illustratively, the material of the electron blocking layer 81 may be P-type doped aluminum gallium nitride (AlGaN), such as AlyGa1- yN，0.15＜y＜0.25。
Further, the thickness of the electron blocking layer 81 may be 30nm to 50nm, preferably 40 nm.
Preferably, as shown in fig. 1, the epitaxial wafer may further include a low-temperature P-type layer 82, and the low-temperature P-type layer 82 is disposed between the active layer 40 and the electron blocking layer 81, so as to prevent indium atoms in the active layer from being precipitated due to the high growth temperature of the electron blocking layer, which affects the light emitting efficiency of the light emitting diode.
Illustratively, the material of the low temperature P-type layer 82 may be P-type doped gallium nitride.
Further, the thickness of the low-temperature P-type layer 82 may be 10nm to 50nm, preferably 30 nm; the doping concentration of the P-type dopant in the low temperature P-type layer 82 may be 1018/cm3～1020/cm3Preferably 1019/cm3。
Optionally, as shown in fig. 1, the epitaxial wafer may further include a contact layer 90, and the contact layer 90 is disposed on the P-type semiconductor layer 50to form an ohmic contact with an electrode or a transparent conductive film formed in a chip manufacturing process.
Illustratively, the material of the contact layer 90 may be P-type doped indium gallium nitride or gallium nitride.
Further, the thickness of the contact layer 90 may be 5nm to 300nm, preferably 100 nm; the doping concentration of the P-type dopant in the contact layer 90 may be 1021/cm3～1022/cm3Preferably 5 x 1021/cm3。
The embodiment of the invention provides a method for manufacturing an epitaxial wafer of a small-spacing light-emitting diode, which is suitable for manufacturing the epitaxial wafer of the small-spacing light-emitting diode shown in figure 1. Fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a small-pitch light emitting diode according to an embodiment of the present invention. Referring to fig. 3, the manufacturing method includes:
step 201: a substrate is provided.
Optionally, the step 201 may include:
the substrate is annealed at a temperature of 1000 to 1100 deg.C (preferably 1050 deg.C) and a pressure of 200to 500torr (preferably 350torr) in a hydrogen atmosphere for 5 to 6 minutes (preferably 5.5 minutes).
The surface of the substrate is cleaned through the steps, impurities are prevented from being doped into the epitaxial wafer, and the growth quality of the epitaxial wafer is improved.
Step 202: a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer are sequentially grown on a substrate.
In the present embodiment, the active layer includes a first superlattice structure and a second superlattice structure that are sequentially stacked, and each of the first superlattice structure and the second superlattice structure includes a plurality of quantum wells and a plurality of quantum barriers that are alternately stacked. The quantum well in the first superlattice structure and the second superlattice structure is made of indium gallium nitride. The quantum barrier in the second superlattice structure comprises (n +1) first sub-layers and n second sub-layers which are alternately stacked, n is a positive integer, and the materials of the first sub-layers, the second sub-layers and the quantum barrier in the first superlattice structure adopt gallium nitride doped with silicon. The doping concentration of silicon in the first sub-layer is 11-20 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure, and the doping concentration of silicon in the second sub-layer is 5-10 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure.
Optionally, the growth conditions of the quantum barriers in the first sub-layer, the second sub-layer and the first superlattice structure are the same, and the growth conditions include growth temperature and growth pressure. The same growth conditions are adopted, and the method is convenient to realize.
Optionally, this step 202 may include:
firstly, controlling the temperature to be 530-560 ℃ (preferably 545 ℃) and the pressure to be 200-500 torr (preferably 350torr), and growing a buffer layer on a substrate;
secondly, controlling the temperature to be 1000-1100 ℃ (preferably 1050 ℃) and the pressure to be 200-300 torr (preferably 250torr), and growing an N-type semiconductor layer on the buffer layer;
thirdly, growing an active layer on the N-type semiconductor layer; wherein, the growth temperature of the quantum well is 760 ℃ to 780 ℃ (preferably 770 ℃), and the pressure is 200 torr; the growth temperature of the quantum barrier is 860 ℃ -890 ℃ (preferably 875 ℃), and the pressure is 200 torr;
and fourthly, controlling the temperature to be 940-980 ℃ (preferably 960 ℃) and the pressure to be 200-600 torr (preferably 400torr), and growing the P-type semiconductor layer on the active layer.
Optionally, before the second step, the manufacturing method may further include:
and growing an undoped gallium nitride layer on the buffer layer.
Accordingly, an N-type semiconductor layer is grown on the undoped gallium nitride layer.
Further, growing an undoped gallium nitride layer on the buffer layer may include:
an undoped gallium nitride layer is grown on the buffer layer at a temperature of 1000 ℃ to 1100 ℃ (preferably 1050 ℃) and a pressure of 200torr to 600torr (preferably 400 torr).
Optionally, before the third step, the manufacturing method may further include:
and growing a stress release layer on the N-type semiconductor layer.
Accordingly, an active layer is grown on the stress relieving layer.
Optionally, before the fourth step, the manufacturing method may further include:
an electron blocking layer is grown on the active layer.
Accordingly, a P-type semiconductor layer is grown on the electron blocking layer.
Further, growing an electron blocking layer on the active layer may include:
the electron blocking layer is grown on the active layer at a controlled temperature of 930 deg.C to 970 deg.C (preferably 950 deg.C) and a pressure of 100 torr.
Preferably, before growing the electron blocking layer on the active layer, the manufacturing method may further include:
a low temperature P-type layer is grown on the active layer.
Accordingly, an electron blocking layer is grown on the low temperature P-type layer.
Further, growing the low temperature P-type layer on the active layer may include:
the temperature is controlled to be 600 ℃ to 850 ℃ (preferably 750 ℃) and the pressure is controlled to be 100torr to 600torr (preferably 300torr), and the low-temperature P type layer is grown on the active layer.
Optionally, after the fourth step, the manufacturing method may further include:
and growing a contact layer on the P-type semiconductor layer.
Further, growing a contact layer on the P-type semiconductor layer may include:
the contact layer is grown on the P-type semiconductor layer at a temperature of 850 to 1050 deg.C (preferably 950 deg.C) and a pressure of 100to 300torr (preferably 200 torr).
After the completion of the epitaxial growth, the temperature is lowered to 650 to 850 ℃ (preferably 750 ℃), the epitaxial wafer is annealed in a nitrogen atmosphere for 5 to 15 minutes (preferably 10 minutes), and then the temperature of the epitaxial wafer is lowered to room temperature.
The control of the temperature and the pressure both refer to the control of the temperature and the pressure in a reaction chamber for growing the epitaxial wafer, and specifically refer to the reaction chamber of a Metal-organic Chemical Vapor Deposition (MOCVD) device, such as Veeco K465i MOCVD or Veeco C4 MOCVD. When implemented with hydrogen (H)2) Or nitrogen (N)2) Or hydrogenMixed gas of gas and nitrogen as carrier gas, trimethyl gallium (TMGa) or triethyl gallium (TEGa) as gallium source, and high-purity ammonia (NH)3) As a nitrogen source, trimethylindium (TMIn) as an indium source, trimethylaluminum (TMAl) as an aluminum source, Silane (SiH)4) As silicon source, magnesium dicocene (Cp)2Mg) as a magnesium source.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. An epitaxial wafer of a small-pitch light emitting diode, the epitaxial wafer comprises a substrate (10), a buffer layer (20), an N-type semiconductor layer (30), an active layer (40) and a P-type semiconductor layer (50), wherein the buffer layer (20), the N-type semiconductor layer (30), the active layer (40) and the P-type semiconductor layer (50) are sequentially laminated on the substrate (10); characterized in that the active layer (40) comprises a first superlattice structure (41) and a second superlattice structure (42) stacked in sequence, the first superlattice structure (41) and the second superlattice structure (42) each comprising a plurality of quantum wells (43) and a plurality of quantum barriers (44) stacked alternately; the material of the quantum well (43) in the first superlattice structure (41) and the second superlattice structure (42) adopts indium gallium nitride; the quantum barrier (44) in the second superlattice structure (42) comprises (n +1) first sub-layers (441) and n second sub-layers (442) which are alternately stacked, n is a positive integer, and the materials of the quantum barrier (44) in the first superlattice structure (41), the first sub-layers (441), the second sub-layers (442) and the second superlattice structure adopt silicon-doped gallium nitride; the doping concentration of silicon in the first sub-layer (441) is 11 to 20 times that of silicon in the quantum barrier (44) in the first superlattice structure (41), and the doping concentration of silicon in the second sub-layer (442) is 5 to 10 times that of silicon in the quantum barrier (44) in the first superlattice structure (41).
2. The epitaxial wafer according to claim 1, characterized in that the doping concentration of silicon in the first sub-layer (441) is gradually increased along the stacking direction of the active layer (40).
3. The epitaxial wafer according to claim 2, characterized in that the doping concentration of silicon in the second sub-layer (442) decreases gradually along the stacking direction of the active layer (40).
4. An epitaxial wafer according to any of claims 1 to 3, characterized in that the content of indium component in the quantum well (43) in the second superlattice structure (42) is 0.3 to 0.4, the thickness of the quantum barrier (44) in the second superlattice structure (42) is 51 to 60 times the thickness of the quantum well (43), and the doping concentration of silicon in the first sub-layer (441) is 5 to 1018/cm3～2*1019/cm3The doping concentration of silicon in the second sub-layer (442) is 2.5 x 1018/cm3～1019/cm3。
5. An epitaxial wafer according to claim 4, characterized in that the content of indium component in the quantum well (43) in the second superlattice structure (42) is 0.3, the thickness of the quantum barrier (44) in the second superlattice structure (42) is 60 times the thickness of the quantum well (43), and the doping concentration of silicon in the first sub-layer (441) is from 10 in the stacking direction of the active layer (40)19/cm3Gradually increase to 2 x 1019/cm3The doping concentration of silicon in the second sub-layer (442) is from 7.5 x 10 in the stacking direction of the active layer (40)18/cm3Gradually decrease to 5 x 1018/cm3。
6. An epitaxial wafer according to any of claims 1 to 3, characterized in that the number of quantum barriers (44) in the second superlattice structure (42) is smaller than the number of quantum barriers (44) in the first superlattice structure (41).
7. The epitaxial wafer of claim 6, characterized in that the number of quantum barriers (44) in the second superlattice structure (42) is three.
8. An epitaxial wafer according to any one of claims 1 to 3, wherein n is 2.
9. A manufacturing method of an epitaxial wafer of a small-spacing light-emitting diode is characterized by comprising the following steps:
providing a substrate;
growing a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer on the substrate in sequence;
wherein the active layer includes a first superlattice structure and a second superlattice structure stacked in sequence, and the first superlattice structure and the second superlattice structure each include a plurality of quantum wells and a plurality of quantum barriers stacked alternately; the quantum well in the first superlattice structure and the second superlattice structure is made of indium gallium nitride; the quantum barrier in the second superlattice structure comprises (n +1) first sub-layers and n second sub-layers which are alternately stacked, n is a positive integer, and the materials of the quantum barrier in the first sub-layers, the second sub-layers and the first superlattice structure adopt gallium nitride doped with silicon; the doping concentration of silicon in the first sub-layer is 11-20 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure, and the doping concentration of silicon in the second sub-layer is 5-10 times of the doping concentration of silicon in the quantum barrier in the first superlattice structure.
10. The method of manufacturing of claim 9, wherein the growth conditions of the quantum barriers in the first sub-layer, the second sub-layer, and the first superlattice structure are the same, and the growth conditions include a growth temperature and a growth pressure.
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