CN110696671B - Signal detection method, computer equipment and computer readable storage medium - Google Patents

Signal detection method, computer equipment and computer readable storage medium Download PDF

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CN110696671B
CN110696671B CN201910841180.9A CN201910841180A CN110696671B CN 110696671 B CN110696671 B CN 110696671B CN 201910841180 A CN201910841180 A CN 201910841180A CN 110696671 B CN110696671 B CN 110696671B
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signal
voltage
voltage value
reference voltage
value
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CN110696671A (en
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石宝辉
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Evergrande Hengchi New Energy Automobile Research Institute Shanghai Co Ltd
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Evergrande Hengchi New Energy Automobile Research Institute Shanghai Co Ltd
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L53/00—Methods of charging batteries, specially adapted for electric vehicles; Charging stations or on-board charging equipment therefor; Exchange of energy storage elements in electric vehicles
    • B60L53/60—Monitoring or controlling charging stations
    • B60L53/62—Monitoring or controlling charging stations in response to charging parameters, e.g. current, voltage or electrical charge
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/7072—Electromobility specific charging systems or methods for batteries, ultracapacitors, supercapacitors or double-layer capacitors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02T90/10—Technologies relating to charging of electric vehicles
    • Y02T90/12—Electric charging stations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02T90/10—Technologies relating to charging of electric vehicles
    • Y02T90/16—Information or communication technologies improving the operation of electric vehicles

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Transportation (AREA)
  • Mechanical Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The invention provides a signal detection method, which comprises the following steps: acquiring a digital signal, wherein the digital signal is generated according to an input signal and a stored reference voltage value; and obtaining the voltage value of the input signal according to the digital signal and the stored reference voltage value. The invention can accurately detect the voltage value of the CP signal and improve the communication stability.

Description

Signal detection method, computer equipment and computer readable storage medium
Technical Field
The present invention relates to the field of signal detection technologies, and in particular, to a signal detection method, a computer device, and a computer-readable storage medium.
Background
With the use of the charging automobile becoming more and more extensive, the industry chain of the upstream and the downstream is also developing vigorously at present, as an infrastructure link, the research and development and construction of the charging pile gradually enter the visual field of people, and the research of the charging protocol is the most important in order to better realize the high-efficient quick charging of the automobile.
According to filling electric pile market survey, it mainly divide into alternating-current charging stake and direct current and fills electric pile, and alternating-current charging stake uses seven hole interfaces and three hole interfaces, and direct current fills electric pile and uses nine hole interfaces. In the conventional ac charging pile, power control is performed only by a CC (connection confirm)/CP (control pilot) signal, and CC/CP signal quality control is a key to the pile communication. The general circuit is limited to be a switch circuit type, and can only detect whether the level of the CP signal meets the basic requirement or not, and cannot detect the specific voltage value of the CP signal.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a signal detection method which can accurately acquire the specific voltage value of a CP signal; the invention also provides a computer device and a computer readable storage medium.
In order to realize the purpose, the following technical scheme is adopted:
in a first aspect, the present invention further provides a signal detection method, including the following steps:
acquiring a digital signal, wherein the digital signal is generated according to an input signal and a stored reference voltage value;
and obtaining the voltage value of the input signal according to the digital signal and the stored reference voltage value.
In a second aspect, the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to make the computer device execute the steps of the foregoing method.
In a third aspect, the invention also provides a computer-readable medium having stored thereon a computer program which, when executed, carries out the aforementioned method steps.
The invention has the beneficial effects that: according to the signal detection method provided by the invention, a digital signal is obtained, and the digital signal is generated according to an input signal and a stored reference voltage value; and obtaining the voltage value of the input signal according to the digital signal and the stored reference voltage value. Therefore, the specific voltage value of the CP signal can be accurately detected, and the communication stability is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope of the present invention.
FIG. 1 is a schematic diagram of a frame structure of a signal detection circuit according to the present invention;
FIG. 2 is a schematic diagram illustrating a connection relationship of some components of a signal detection circuit according to the present invention;
fig. 3 is a schematic circuit diagram of an error amplifier of the signal detection circuit according to the present invention.
Fig. 4 is a schematic flow chart of a signal detection method according to the present invention.
Fig. 5 is a schematic flow chart of digital signal generation of a signal detection method according to the present invention.
Detailed Description
Hereinafter, various embodiments of the present invention will be described more fully. The invention is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit various embodiments of the invention to the specific embodiments disclosed herein, but on the contrary, the intention is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of various embodiments of the invention.
Hereinafter, the terms "includes" or "may include" used in various embodiments of the present invention indicate the presence of disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. Furthermore, as used in various embodiments of the present invention, the terms "comprises," "comprising," "includes," "including," "has," "having" and their derivatives are intended to mean that the specified features, numbers, steps, operations, elements, components, or combinations of the foregoing, are only meant to indicate that a particular feature, number, step, operation, element, component, or combination of the foregoing, is not to be understood as first excluding the existence of, or adding to the possibility of, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.
In various embodiments of the invention, the expression "a or/and B" includes any or all combinations of the words listed simultaneously, e.g., may include a, may include B, or may include both a and B.
Expressions (such as "first", "second", and the like) used in various embodiments of the present invention may modify various constituent elements in various embodiments, but may not limit the respective constituent elements. For example, the above description does not limit the order and/or importance of the elements described. The foregoing description is for the purpose of distinguishing one element from another. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of various embodiments of the present invention.
It should be noted that: in the present invention, unless otherwise explicitly stated or defined, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium; there may be communication between the interiors of the two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, it should be understood by those skilled in the art that the terms indicating an orientation or a positional relationship herein are based on the orientations and the positional relationships shown in the drawings and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation and operate, and thus, should not be construed as limiting the present invention.
The terminology used in the various embodiments of the present invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the present invention. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The embodiment of the invention provides a signal detection circuit, as shown in fig. 1, which includes a sampling circuit 1, a reference voltage generating circuit 2, an amplifying circuit 3, an analog-to-digital converter 4, and a processor 5, wherein an input end of the sampling circuit 1 is connected with an input end of an input signal, and an output end of the sampling circuit 1 is connected with an input end of the amplifying circuit 3, and is used for sampling the input signal; the input end of the reference voltage generating circuit 2 is connected with the input end of the input signal, the output end of the reference voltage generating circuit 2 is connected with the input end of the amplifying circuit 3, and the reference voltage generating circuit is used for outputting the reference voltage according to the reference voltage stored in the processor; the input end of the amplifying circuit 3 is connected with the output end of the sampling circuit 1 and the output end of the reference voltage generating circuit 2, and the output end of the amplifying circuit 3 is connected with the input end of the analog-to-digital converter 4 and used for subtracting and amplifying the sampled signal and the generated reference voltage; the input end of the analog-to-digital converter 4 is connected with the output end of the amplifying circuit 3, and the output end of the analog-to-digital converter 4 is connected with the input end and the output end of the processor 5 and is used for performing analog-to-digital conversion on the amplified signals; the processor 5 is configured to process the signal converted by the analog-to-digital converter to determine a level value of the input signal.
Wherein the input signal is a CP signal.
As shown in fig. 2, the sampling circuit 1 includes a first MOS transistor Q1, a first resistor R1, and a second resistor R2, the gate of the first MOS transistor Q1 is connected to the first voltage input terminal through the first resistor R1, the source of the first MOS transistor Q1 is connected to ground through the second resistor R2, the source of the first MOS transistor Q1 is further connected to the first input terminal of the amplifying circuit 3, and the drain of the first MOS transistor Q1 is connected to the CP signal input terminal.
Further, the first voltage input terminal may be the CP signal input terminal, that is, the gate of the first MOS transistor Q1 is connected to the CP signal input terminal through the first resistor R1.
Further, the sampling circuit further comprises a third resistor R3, wherein the drain of the first MOS transistor Q1 is further connected to the CP signal input terminal through the third resistor R3.
The reference voltage generating circuit 2 includes a second MOS transistor Q2 and a fourth resistor R4, a gate of the second MOS transistor Q2 is connected to the second voltage input terminal, a drain of the second MOS transistor Q2 is connected to the CP signal input terminal, a source of the second MOS transistor Q2 is connected to ground through the fourth resistor R4, and a source of the second MOS transistor Q2 is further connected to the second input terminal of the amplifying circuit 3.
Further, the reference voltage generating circuit 2 further includes a fifth resistor R5, wherein the gate of the second MOS transistor Q2 is further connected to the second voltage terminal through the fifth resistor R5.
Further, the reference voltage generating circuit 2 further includes an optocoupler U2, wherein an anode of the light emitting diode of the optocoupler U2 is connected to the CP signal input terminal, a cathode of the light emitting diode is connected to the third voltage input terminal, an emitter of the phototransistor of the optocoupler is connected to the drain of the second MOS transistor Q2, and a collector of the phototransistor is connected to the fourth voltage input terminal.
Further, the reference voltage generating circuit further includes a sixth resistor R6 and a seventh resistor R7, wherein the second voltage input terminal is connected to the emitter of the phototransistor through the sixth resistor R6, and the second voltage terminal is connected to ground through the seventh resistor R7.
Further, the reference voltage generating circuit further includes an eighth resistor R8, wherein the cathode of the light emitting diode is further connected to the third voltage input terminal through the eighth resistor R8, and the third voltage input terminal is connected to the CC signal input terminal.
Further, the reference voltage generating circuit further includes a ninth resistor R9, wherein the emitter of the phototransistor of the optocoupler U2 is further connected to the drain of the second MOS transistor through the ninth resistor R9.
Further, the reference voltage generating circuit further comprises a first capacitor C1, and the collector of the phototransistor of the optocoupler U2 is further connected to ground through the first capacitor C1.
Wherein the amplifying circuit 3 includes: an error amplifying circuit U3, a tenth input resistor R10, an eleventh input resistor R11, a twelfth resistor R12, and a thirteenth resistor R13, wherein an output end of the sampling circuit is connected to a first input end of the error amplifying circuit through the tenth resistor R10, an output end of the reference voltage generating circuit is connected to a second input end of the error amplifying circuit U3 through the eleventh resistor R11, an output end of the error amplifying circuit U3 is connected to an input end of the analog-to-digital converter 4, and the error amplifying circuit U3 subtracts and amplifies a signal output by the sampling circuit 1 and a reference voltage output by the reference voltage generating circuit 2 to output an amplified signal.
Further, as shown in fig. 3, the error amplifying circuit U3 includes a third MOS transistor Q3, a fourth MOS transistor Q4, a fifth MOS transistor Q5, a sixth MOS transistor Q6, a seventh MOS transistor Q7, and an eighth MOS transistor Q8, wherein the third MOS transistor Q3, the fourth MOS transistor Q4, the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7, and the eighth MOS transistor Q8 are disposed in theA gate of the third MOS transistor Q3 is connected to an output terminal of the reference voltage generating circuit 2, a source of the third MOS transistor Q3 is connected to a gate of the seventh MOS transistor Q7, a drain of the third MOS transistor Q3 is connected to a source of the sixth MOS transistor Q6, a gate of the sixth MOS transistor Q6 is connected to a gate of the fifth MOS transistor Q5, and a source of the fifth MOS transistor Q5 is connected to the negative power supply voltage terminal-VSSThe drain electrode of the fifth MOS transistor Q5, the drain electrode of the sixth MOS transistor Q6 and a positive power supply voltage end + V are connectedDDThe drain electrode of the seventh MOS transistor Q7 is connected with the source electrode of the third MOS transistor Q3, and the drain electrode of the seventh MOS transistor Q7 is connected with the negative power voltage terminal-VSSThe gate of the fourth MOS transistor Q4 is connected to the output terminal of the CP sampling circuit, the source of the fourth MOS transistor Q4 is connected to the drain of the eighth MOS transistor Q8, the drain of the fourth MOS transistor Q4 is connected to the source of the sixth MOS transistor Q6, the gate of the eighth MOS transistor Q8 is connected to the source of the third MOS transistor Q3, the source of the eighth MOS transistor Q8 is connected to ground, and the drain of the fourth MOS transistor Q4 is further connected to the input terminal of the analog-to-digital converter 4.
Further, the error amplifying circuit U3 further includes a ninth MOS transistor Q9 and a tenth MOS transistor Q10, wherein a gate of the ninth MOS transistor Q9 is connected to a gate of the fifth MOS transistor Q5, a source of the ninth MOS transistor Q9 is connected to a drain of the tenth MOS transistor Q10, a drain of the ninth MOS transistor Q9 is connected to the positive power voltage, a source of the tenth MOS transistor Q10 is connected to ground, and a drain of the tenth MOS transistor Q10 is further connected to the input terminal of the analog-to-digital converter 4.
Further, the amplifying circuit further includes a second capacitor C2, wherein the gate of the tenth MOS transistor Q10 is further connected to the drain of the tenth MOS transistor Q10 through the second capacitor C2.
For example, if the current voltage of the CP signal is 6.2V, the first MOS transistor Q1 is turned on, the high-precision Q1 is selected, and the voltage difference V between the source and drain of the first MOS transistor Q1 is set to be highDSIs 0.1V, if R1 is equal to R10, the output sampling voltage is VQ1-2Assuming that (6.2-0.1)/2 is 3.05V, the voltage VDD _1 at the third supply voltage input terminal is 12V, and the second MOS transistor is operated at the first MOS transistorThe voltage difference between the source and the drain is 0.1V, R2 is 3 × R12, and then the reference voltage V is obtainedQ2-2Assuming that (12-0.1) × 0.25 ═ 2.975, and assuming that R15 ═ R14 ═ R7 ═ 40 ═ R8, the amplified error signal V isU3-4The error 3V is analog-to-digital converted to obtain a digital signal, with 40 × (3.05-2.975) ═ 3V. The processor can calculate and obtain the current voltage, namely the voltage value of the input signal according to the obtained digital signal and the reverse mode of calculating the amplified error signal according to the reference voltage value and the corresponding amplification factor.
The signal detection circuit comprises a sampling circuit, a reference voltage generation circuit, an amplification circuit, an analog-to-digital converter and a processor, wherein the CP signal is sampled and a reference voltage is generated, the sampling signal and the reference voltage are subjected to error amplification, the amplified signal is subjected to analog-to-digital conversion, and the processor can accurately know the specific voltage value of the CP signal according to the digital signal and the reference voltage, so that the communication stability is improved.
Based on the first embodiment of the present invention, the second embodiment of the present invention provides a signal detection method, as shown in fig. 4, the method includes the following steps:
and S1, acquiring a digital signal, wherein the digital signal is generated according to the input signal and the stored reference voltage value.
And S2, obtaining the voltage value of the input signal according to the digital signal and the stored reference voltage value.
Specifically, as shown in fig. 5, the generating the digital signal according to the input signal and the stored reference voltage value in step S1 includes:
and S11, sampling the input signal to obtain a sampled voltage signal, and obtaining a reference voltage according to the stored reference voltage value.
Further, in order to realize the sampling of the CP signal, a control pilot signal is input to a drain of the first MOS transistor, and a control voltage is input to a gate of the first MOS transistor, specifically, the control voltage may be an input CP signal, so that the first MOS transistor works in an amplification region, and the control pilot signal is sampled by the first MOS transistor, so that the source of the first MOS transistor outputs a sampled voltage signal.
Further, the obtaining the reference voltage according to the stored reference voltage value specifically includes: inputting a second power voltage to a grid electrode of a second MOS tube to enable the second MOS tube to be in a linear amplification state, inputting a third power voltage to a drain electrode of the second MOS tube to obtain a first voltage difference between a source electrode and the drain electrode of the second MOS tube, determining a voltage division ratio of the source electrode and a drain electrode of the second MOS tube according to the stored reference voltage value, the third power voltage and the first voltage difference, and enabling the source electrode of the second MOS tube to output the reference voltage according to the control pilot signal.
Further, the causing the source of the second MOS transistor to output the reference voltage according to the control pilot signal includes: when the value of the control pilot signal is larger than zero, the drain electrode of the second MOS tube is connected with the third power supply voltage, and the source electrode of the second MOS tube outputs the reference voltage.
Further, the causing the source of the second MOS transistor to output the reference voltage according to the control pilot signal includes: and when the value of the control guide signal is greater than that of the connection confirmation signal, the drain electrode of the second MOS tube is connected with the third power voltage, and the source electrode of the second MOS tube outputs the reference voltage.
And S12, calculating the difference between the sampled voltage signal and the reference voltage, and amplifying the difference.
And S13, performing analog-to-digital conversion on the amplified difference to obtain the digital signal.
Further, the step S2 includes: obtaining an amplified error voltage value according to the digital signal; obtaining a first amplification factor of the amplified error voltage value; calculating an error voltage value before amplification according to the amplified error voltage value and the first amplification factor; and calculating the voltage value of the input signal according to the error voltage value before amplification and the stored reference voltage.
Wherein the calculating the voltage value of the input signal according to the error voltage value before amplification and the stored reference voltage comprises: calculating a sampled voltage signal according to the error voltage value before amplification and the stored reference voltage; acquiring a second amplification factor between the input voltage and the sampled voltage signal and a second voltage difference between a source electrode and a drain electrode of the first MOS tube; and calculating the voltage value of the input signal according to the sampled voltage signal, the second amplification factor and the second voltage difference value.
Wherein the calculating the sampled voltage signal according to the error voltage value before amplification and the stored reference voltage specifically includes: and calculating the sum of the error voltage value before amplification and the stored reference voltage to obtain the sampled voltage signal.
Wherein the calculating the voltage value of the input signal according to the sampled voltage signal, a second amplification factor, and the second voltage difference value comprises: calculating the product of the sampled voltage signal and the second amplification factor to obtain a first voltage signal; and calculating the sum of the first voltage signal and the second voltage difference value to obtain the voltage value of the input signal.
Based on the second embodiment of the present invention, the third embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed, implements the foregoing method steps.
Based on the second embodiment of the present invention, the fourth embodiment of the present invention provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to make the computer device execute the steps of the foregoing method.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and bus dynamic RAM (RDRAM).
The above-described embodiments are merely illustrative of several embodiments of the present invention, which are described in more detail and detail, but are not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, other various changes and modifications can be made according to the above-described technical solutions and concepts, and all such changes and modifications should fall within the protection scope of the present invention.

Claims (7)

1. A method of signal detection, comprising the steps of:
acquiring a digital signal, wherein the digital signal is generated according to an input signal and a stored reference voltage value;
obtaining a voltage value of the input signal according to the digital signal and the stored reference voltage value;
wherein generating the digital signal from the input signal and the stored reference voltage value comprises:
sampling an input signal to obtain a sampled voltage signal, and obtaining a reference voltage according to a stored reference voltage value;
calculating a difference value between the sampled voltage signal and the reference voltage, and amplifying the difference value;
performing analog-to-digital conversion on the amplified difference value to generate the digital signal;
the sampling the input signal to obtain a sampled voltage signal includes:
inputting a control guide signal into a drain electrode of a first MOS tube, sampling the control guide signal through the first MOS tube, and outputting a sampled voltage signal by a source electrode of the first MOS tube;
the obtaining of the reference voltage according to the stored reference voltage value specifically includes:
inputting a second power supply voltage to a grid electrode of a second MOS tube to enable the second MOS tube to be in a linear amplification state, inputting a third power supply voltage to a drain electrode of the second MOS tube to obtain a first voltage difference between a source electrode and the drain electrode of the second MOS tube, determining a voltage division ratio of the source electrode and the drain electrode of the second MOS tube according to the stored reference voltage value, the third power supply voltage and the first voltage difference, and outputting the reference voltage by the source electrode of the second MOS tube according to the control pilot signal;
the outputting the reference voltage by the source of the second MOS transistor according to the control pilot signal includes:
when the value of the control pilot signal is larger than zero, the drain electrode of the second MOS tube is connected with the third power supply voltage, and the source electrode of the second MOS tube outputs the reference voltage.
2. The detection method of claim 1, wherein the obtaining the voltage value of the input signal from the digital signal and a stored reference voltage value comprises:
obtaining an amplified error voltage value according to the digital signal;
obtaining a first amplification factor of the amplified error voltage value;
calculating an error voltage value before amplification according to the amplified error voltage value and the first amplification factor;
and calculating the voltage value of the input signal according to the error voltage value before amplification and the stored reference voltage value.
3. The detection method of claim 2, wherein the calculating the voltage value of the input signal from the pre-amplification error voltage value and the stored reference voltage value comprises:
calculating a sampled voltage signal according to the error voltage value before amplification and the stored reference voltage value;
acquiring a second amplification factor between the input voltage and the sampled voltage signal and a second voltage difference between the source electrode and the drain electrode of the first MOS tube;
and calculating the voltage value of the input signal according to the sampled voltage signal, the second amplification factor and the second voltage difference value.
4. The method according to claim 3, wherein the calculating the sampled voltage signal according to the pre-amplification error voltage value and the stored reference voltage value specifically comprises:
and calculating a first sum of the error voltage value before amplification and the stored reference voltage value, wherein the first sum is the sampled voltage signal.
5. The detection method of claim 4, wherein calculating the voltage value of the input signal based on the sampled voltage signal, a second amplification factor, and the second voltage difference value comprises:
calculating the product of the sampled voltage signal and the second amplification factor to obtain a first voltage signal;
and calculating a second sum of the difference value of the first voltage signal and the second voltage, wherein the second sum is the voltage value of the input signal.
6. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program realizes the method steps of any of the preceding claims when executed by a computer device.
7. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor executes the computer program to cause the computer device to perform the steps of the method according to any of claims 1 to 5.
CN201910841180.9A 2019-09-06 2019-09-06 Signal detection method, computer equipment and computer readable storage medium Active CN110696671B (en)

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