CN217954989U - Input bias current compensation circuit and oscilloscope - Google Patents
Input bias current compensation circuit and oscilloscope Download PDFInfo
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- CN217954989U CN217954989U CN202222356591.9U CN202222356591U CN217954989U CN 217954989 U CN217954989 U CN 217954989U CN 202222356591 U CN202222356591 U CN 202222356591U CN 217954989 U CN217954989 U CN 217954989U
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Abstract
The utility model discloses an input bias current compensating circuit and oscilloscope. The input bias current compensation circuit includes: the base electrode of the input transistor is used for collecting an input signal; a compensation transistor connected in series with the input transistor; a current mirror electrically connected to the base of the input transistor and electrically connected to the base of the compensation transistor; the current mirror is used for mirroring the base current of the compensation transistor to the base of the input transistor so as to compensate the base bias current of the input transistor. The embodiment of the utility model provides a through setting up compensation transistor and current mirror, compensatied the input bias current that the input transistor base produced to measuring the influence that produces, improved the measuring precision.
Description
Technical Field
The utility model relates to the technical field of circuits, especially, relate to an input bias current compensating circuit and oscilloscope.
Background
An oscilloscope is an instrument used to measure the waveform of an alternating current or a pulsed current. The device can convert an electric signal into a visible image, and the periodic physical process which can become an electric effect can be observed by an oscilloscope, so that people can conveniently research the change process of various electric phenomena.
In the prior art, the power amplification function of the oscilloscope during operation is completed by the transistor, but the diffusion and recombination of carriers in the base region of the transistor can form corresponding composite current, namely base current.
Therefore, when the transistor is used as an input transistor of an oscilloscope, an input bias current is generated, which causes the voltage of the tested point to generate offset, thereby influencing the measurement accuracy of the oscilloscope.
SUMMERY OF THE UTILITY MODEL
The utility model provides an input bias current compensating circuit and oscilloscope to the input bias current of compensation input transistor promotes oscilloscope's measurement accuracy.
According to the utility model discloses an aspect provides an input bias current compensation circuit, include:
the base electrode of the input transistor is used for collecting an input signal;
a compensation transistor connected in series with the input transistor;
a current mirror electrically connected to the base of the input transistor and electrically connected to the base of the compensation transistor; the current mirror is used for mirroring the base current of the compensation transistor to the base of the input transistor so as to compensate the base bias current of the input transistor.
Optionally, the current mirror is a mirror proportion adjustable current mirror, and the mirror proportion of the current mirror is a set value.
Optionally, the compensation transistor, the input transistor and the current mirror are integrated in the same chip.
Optionally, a distance between the compensation transistor and the input transistor is less than a preset distance.
Optionally, the input bias current compensation circuit further comprises:
an impedance isolation module connected in series between the base of the input transistor and the current mirror; the impedance isolation module is used for carrying out impedance isolation with the input end.
Optionally, the impedance isolation module comprises: a first resistor connected in series between the base of the input transistor and the current mirror;
alternatively, the impedance isolation module includes: the first current buffer is connected between the base of the input transistor and the current mirror in series, and the bias end of the first current buffer is connected with a first bias voltage.
Optionally, the input bias current compensation circuit further comprises:
the working point stabilizing module is connected between the base electrode of the compensating transistor and the current mirror in series; the working point stabilizing module is used for stabilizing direct current working points of the input transistor and the compensating transistor and carrying out impedance isolation on the input end.
Optionally, the operating point stabilizing module includes: a second resistor connected in series between the base of the compensation transistor and the current mirror;
or, the operating point stabilizing module includes: the second current buffer is connected between the base electrode of the compensation transistor and the current mirror in series, and the bias end of the second current buffer is connected with a second bias voltage;
or, the operating point stabilizing module includes: a diode connected in series between the base of the compensation transistor and the current mirror.
Optionally, the input transistor and the compensation transistor are both triodes;
the transistor adopted by the current mirror is a field effect transistor and/or a triode.
According to the utility model discloses an on the other hand provides an oscilloscope, include: the input bias current compensation circuit of any of the above embodiments; and the base electrode of the input transistor is used as the input end of the oscilloscope.
The utility model discloses technical scheme adopts the scheme of input transistor, compensation transistor and current mirror combination, and compensation transistor's base is connected with the one end of current mirror, and input transistor's base is connected with the other end of current mirror. The base current of the compensation transistor flows into a current mirror, the base current of the compensation transistor is 'copied' by the current mirror, and the 'copied' current is output to the base of the input transistor by the current mirror through the other end and is used for compensating the input bias current of the base of the input transistor. Therefore, the embodiment of the utility model provides a reduced the input bias current that the input transistor base produced to measure the influence that produces, improved the measuring precision.
It should be understood that the statements herein are not intended to identify key or critical features of any embodiment of the present invention, nor are they intended to limit the scope of the invention. Other features of the present invention will become apparent from the following description.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained without creative efforts.
Fig. 1 is a schematic structural diagram of an input bias current compensation circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another input bias current compensation circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an input bias current compensation circuit according to another embodiment of the present invention;
fig. 4 is a schematic diagram of a further input bias current compensation circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a further input bias current compensation circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an input bias current compensation circuit according to another embodiment of the present invention;
fig. 7 is a schematic diagram of an input bias current compensation circuit according to another embodiment of the present invention;
fig. 8 is a schematic diagram of another input bias current compensation circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Moreover, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of an input bias current compensation circuit according to an embodiment of the present invention. Referring to fig. 1, the input bias current compensation circuit includes:
the input transistor Q1, the base of the input transistor Q1 is used for gathering the input signal;
a compensation transistor Q2, the compensation transistor Q2 being connected in series with the input transistor Q1;
a current mirror 110, the current mirror 110 being electrically connected to the base of the input transistor Q1, and the current mirror 110 being electrically connected to the base of the compensation transistor Q2; the current mirror 110 is used to mirror the base current of the compensation transistor Q2 to the base of the input transistor Q1 to compensate the base bias current of the input transistor Q1.
Specifically, the input transistor Q1 is a detection end transistor of the oscilloscope, i.e. the base of the input transistor Q1 is used for connecting a tested point. When the input transistor Q1 operates, its base generates a small current (i.e., an input bias current) which is drawn from the tested point, thereby affecting the voltage of the tested point and affecting the measurement accuracy. The embodiment of the utility model provides a can carry out current compensation to input transistor Q1's input stage through setting up compensation transistor Q2 and current mirror 110 to compensate the influence that the extraction current produced to the measurement. The current mirror 110 is a standard component commonly found in analog integrated circuits, and is characterized by the fact that the output current is a "replica" of the input current in a certain proportion.
Optionally, the input transistor Q1 and the compensation transistor Q2 are both triodes; the transistors used by the current mirror 110 are field effect transistors and/or transistors.
For example, the principle of compensating the input bias current according to the embodiment of the present invention is: the input transistor Q1 and the compensation transistor Q2 are located in the same current path, so that when the base of the input transistor Q1 is connected to the voltage of the tested point to generate current, the compensation transistor Q2 will generate current accordingly. Similar to input transistor Q1, the base of compensation transistor Q2 also produces a smaller current that is mirrored to the base of input transistor Q1 by current mirror 110. It can be seen that there are two current paths flowing into the base of the input transistor Q1, one being the current path of the tested point and the other being the current path of the current mirror 110. Compare with the base current of input transistor Q1 among the prior art only by being provided by the test point, the embodiment of the utility model provides an increased current mirror 110 and compensated input transistor Q1's base current to reduced from the electric current by the test point extraction. In an ideal situation, when the current of the current path of the current mirror 110 is equal to the base current of the input transistor Q1, the current drawn from the tested point is 0.
Therefore, the embodiment of the invention arranges the compensation transistor Q2 and the current mirror 110 in the input bias current compensation circuit, so as to compensate the base bias current of the input transistor Q1, thereby improving the measurement accuracy.
Optionally, on the basis of the above embodiment, the current mirror 110 is a mirror proportion adjustable current mirror, and the mirror proportion of the current mirror 110 is a set value.
The current mirror 110 used in the embodiment of the present invention is a proportional adjustable current mirror, which can output a corresponding current according to a set proportion. By using the proportional adjustable current mirror, when there is a difference between the base current of the input transistor Q1 and the base current of the compensation transistor Q2, the base current of the input transistor Q1 can also be compensated by setting the proportional mirror to compensate the base current of the transistor Q2. The arrangement reduces the influence caused by the difference between the transistors, is favorable for setting the current extracted from the tested point to be 0, and further improves the accuracy of measurement.
Optionally, on the basis of the above embodiment, the compensation transistor Q2, the input transistor Q1, and the current mirror 110 are integrated in the same chip, and may be prepared in the same process, and process errors of the transistors are relatively close to each other, which is beneficial to improving process accuracy and improving measurement accuracy. Illustratively, the input transistor Q1 and the compensation transistor Q2 are transistors of the same type, and are equal in size and size, and the mirror ratio of the current mirror 110 is 1:1, can also play a better compensation effect. The arrangement can reduce the volume of the input bias current compensation circuit, so that the input bias current compensation circuit can be applied to the environment with limited space, and the use scene is expanded.
Alternatively, on the basis of the above embodiment, the distance between the compensation transistor Q2 and the input transistor Q1 is smaller than the preset distance. Specifically, the preset distance may be set as needed, so that the compensation transistor Q2 and the input transistor Q1 are located very close to each other on the chip. The arrangement is such that during chip processing, the compensation transistor Q2 and the input transistor Q1 can be in the same temperature environment, which is less affected by process fluctuation, so as to reduce the influence caused by process and temperature errors.
Fig. 2 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. Referring to fig. 2, the input bias current compensation circuit further includes:
the impedance isolation module 210, the impedance isolation module 210 is connected in series between the base of the input transistor Q1 and the current mirror 110; the impedance isolation module 210 is used for impedance isolation from the input terminal. The input impedance is the equivalent impedance of the input terminal in the circuit, and the input impedance reflects the magnitude of the current blocking effect. The impedance isolation is to connect the upper circuit and the lower circuit into impedance to isolate the two circuits and reduce the influence between the two circuits. The impedance isolation module 210 is connected in series between the current mirror 110 and the base of the input transistor Q1, which is equivalent to increasing the input impedance of the circuit, thereby performing impedance isolation. Such an arrangement can reduce the influence of the current mirror 110 on the input stage characteristics of the input transistor Q1.
Fig. 3 is a schematic diagram of an input bias current compensation circuit according to another embodiment of the present invention.
Fig. 4 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. Referring to fig. 3 and 4, the impedance isolation module 210 includes: the first resistor R1, the first resistor R1 is connected in series between the base of the input transistor Q1 and the current mirror 110.
Specifically, the input impedance is an equivalent impedance of an input terminal in the circuit, and the input impedance reflects the magnitude of the current blocking effect. The resistor acts as a barrier to current flow in the circuit and is also an impedance. A first resistor R1 is connected in series between the current mirror 110 and the base of the input transistor Q1, which is equivalent to increasing the input impedance of the circuit, thereby performing impedance isolation.
Alternatively, the impedance isolation module 210 includes: the first current buffer Q3, the first current buffer Q3 is connected in series between the base of the input transistor Q1 and the current mirror 110, and the bias terminal of the first current buffer Q3 is connected to the first bias voltage.
Specifically, the voltage difference between the source and the drain of the first current buffer Q3 is variable, and the current passing through the first current buffer Q decreases as the voltage difference increases; the current passed increases as the voltage difference decreases. Therefore, the first current buffer Q3 can be made equivalent to a resistor, and the resistance value of the equivalent resistor can be adjusted by changing the voltage difference between the source and the drain.
The embodiment of the utility model provides a through set up first resistance R1 or first current buffer Q3 between input transistor Q1 and current mirror 110, increase the impedance between input transistor Q1 and current mirror 110, reduce electric capacity and/or impedance undersize in current mirror 110 to the influence of input transistor Q1 input stage characteristic.
Fig. 5 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. Referring to fig. 5, the input bias current compensation circuit further includes:
an operating point stabilizing module 220, wherein the operating point stabilizing module 220 is connected in series between the base of the compensating transistor Q2 and the current mirror 110; the operating point stabilizing module 220 is used for stabilizing the dc operating points of the input transistor Q1 and the compensating transistor Q2.
Specifically, the dc operating point refers to a voltage between a base, a collector, and an emitter of the transistor having a predetermined relationship, and the dc operating point of the transistor can be guaranteed only when the voltages of the base, the collector, and the emitter of the transistor satisfy the predetermined relationship. For input transistor Q1, the arrangement of compensation transistor Q2 and current mirror 110 changes the collector and emitter voltages of input transistor Q1, possibly affecting its dc operating point to some extent. The embodiment of the invention can adjust the voltages of the collector and the emitter of the input transistor Q1 and the compensation transistor Q2 by arranging the working point stabilizing module, and the working points are required to be ensured to be in the safe working area of the transistors.
Illustratively, the collector voltage of the compensation transistor Q2 remains unchanged, but the base of the compensation transistor Q2 is controlled by the operating point stabilizing module 220, thereby affecting the emitter voltage of the compensation transistor Q2. Since the emitter voltage of the compensation transistor Q2 is the collector voltage of the input transistor Q1, the emitter voltage of the input transistor Q1 is the base voltage of the compensation transistor Q2 minus the base-emitter voltage of the compensation transistor Q2. Therefore, the dc operating point of the input transistor Q1 and the compensation transistor Q2 can be adjusted by the operating point stabilizing module 220. Such an arrangement can improve the operational stability of the input bias current compensation circuit.
Fig. 6 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. Fig. 7 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. Fig. 8 is a schematic structural diagram of another input bias current compensation circuit according to an embodiment of the present invention. With reference to fig. 6, 7 and 8, the operating point stabilizing module 220 includes: a second resistor R2, wherein the second resistor R2 is connected in series between the base of the compensation transistor Q2 and the current mirror 110;
alternatively, the operating point stabilization module 220 includes: a second current buffer Q4, the second current buffer Q4 is connected in series between the base of the compensation transistor Q2 and the current mirror 110, and a bias terminal of the second current buffer Q4 is connected to a second bias voltage;
alternatively, the operating point stabilizing module 220 includes: and a diode D connected in series between the base of the compensation transistor Q2 and the current mirror 110.
The embodiment of the utility model provides a set up second resistance R2 or second current buffer Q4 or diode D and undertake the partial pressure effect between compensating transistor Q2 and current mirror 110, and then change compensating transistor Q2's base voltage and direct current operating point, ensure that input transistor Q1's projecting pole is in the safe workspace of transistor, improve the job stabilization nature of input bias current compensating circuit.
The embodiment of the utility model provides a still provide an oscilloscope, this oscilloscope includes: the input bias current compensation circuit provided in any of the above embodiments; wherein, the base electrode of the input transistor Q1 is used as the input end of the oscilloscope. The oscilloscope provided by the embodiment has the beneficial effects of the input bias current compensation circuit provided by any of the above embodiments, and details are not repeated herein.
It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present invention may be executed in parallel, may be executed sequentially, or may be executed in different orders, as long as the desired result of the technical solution of the present invention can be achieved, and the present invention is not limited thereto.
The above detailed description does not limit the scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An input bias current compensation circuit, comprising:
the base of the input transistor is used for collecting an input signal;
a compensation transistor connected in series with the input transistor;
a current mirror electrically connected to the base of the input transistor and the base of the compensation transistor; the current mirror is used for mirroring the base current of the compensation transistor to the base of the input transistor so as to compensate the base bias current of the input transistor.
2. The input bias current compensation circuit of claim 1, wherein the current mirror is a mirror-ratio adjustable current mirror, and wherein a mirror ratio of the current mirror is a set value.
3. The input bias current compensation circuit of claim 1, wherein the compensation transistor, the input transistor, and the current mirror are integrated in the same chip.
4. The input bias current compensation circuit of claim 3, wherein a distance between the compensation transistor and the input transistor is less than a preset distance.
5. The input bias current compensation circuit of claim 1, further comprising:
an impedance isolation module connected in series between the base of the input transistor and the current mirror; the impedance isolation module is used for performing impedance isolation with the input end.
6. The input bias current compensation circuit of claim 5, wherein the impedance isolation module comprises: a first resistor connected in series between the base of the input transistor and the current mirror;
alternatively, the impedance isolation module includes: the first current buffer is connected between the base electrode of the input transistor and the current mirror in series, and the bias end of the first current buffer is connected with a first bias voltage.
7. The input bias current compensation circuit of claim 1, further comprising:
the working point stabilizing module is connected between the base electrode of the compensating transistor and the current mirror in series; the working point stabilizing module is used for stabilizing direct current working points of the input transistor and the compensating transistor.
8. The input bias current compensation circuit of claim 7, wherein the operating point stabilization module comprises: a second resistor connected in series between the base of the compensation transistor and the current mirror;
or, the operating point stabilizing module includes: the second current buffer is connected between the base electrode of the compensation transistor and the current mirror in series, and the bias end of the second current buffer is connected with a second bias voltage;
or, the operating point stabilizing module includes: a diode connected in series between the base of the compensation transistor and the current mirror.
9. The input bias current compensation circuit of claim 1, wherein the input transistor and the compensation transistor are both transistors;
the transistor adopted by the current mirror is a field effect transistor and/or a triode.
10. An oscilloscope, comprising: the input bias current compensation circuit of any one of claims 1-9; and the base electrode of the input transistor is used as the input end of the oscilloscope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222356591.9U CN217954989U (en) | 2022-09-05 | 2022-09-05 | Input bias current compensation circuit and oscilloscope |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222356591.9U CN217954989U (en) | 2022-09-05 | 2022-09-05 | Input bias current compensation circuit and oscilloscope |
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| Publication Number | Publication Date |
|---|---|
| CN217954989U true CN217954989U (en) | 2022-12-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222356591.9U Active CN217954989U (en) | 2022-09-05 | 2022-09-05 | Input bias current compensation circuit and oscilloscope |
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| CN (1) | CN217954989U (en) |
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2022
- 2022-09-05 CN CN202222356591.9U patent/CN217954989U/en active Active
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