CN110690287B - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN110690287B
CN110690287B CN201910593346.XA CN201910593346A CN110690287B CN 110690287 B CN110690287 B CN 110690287B CN 201910593346 A CN201910593346 A CN 201910593346A CN 110690287 B CN110690287 B CN 110690287B
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China
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pattern
ferroelectric
active
semiconductor device
gate
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CN201910593346.XA
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CN110690287A (zh
Inventor
任廷爀
金完敦
金元洪
朴锺昊
白贤俊
李炳训
玄尚镇
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020190005362A external-priority patent/KR102554708B1/ko
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
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Abstract

本公开提供了半导体器件。一种半导体器件包括：基板，包括第一有源区域和第二有源区域；第一有源图案和第二有源图案，分别设置在第一有源区域和第二有源区域中；第一栅电极和第二栅电极，分别交叉第一有源图案和第二有源图案；第一栅极绝缘图案，插设在第一有源图案和第一栅电极之间；以及第二栅极绝缘图案，插设在第二有源图案和第二栅电极之间。第一栅极绝缘图案包括第一电介质图案和设置在第一电介质图案上的第一铁电图案。第二栅极绝缘图案包括第二电介质图案。第一有源区域中的晶体管的阈值电压不同于第二有源区域中的晶体管的阈值电压。

Description

半导体器件
技术领域
本发明构思的示范性实施方式涉及一种半导体器件，更具体地，涉及包括场效应晶体管的半导体器件以及制造该半导体器件的方法。
背景技术
半导体器件包括集成电路，该集成电路包括金属氧化物半导体场效应晶体管(MOSFET)。为了满足对具有小图案尺寸小和减小的设计规则的半导体器件的日益增长的需求，MOSFET可以按比例缩小。然而，使MOSFET按比例缩小会导致半导体器件的操作性能的变差。
发明内容
本发明构思的示范性实施方式提供包括具有不同阈值电压的晶体管的半导体器件。
根据本发明构思的一示范性实施方式，一种半导体器件包括：基板，包括第一有源区域和第二有源区域；第一有源图案和第二有源图案，分别设置在第一有源区域和第二有源区域中；第一栅电极和第二栅电极，分别交叉第一有源图案和第二有源图案；以及插设在第一有源图案和第一栅电极之间的第一栅极绝缘图案和插设在第二有源图案和第二栅电极之间的第二栅极绝缘图案。第一栅极绝缘图案包括第一电介质图案和设置在第一电介质图案上的第一铁电图案，第二栅极绝缘图案包括第二电介质图案。第一有源区域中的晶体管的阈值电压不同于第二有源区域中的晶体管的阈值电压。
根据本发明构思的示范性实施方式，一种半导体器件包括：基板，包括第一有源区域和第二有源区域；第一有源图案和第二有源图案，分别设置在第一有源区域和第二有源区域中；第一栅电极和第二栅电极，分别交叉第一有源图案和第二有源图案；以及插设在第一有源图案和第一栅电极之间的第一栅极绝缘图案和插设在第二有源图案和第二栅电极之间的第二栅极绝缘图案。第一栅极绝缘图案包括第一电介质图案和设置在第一电介质图案上的第一铁电图案，第二栅极绝缘图案包括第二电介质图案和设置在第二电介质图案上的第二铁电图案。第一铁电图案在铁电材料、杂质浓度和厚度中的至少一个上不同于第二铁电图案。
根据本发明构思的一示范性实施方式，一种半导体器件包括：基板，包括第一有源区域和第二有源区域；第一有源图案和第二有源图案，分别设置在第一有源区域和第二有源区域中；第一栅电极和第二栅电极，分别交叉第一有源图案和第二有源图案；栅极间隔物，设置在第一栅电极和第二栅电极的每个的侧表面上；第一电介质图案和第一铁电图案，插设在第一栅电极和栅极间隔物之间；以及第二电介质图案，插设在第二栅电极和栅极间隔物之间。
附图说明
通过参照附图详细描述本发明构思的示范性实施方式，本发明构思的以上和其它的特征将变得更加明显，附图中：
图1是示出根据本发明构思的一示范性实施方式的半导体器件的平面图。
图2A是沿着图1的线A-A'和B-B'剖取的截面图。
图2B是沿着图1的线C-C'和D-D'剖取的截面图。
图2C是沿着图1的线E-E'剖取的截面图。
图2D是沿着图1的线F-F'剖取的截面图。
图3、图5、图7和图9是示出根据本发明构思的一示范性实施方式的制造半导体器件的方法的平面图。
图4、图6A和图8A是分别沿着图3、图5和图7的线A-A'剖取的截面图。
图6B和图8B是分别沿着图5和图7的线B-B'剖取的截面图。
图6C和图8C是分别沿着图5和图7的线C-C'剖取的截面图。
图10A是沿着图9的线A-A'和B-B'剖取的截面图。
图10B是沿着图9的线C-C'和D-D'剖取的截面图。
图10C是沿着图9的线E-E'剖取的截面图。
图10D是沿着图9的线F-F'剖取的截面图。
图11至图15是截面图，其每个沿着图1的线A-A'和B-B'剖取，并示出根据本发明构思的一示范性实施方式的半导体器件。
图16是示出根据本发明构思的一示范性实施方式的半导体器件的平面图。
图17A是沿着图16的线A-A'和B-B'剖取的截面图。
图17B是沿着图16的线C-C'剖取的截面图。
图17C是沿着图16的线D-D'剖取的截面图。
具体实施方式
下面将参照附图更全面地描述本发明构思的示范性实施方式。相同的附图标记可以在整个附图中表示相同的元件。
为了便于描述，这里可以使用空间关系术语诸如“在……之下”、“在……下面”、“下”、“在……下方”、“在……之上”、“上”等来描述如附图所示的一个元件和特征与另一个(些)元件或特征的关系。将理解，空间关系术语旨在涵盖除了附图所示的取向之外装置在使用或操作中的不同取向。例如，如果附图中的装置被翻转过来，被描述为在其它元件或特征“下面”或“之下”或“下方”的元件将于是取向在其它元件或特征“之上”。因此，示范性术语“在……下面”和“在……之下”可以涵盖之上和之下两种取向。此外，还将理解，当一层被称为在两个层“之间”时，它可以是这两个层之间的唯一的层，或者还可以存在一个或更多个插入的层。此外，还将理解，当一元件被称为“覆盖”另一元件时，它可以是覆盖该另一元件的唯一元件，或者一个或更多个插入的元件也可以覆盖该另一元件。
图1是示出根据本发明构思的一示范性实施方式的半导体器件的平面图。图2A是沿着图1的线A-A'和B-B'剖取的截面图。图2B是沿着图1的线C-C'和D-D'剖取的截面图。图2C是沿着图1的线E-E'剖取的截面图。图2D是沿着图1的线F-F'剖取的截面图。
参照图1和图2A至图2D，可以提供基板100，基板100包括第一PMOSFET区域PR1、第二PMOSFET区域PR2、第一NMOSFET区域NR1和第二NMOSFET区域NR2。基板100可以是基于IV族元素的半导体基板(例如硅、锗或硅锗的半导体基板)或化合物半导体基板。作为示例，基板100可以是硅晶片。
在一示范性实施方式中，第一PMOSFET区域PR1和第二PMOSFET区域PR2以及第一NMOSFET区域NR1和第二NMOSFET区域NR2中的每个可以是逻辑单元区域，其上集成构成半导体器件的逻辑电路的逻辑晶体管。作为示例，构成逻辑电路的逻辑晶体管可以设置在基板100的逻辑单元区域中。第一PMOSFET区域PR1和第二PMOSFET区域PR2以及第一NMOSFET区域NR1和第二NMOSFET区域NR2可以包括所述逻辑晶体管中的一些。
将理解，这里使用术语“第一”、“第二”、“第三”等以将一个元件与另一元件区别开，这些元件不受这些术语限制。因此，在一示范性实施方式中的“第一”元件可以在另一个示范性实施方式中被描述为“第二”元件。
第二沟槽TR2可以形成在基板100的上部中以限定第一PMOSFET区域PR1和第二PMOSFET区域PR2以及第一NMOSFET区域NR1和第二NMOSFET区域NR2。第二沟槽TR2可以位于第一PMOSFET区域PR1和第一NMOSFET区域NR1之间以及第二PMOSFET区域PR2和第二NMOSFET区域NR2之间。第一PMOSFET区域PR1和第一NMOSFET区域NR1可以在第一方向D1上彼此间隔开而使第二沟槽TR2插设在其间。第二PMOSFET区域PR2和第二NMOSFET区域NR2可以在第一方向D1上彼此间隔开而使第二沟槽TR2插设在其间。第一PMOSFET区域PR1和第二PMOSFET区域PR2可以在第二方向D2上彼此间隔开。第一NMOSFET区域NR1和第二NMOSFET区域NR2可以在第二方向D2上彼此间隔开。
第一有源图案AP1可以提供在第一PMOSFET区域PR1和第二PMOSFET区域PR2上。第二有源图案AP2可以提供在第一NMOSFET区域NR1和第二NMOSFET区域NR2上。第一PMOSFET区域PR1和第二PMOSFET区域PR2以及第一NMOSFET区域NR1和第二NMOSFET区域NR2也可以在这里被称为有源区域。因此，第一有源图案AP1和第二有源图案AP2可以被描述为设置在有源区域中。第一有源图案AP1和第二有源图案AP2可以在第二方向D2上延伸。第一有源图案AP1和第二有源图案AP2可以为基板100的具有竖直突出形状的部分。第一沟槽TR1可以被限定在相邻的第一有源图案AP1之间以及在相邻的第二有源图案AP2之间。第一沟槽TR1可以比第二沟槽TR2浅。
器件隔离层ST可以被提供来填充第一沟槽TR1和第二沟槽TR2。器件隔离层ST可以包括例如硅氧化物层。第一有源图案AP1的上部和第二有源图案AP2的上部可以具有在器件隔离层ST之上竖直突出的形状(例如见图2C)。第一有源图案AP1的上部和第二有源图案AP2的上部中的每个可以具有鳍形状。在一示范性实施方式中，器件隔离层ST不覆盖第一有源图案AP1的上部和第二有源图案AP2的上部。器件隔离层ST可以覆盖第一有源图案AP1的下部侧表面和第二有源图案AP2的下部侧表面。
第一源极/漏极图案SD1可以提供在第一有源图案AP1的上部上。第一源极/漏极图案SD1可以为第一导电类型(例如p型)的杂质区域。第一沟道区域CH1可以插设在每对第一源极/漏极图案SD1之间。第二源极/漏极图案SD2可以提供在第二有源图案AP2的上部上。第二源极/漏极图案SD2可以为第二导电类型(例如n型)的杂质区域。第二沟道区域CH2可以插设在每对第二源极/漏极图案SD2之间。
在一示范性实施方式中，第一源极/漏极图案SD1可以具有p型导电性，第二源极/漏极图案SD2可以具有n型导电性。在另一个示范性实施方式中，第一源极/漏极图案SD1可以具有n型导电性，第二源极/漏极图案SD2可以具有p型导电性。
第一源极/漏极图案SD1和第二源极/漏极图案SD2可以是通过选择性外延生长工艺形成的外延图案。第一源极/漏极图案SD1和第二源极/漏极图案SD2可以具有位于比第一沟道区域CH1的顶表面和第二沟道区域CH2的顶表面高的水平面处的顶表面。例如，如图2A和图2B所示，在一示范性实施方式中，从基板100的顶表面到第一源极/漏极图案SD1的顶表面的距离可以大于从基板100的顶表面到第一沟道区域CH1的顶表面的距离。类似的空间关系可以存在于第二源极/漏极图案SD2和第二沟道区域CH2之间。在一示范性实施方式中，第一源极/漏极图案SD1可以包括具有比基板100的晶格常数大的晶格常数的半导体材料(例如SiGe)。在此情况下，第一源极/漏极图案SD1可以向第一沟道区域CH1施加压应力。在一示范性实施方式中，第二源极/漏极图案SD2可以包括与基板100的半导体材料相同的半导体材料(例如Si)。
第一栅电极GE1和第二栅电极GE2可以被提供为交叉第一有源图案AP1和第二有源图案AP2并在第一方向D1上延伸。例如，如图1所示，第一有源图案AP1和第二有源图案AP2可以在第二方向D2上纵向地延伸，并且第一栅电极GE1和第二栅电极GE2可以在第一方向D1上纵向地延伸使得它们交叉第一有源图案AP1和第二有源图案AP2。第一栅电极GE1可以跨越第一PMOSFET区域PR1和第一NMOSFET区域NR1。第二栅电极GE2可以跨越第二PMOSFET区域PR2和第二NMOSFET区域NR2。第一栅电极GE1和第二栅电极GE2可以在第二方向D2上彼此间隔开。
第一栅电极GE1和第二栅电极GE2中的每个可以与第一沟道区域CH1和第二沟道区域CH2竖直地重叠。第一栅电极GE1和第二栅电极GE2中的每个可以被提供为面对第一沟道区域CH1和第二沟道区域CH2中的每个的顶表面和相反的侧表面(例如见图2C)。
一对栅极间隔物GS可以分别设置在第一栅电极GE1和第二栅电极GE2中的每个的相反的侧表面上。栅极间隔物GS可以沿着第一栅电极GE1和第二栅电极GE2且在第一方向D1上延伸。栅极间隔物GS的顶表面可以高于第一栅电极GE1的顶表面和第二栅电极GE2的顶表面。例如，在一示范性实施方式中，栅极间隔物GS的顶表面和基板100的顶表面之间的距离可以大于第一栅电极GE1和第二栅电极GE2的顶表面和基板100的顶表面之间的距离。栅极间隔物GS的顶表面可以与将在下面描述的第一层间绝缘层110的顶表面是共平面的。例如，栅极间隔物GS的顶表面可以与第一层间绝缘层110的顶表面基本上对齐。栅极间隔物GS可以由例如SiCN、SiCON和SiN中的至少一种形成，或包括例如SiCN、SiCON和SiN中的至少一种。在示范性实施方式中，栅极间隔物GS可以具有多层结构，该多层结构包括例如SiCN、SiCON和SiN层中的至少两个。
栅极覆盖图案GP可以分别提供在第一栅电极GE1和第二栅电极GE2上。栅极覆盖图案GP可以沿着第一栅电极GE1和第二栅电极GE2且在第一方向D1上延伸。栅极覆盖图案GP可以由被选择为相对于下面描述的第一层间绝缘层110和第二层间绝缘层120具有蚀刻选择性的材料中的至少一种形成，或包括被选择为相对于下面描述的第一层间绝缘层110和第二层间绝缘层120具有蚀刻选择性的材料中的至少一种。例如，栅极覆盖图案GP可以由SiON、SiCN、SiCON和SiN中的至少一种形成，或包括SiON、SiCN、SiCON和SiN中的至少一种。
第一栅极绝缘图案GI1可以插设在第一栅电极GE1和第一有源图案AP1之间以及在第一栅电极GE1和第二有源图案AP2之间。第一栅极绝缘图案GI1可以插设在第一栅电极GE1和栅极间隔物GS之间。第二栅极绝缘图案GI2可以插设在第二栅电极GE2和第一有源图案AP1之间以及在第二栅电极GE2和第二有源图案AP2之间。第二栅极绝缘图案GI2可以插设在第二栅电极GE2和栅极间隔物GS之间。
第一栅极绝缘图案GI1和第二栅极绝缘图案GI2可以分别在第一栅电极GE1的底表面和第二栅电极GE2的底表面处延伸。第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以覆盖第一沟道区域CH1的顶表面和相反的侧表面。第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以覆盖第二沟道区域CH2的顶表面和相反的侧表面。第一栅极绝缘图案GI1和第二栅极绝缘图案GI2可以覆盖器件隔离层ST的顶表面，该器件隔离层ST提供在第一栅电极GE1和第二栅电极GE2下面(例如见图2C)。
第一栅极绝缘图案GI1可以包括电介质图案DE和设置在电介质图案DE上的铁电图案FE。铁电图案FE的厚度可以大于或大约等于电介质图案DE的厚度。
根据本发明构思的一示范性实施方式，电介质图案DE可以用作正电容器。电介质图案DE可以包括例如硅氧化物层、高k电介质层、或其中顺序堆叠硅氧化物层和高k电介质层的多层结构。作为示例，高k电介质层可以由铪氧化物、铪硅氧化物、镧氧化物、锆氧化物、锆硅氧化物、钽氧化物、钛氧化物、钡锶钛氧化物、钡钛氧化物、锶钛氧化物、锂氧化物、铝氧化物、铅钪钽氧化物和铌酸铅锌中的至少一种形成，或包括上述材料中的至少一种。
在一示范性实施方式中，铁电图案FE可以用作负电容器。例如，当外部电压施加到铁电图案FE时，由于铁电图案FE中的偶极子的运动，铁电图案FE的相可以改变为与其初始极化状态不同的状态，因此可以发生负电容效应。在此情况下，包括铁电图案FE的晶体管的总电容可以增大。结果，在一示范性实施方式中，可以改善晶体管的亚阈值摆动特性，并可以减小操作电压。
铁电图案FE可以包括包含例如锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种的铪氧化物。铁电图案FE可以包括掺杂有例如锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种的铪氧化物。在铪氧化物以特定的比率掺杂有锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种的情况下，铁电图案FE的至少一部分可以具有正交晶体结构。当铁电图案FE的至少一部分具有正交晶体结构时，可以发生负电容效应。具有正交晶体结构的部分的体积与铁电图案FE的总体积的体积比可以在从约10％至约50％的范围内。
如这里使用的术语“约”是包括所述值的并表示在如本领域普通技术人员所确定的对于特定值的可接受偏差范围内，考虑到所讨论的测量和与特定量的测量相关的误差(例如测量系统的限制)。例如，“约”可以表示在如本领域普通技术人员所理解的一个或多个标准偏差内。此外，将理解，根据示范性实施方式，当参数可以在这里被描述为具有“约”特定值时，该参数可以正好是该特定值、或在本领域普通技术人员将理解的测量误差内大致为该特定值。
在铁电图案FE包括锆掺杂的铪氧化物(ZrHfO)的情况下，Zr原子的数量与Zr和Hf原子的数量的比例(例如Zr/(Hf+Zr))可以在从约45at％至约55at％的范围内。在铁电图案FE包括硅掺杂的铪氧化物(SiHfO)的情况下，Si原子的数量与Si和Hf原子的数量的比例(例如Si/(Hf+Si))可以在从约4at％至约6at％的范围内。在铁电图案FE包括铝掺杂的铪氧化物(AlHfO)的情况下，Al原子的数量与Al和Hf原子的数量的比例(例如Al/(Hf+Al))可以在从约5at％至约10at％的范围内。在铁电图案FE包括镧掺杂的铪氧化物(LaHfO)的情况下，La原子的数量与La和Hf原子的数量的比例(例如La/(Hf+La))可以在从约5at％至约10at％的范围内。
在一示范性实施方式中，第一栅极绝缘图案GI1包括电介质图案DE和铁电图案FE两者，第二栅极绝缘图案GI2包括电介质图案DE而不包括铁电图案FE。例如，在一示范性实施方式中，第二栅极绝缘图案GI2仅由电介质图案DE形成，而不包括铁电图案FE(或者任何其它的铁电材料)。
第一栅电极GE1和第二栅电极GE2中的每个可以包括顺序堆叠的第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL。第一功函数金属图案WF1可以提供在铁电图案FE上。例如，铁电图案FE可以插设在第一功函数金属图案WF1与第一沟道区域CH1和第二沟道区域CH2之间。
第一功函数金属图案WF1可以包括金属氮化物层(例如钛氮化物层(TiN)或钽氮化物层(TaN))。第二功函数金属图案WF2可以包括金属碳化物层，其包括铝或硅、或掺杂有铝或硅。作为示例，第二功函数金属图案WF2可以包括TiAlC、TaAlC、TiSiC或TaSiC。电极图案EL可以具有比第一功函数金属图案WF1和第二功函数金属图案WF2低的电阻。作为示例，电极图案EL可以包括低电阻金属中的至少一种，该低电阻金属包括铝(Al)、钨(W)、钛(Ti)和钽(Ta)。
图2A所示的在第一PMOSFET区域PR1和第二PMOSFET区域PR2上的第一功函数金属图案WF1的厚度可以大于图2B所示的在第一NMOSFET区域NR1和第二NMOSFET区域NR2上的第一功函数金属图案WF1的厚度。图2B所示的在第一NMOSFET区域NR1和第二NMOSFET区域NR2上的第二功函数金属图案WF2的厚度可以大于图2A所示的在第一PMOSFET区域PR1和第二PMOSFET区域PR2上的第二功函数金属图案WF2的厚度。
第一层间绝缘层110可以提供在基板100上。第一层间绝缘层110可以覆盖栅极间隔物GS以及第一源极/漏极图案SD1和第二源极/漏极图案SD2。第一层间绝缘层110的顶表面可以与栅极覆盖图案GP的顶表面和栅极间隔物GS的顶表面基本上共平面。例如，第一层间绝缘层110的顶表面、栅极覆盖图案GP的顶表面和栅极间隔物GS的顶表面可以基本上彼此对齐。第二层间绝缘层120可以设置在第一层间绝缘层110上并可以覆盖栅极覆盖图案GP。作为示例，第一层间绝缘层110和第二层间绝缘层120可以包括硅氧化物。
有源接触AC可以提供在第一栅电极GE1和第二栅电极GE2中的每个的两侧并与第一栅电极GE1和第二栅电极GE2中的每个相邻。有源接触AC可以穿透第一层间绝缘层110和第二层间绝缘层120，并可以电连接到第一源极/漏极图案SD1和第二源极/漏极图案SD2。有源接触AC可以包括金属材料(例如铝、铜、钨、钼和钴)中的至少一种。
金属硅化物层可以插设在第一源极/漏极图案SD1和第二源极/漏极图案SD2与有源接触AC之间。有源接触AC可以通过金属硅化物层电连接到第一源极/漏极图案SD1和第二源极/漏极图案SD2。金属硅化物层可以包括金属硅化物材料中的至少一种，所述金属硅化物材料包括例如钛硅化物、钽硅化物、钨硅化物、镍硅化物和钴硅化物。
栅极接触GC可以穿透第二层间绝缘层120和栅极覆盖图案GP，并可以电连接到第一栅电极GE1和第二栅电极GE2。栅极接触GC可以包括与有源接触AC相同的金属材料。
根据本发明构思的一示范性实施方式，铁电图案FE可以提供在栅电极(例如GE1、GE2)和沟道区域(例如CH1、CH2)之间。铁电图案FE可以包括正交晶体结构，引起负电容效应。结果，可以改善晶体管的亚阈值摆动特性，并可以降低晶体管的操作电压。
根据本发明构思的一示范性实施方式，第二栅极绝缘图案GI2可以仅包括电介质图案DE，第一栅极绝缘图案GI1可以包括电介质图案DE以及铁电图案FE。因此，第一PMOSFET区域PR1上的晶体管的阈值电压可以不同于第二PMOSFET区域PR2上的晶体管的阈值电压。第一NMOSFET区域NR1上的晶体管的阈值电压可以不同于第二NMOSFET区域NR2上的晶体管的阈值电压。通过从区域到区域不同地提供构成栅极绝缘图案的层，可以实现从区域到区域的晶体管的阈值电压的差异。
图3、图5、图7和图9是示出根据本发明构思的一示范性实施方式的制造半导体器件的方法的平面图。图4、图6A和图8A是分别沿着图3、图5和图7的线A-A'剖取的截面图。图6B和图8B是分别沿着图5和图7的线B-B'剖取的截面图。图6C和图8C是分别沿着图5和图7的线C-C'剖取的截面图。图10A是沿着图9的线A-A'和B-B'剖取的截面图。图10B是沿着图9的线C-C'和D-D'剖取的截面图。图10C是沿着图9的线E-E'剖取的截面图。图10D是沿着图9的线F-F'剖取的截面图。
参照图3和图4，可以提供包括第一PMOSFET区域PR1、第二PMOSFET区域PR2、第一NMOSFET区域NR1和第二NMOSFET区域NR2的基板100。第一有源图案AP1和第二有源图案AP2可以通过图案化基板100而形成。第一有源图案AP1可以形成在第一PMOSFET区域PR1和第二PMOSFET区域PR2上，第二有源图案AP2可以形成在第一NMOSFET区域NR1和第二NMOSFET区域NR2上。第一沟槽TR1可以形成在第一有源图案AP1之间以及在第二有源图案AP2之间。
基板100可以被图案化以在第一PMOSFET区域PR1和第一NMOSFET区域NR1之间以及在第二PMOSFET区域PR2和第二NMOSFET区域NR2之间形成第二沟槽TR2。第二沟槽TR2可以形成得比第一沟槽TR1深。
器件隔离层ST可以形成在基板100上以填充第一沟槽TR1和第二沟槽TR2。器件隔离层ST可以包括绝缘材料(例如硅氧化物层)。器件隔离层ST可以凹陷以暴露第一有源图案AP1的上部和第二有源图案AP2的上部。结果，第一有源图案AP1的上部和第二有源图案AP2的上部可以具有竖直突出在器件隔离层ST之上的形状。
参照图5和图6A至图6C，第一牺牲图案PP1和第二牺牲图案PP2可以形成为交叉第一有源图案AP1和第二有源图案AP2。第一牺牲图案PP1可以交叉第一PMOSFET区域PR1和第一NMOSFET区域NR1，第二牺牲图案PP2可以交叉第二PMOSFET区域PR2和第二NMOSFET区域NR2。第一牺牲图案PP1和第二牺牲图案PP2可以形成为具有在第一方向D1上延伸的线状或条状。例如，如图5所示，第一牺牲图案PP1和第二牺牲图案PP2可以具有在第一方向D1上延伸的基本上直线形状。
第一牺牲图案PP1和第二牺牲图案PP2的形成可以包括：在基板100上形成牺牲层；在牺牲层上形成硬掩模图案MA；以及采用硬掩模图案MA作为蚀刻掩模图案化牺牲层。牺牲层可以包括例如多晶硅层。
一对栅极间隔物GS可以分别形成在第一牺牲图案PP1和第二牺牲图案PP2中的每个的相反的侧表面上。栅极间隔物GS也可以形成在第一有源图案AP1和第二有源图案AP2中的每个的相反的侧表面上。第一有源图案AP1和第二有源图案AP2中的每个的相反的侧表面可以是没有被器件隔离层ST以及第一和第二牺牲图案PP1和PP2覆盖的表面。例如，第一有源图案AP1和第二有源图案AP2中的每个的相反的侧表面可以被暴露。
栅极间隔物GS的形成可以包括在基板100上共形地形成栅极间隔物层以及各向异性蚀刻该栅极间隔物层。栅极间隔物层可以包括例如SiCN、SiCON和SiN中的至少一种。在一示范性实施方式中，栅极间隔物层可以是多层结构，该多层结构包括例如SiCN、SiCON和SiN层中的至少两个。
参照图7和图8A至图8C，第一源极/漏极图案SD1可以形成在第一有源图案AP1的每个的上部处或中。一对第一源极/漏极图案SD1可以形成在第一牺牲图案PP1和第二牺牲图案PP2中的每个的两侧。
例如，第一凹陷区域可以通过采用硬掩模图案MA和栅极间隔物GS作为蚀刻掩模蚀刻第一有源图案AP1的上部而形成。每个第一有源图案AP1的相反的侧表面上的栅极间隔物GS可以在第一有源图案AP1的上表面的蚀刻期间被去除。第一有源图案AP1之间的器件隔离层ST可以在第一有源图案AP1的上部的蚀刻期间凹陷。
可以执行选择性外延生长工艺(其中第一有源图案AP1的第一凹陷区域的内侧壁用作籽晶层)以形成第一源极/漏极图案SD1。作为形成第一源极/漏极图案SD1的结果，第一沟道区域CH1可以限定在每对第一源极/漏极图案SD1之间。作为示例，选择性外延生长工艺可以包括化学气相沉积(CVD)工艺或分子束外延(MBE)工艺。第一源极/漏极图案SD1可以包括具有比基板100的晶格常数大的晶格常数的半导体材料(例如SiGe)。每个第一源极/漏极图案SD1可以由多个半导体层形成。
作为示例，在选择性外延生长工艺期间，第一源极/漏极图案SD1可以原位掺杂有杂质。作为另一个示例，在形成第一源极/漏极图案SD1之后，杂质可以被注入到第一源极/漏极图案SD1中。第一源极/漏极图案SD1可以被掺杂为具有第一导电类型(例如p型)。
第二源极/漏极图案SD2可以形成在每个第二有源图案AP2的上部处或中。一对第二源极/漏极图案SD2可以形成在第一牺牲图案PP1和第二牺牲图案PP2中的每个的两侧。
例如，第二凹陷区域可以通过采用硬掩模图案MA和栅极间隔物GS作为蚀刻掩模蚀刻第二有源图案AP2的上部而形成。可以执行选择性外延生长工艺(其中第二有源图案AP2的第二凹陷区域的内侧壁用作籽晶层)以形成第二源极/漏极图案SD2。作为形成第二源极/漏极图案SD2的结果，第二沟道区域CH2可以限定在每对第二源极/漏极图案SD2之间。在一示范性实施方式中，第二源极/漏极图案SD2可以包括与基板100的半导体材料相同的半导体材料(例如Si)。第二源极/漏极图案SD2可以被掺杂为具有第二导电类型(例如n型)。
第一源极/漏极图案SD1和第二源极/漏极图案SD2可以通过不同的工艺顺序地形成。例如，第一源极/漏极图案SD1和第二源极/漏极图案SD2可以不是基本上同时形成。
参照图9和图10A至图10D，第一层间绝缘层110可以形成为覆盖第一源极/漏极图案SD1和第二源极/漏极图案SD2、硬掩模图案MA和栅极间隔物GS。作为示例，第一层间绝缘层110可以包括硅氧化物层。
第一层间绝缘层110可以被平坦化以暴露第一牺牲图案PP1的顶表面和第二牺牲图案PP2的顶表面。第一层间绝缘层110的平坦化可以采用例如回蚀刻或化学机械抛光(CMP)工艺进行。在平坦化工艺期间，可以去除全部硬掩模图案MA。结果，第一层间绝缘层110可以具有与第一牺牲图案PP1的顶表面和第二牺牲图案PP2的顶表面以及栅极间隔物GS的顶表面基本上共平面的顶表面。例如，在一示范性实施方式中，第一层间绝缘层110的顶表面、第一牺牲图案PP1的顶表面和第二牺牲图案PP2的顶表面以及栅极间隔物GS的顶表面可以基本上彼此对齐。
第一牺牲图案PP1和第二牺牲图案PP2可以分别用第一栅电极GE1和第二栅电极GE2置换。例如，暴露的第一牺牲图案PP1和第二牺牲图案PP2可以被选择性去除，并且作为去除第一牺牲图案PP1和第二牺牲图案PP2的结果可以分别形成第一空的空间ET1和第二空的空间ET2。
第一栅极绝缘图案GI1和第一栅电极GE1可以形成在第一空的空间ET1中。第一栅极绝缘图案GI1的形成可以包括顺序地形成电介质图案DE和铁电图案FE以部分地填充第一空的空间ET1。电介质图案DE可以包括例如硅氧化物层、高k电介质层或多层结构，在该多层结构中硅氧化物层和高k电介质层被顺序地堆叠。铁电图案FE可以包括由铪氧化物形成或包括铪氧化物，该铪氧化物包括锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种或者掺杂有锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种。第一栅电极GE1的形成可以包括在铁电图案FE上顺序地形成第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL。
第二栅极绝缘图案GI2和第二栅电极GE2可以形成在第二空的空间ET2中。第二栅极绝缘图案GI2的形成可以包括形成电介质图案DE以部分地填充第二空的空间ET2。第二栅电极GE2的形成可以包括在电介质图案DE上顺序地形成第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL。
在第一空的空间ET1和第二空的空间ET2中分别形成第一栅电极GE1和第二栅电极GE2之后，可以执行平坦化工艺以暴露第一层间绝缘层110的顶表面。
返回参照图1和图2A至图2D，第二层间绝缘层120可以形成在第一层间绝缘层110上。第二层间绝缘层120可以包括例如硅氧化物层或低k氧化物层。作为示例，低k氧化物可以包括碳掺杂的硅氧化物层，例如SiCOH。第二层间绝缘层120可以例如通过CVD工艺形成。
有源接触AC可以形成为穿透第二层间绝缘层120和第一层间绝缘层110，并可以电连接到第一源极/漏极图案SD1和第二源极/漏极图案SD2。栅极接触GC可以穿透第二层间绝缘层120和栅极覆盖图案GP，并可以电连接到第一栅电极GE1和第二栅电极GE2。
图11至图15是截面图，其每个是沿着图1的线A-A'和B-B'剖取，并示出根据本发明构思的一示范性实施方式的半导体器件。在下面的描述中，之前参照图1和图2A至图2D描述的元件可以由相同的附图标记表示，并且为了说明的便利，可以省略其进一步的描述。
参照图1和图11，第一功函数金属图案WF1的上部可以被切角，使得第一功函数金属图案WF1具有比电极图案EL的顶表面ELt低的顶表面WF1t。例如，基板100的顶表面和第一功函数金属图案WF1的顶表面WF1t之间的距离可以小于基板100的顶表面和电极图案EL的顶表面ELt之间的距离。第二功函数金属图案WF2可以覆盖第一功函数金属图案WF1的顶表面WF1t。第一功函数金属图案WF1的上部的切角可以导致电极图案EL的上部的宽度的增大。
参照图1和图12，第一栅极绝缘图案GI1可以包括电介质图案DE和第一铁电图案FE1，第二栅极绝缘图案GI2可以包括电介质图案DE和第二铁电图案FE2。
第一铁电图案FE1和第二铁电图案FE2可以包括不同的铁电材料。作为示例，第一铁电图案FE1可以包括锆掺杂的铪氧化物，第二铁电图案FE2可以包括铝掺杂的铪氧化物。
在一示范性实施方式中，第一铁电图案FE1和第二铁电图案FE2可以包括相同的铁电材料。然而，第一铁电图案FE1的杂质浓度可以不同于第二铁电图案FE2的杂质浓度。作为示例，第一铁电图案FE1和第二铁电图案FE2可以包括锆掺杂的铪氧化物，并且在此情况下，第一铁电图案FE1的Zr/(Hf+Zr)的比例可以为约45at％，第二铁电图案FE2的Zr/(Hf+Zr)的比例可以为约55at％。
第一铁电图案FE1和第二铁电图案FE2可以具有基本上相同的厚度。例如，第一铁电图案FE1的厚度和第二铁电图案FE2的厚度可以在测量误差内彼此相等，或者如果可测量得不相等，可以在值上足够接近以在功能上彼此相等，如本领域普通技术人员将理解的。或者，在一示范性实施方式中，第一铁电图案FE1和第二铁电图案FE2可以具有彼此不同的厚度。
因此，在一示范性实施方式中，第一铁电图案FE1的铁电材料、杂质浓度和厚度中的至少一个不同于第二铁电图案FE2的铁电材料、杂质浓度和厚度中的至少一个。也就是，在一示范性实施方式中，第一铁电图案FE1和第二铁电图案FE2的铁电材料、杂质浓度和厚度中的至少一个在第一铁电图案FE1和第二铁电图案FE2之间是不同的。
在一示范性实施方式中，第一栅极绝缘图案GI1中包括的电介质图案DE可以被称为第一电介质图案，并且形成第二栅极绝缘图案GI2的电介质图案DE可以被称为第二电介质图案。在一示范性实施方式中，形成第二栅极绝缘图案GI2的第二电介质图案(例如DE)的侧表面与栅极间隔物GS直接接触，并且形成第二栅极绝缘图案GI2的第二电介质图案(例如DE)的相反的侧表面与第二栅电极GE2直接接触。
参照图1和图13，第一栅极绝缘图案GI1可以包括电介质图案DE、第一铁电图案FE1和第二铁电图案FE2，第二栅极绝缘图案GI2可以包括电介质图案DE和第二铁电图案FE2。因此，如可见的，在一示范性实施方式中，第一栅极绝缘图案GI1可以包括第一铁电图案FE1和设置在第一铁电图案FE1上的第二铁电图案FE2两者。在一示范性实施方式中，代替包括设置在第一铁电图案FE1上的第二铁电图案FE2，与第一铁电图案FE1和第二铁电图案FE2不同的第三铁电图案可以设置在第一栅极绝缘图案GI1中的第一铁电图案FE1上。第一栅极绝缘图案GI1的第二铁电图案FE2可以插设在第一功函数金属图案WF1和第一铁电图案FE1之间。第一铁电图案FE1和第二铁电图案FE2可以与参照图12描述的之前的示范性实施方式中的那些基本上相同。
参照图1和图14，第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以包括电介质图案DE和铁电图案FE。第一栅极绝缘图案GI1的铁电图案FE和第二栅极绝缘图案GI2的铁电图案FE可以包括相同的铁电材料。第一栅极绝缘图案GI1的铁电图案FE的杂质浓度可以大约等于第二栅极绝缘图案GI2的铁电图案FE的杂质浓度。
第一栅极绝缘图案GI1的铁电图案FE可以具有第一厚度T1，第二栅极绝缘图案GI2的铁电图案FE可以具有第二厚度T2。第一厚度T1可以大于第二厚度T2。
参照图1和图15，第一栅电极GE1还可以包括插设在第一栅极绝缘图案GI1和第一功函数金属图案WF1之间的阻挡图案BM。第二栅电极GE2还可以包括插设在第二栅极绝缘图案GI2和第一功函数金属图案WF1之间的阻挡图案BM。阻挡图案BM可以防止金属元素在第一功函数金属图案WF1与第一和第二栅极绝缘图案GI1和GI2之间扩散。作为示例，阻挡图案BM可以由TiN、TaC、TaN、TiSiN、TaTiN、TaSiN或其任何组合形成，或者包括TiN、TaC、TaN、TiSiN、TaTiN、TaSiN或其任何组合，并可以具有单层或多层结构。
图16是示出根据本发明构思的一示范性实施方式的半导体器件的平面图。图17A是沿着图16的线A-A'和B-B'剖取的截面图。图17B是沿着图16的线C-C'剖取的截面图。图17C是沿着图16的线D-D'剖取的截面图。在下面的描述中，之前参照图1和图2A至图2D描述的元件可以由相同的附图标记表示，并且为了说明的方便，可以省略之前描述的元件的进一步描述。
参照图16和图17A至图17C，可以提供包括第一有源区域AR1和第二有源区域AR2的基板100。有源图案AP可以提供在第一有源区域AR1和第二有源区域AR2上。作为示例，第一有源区域AR1和第二有源区域AR2可以是逻辑单元区域。构成逻辑电路的逻辑晶体管可以设置在逻辑单元区域中。
器件隔离层ST可以提供在基板100上。器件隔离层ST可以限定基板100的上部中的有源图案AP。有源图案AP可以具有在第二方向D2上延伸的线形或条形。例如，如图16所示，有源图案AP可以具有在第二方向D2上延伸的基本上直线形状。
器件隔离层ST可以填充沟槽TR，该沟槽TR形成在有源图案AP中的相邻的一对之间。器件隔离层ST的顶表面可以低于有源图案AP的顶表面。例如，器件隔离层ST的顶表面和基板100的顶表面之间的距离可以小于有源图案AP的顶表面和基板100的顶表面之间的距离。
源极/漏极图案SD和插设在源极/漏极图案SD中的相邻一对之间的沟道图案CHP可以提供在有源图案AP上。沟道图案CHP可以包括顺序地堆叠的第一至第三半导体图案SP1、SP2和SP3。第一至第三半导体图案SP1、SP2和SP3可以在垂直于基板100的顶表面的第三方向D3上彼此间隔开。第一至第三半导体图案SP1、SP2和SP3可以彼此竖直地重叠。每个源极/漏极图案SD可以与第一至第三半导体图案SP1、SP2和SP3中的每个的侧表面直接接触。因此，第一至第三半导体图案SP1、SP2和SP3可以将源极/漏极图案SD中的相邻一对彼此连接。
沟道图案CHP的第一至第三半导体图案SP1、SP2和SP3可以具有相同的厚度或不同的厚度。作为示例，当在第二方向D2上测量时，沟道图案CHP的第一至第三半导体图案SP1、SP2和SP3的最大长度可以彼此不同。作为示例，第一半导体图案SP1在第二方向D2上的最大长度可以是第一长度，第二半导体图案SP2在第二方向D2上的最大长度可以是第二长度，并且第一长度可以大于第二长度。
沟道图案CHP的第一至第三半导体图案SP1、SP2和SP3可以包括例如硅(Si)、锗(Ge)和硅锗(SiGe)中的至少一种。尽管沟道图案CHP被示出为具有第一至第三半导体图案SP1、SP2和SP3，但是本发明构思不被限制为特定数量的半导体图案。
每个源极/漏极图案SD可以是通过采用沟道图案CHP的第一至第三半导体图案SP1、SP2和SP3以及有源图案AP作为籽晶层而形成的外延图案。作为示例，源极/漏极图案SD在第二方向D2上的宽度可以在其中间部分是最大的(例如见图17A)。源极/漏极图案SD在第二方向D2上的宽度可以从其顶部朝向中间部分增大，并且源极/漏极图案SD在第二方向D2上的宽度可以从中间部分朝向其底部减小。源极/漏极图案SD可以是p型杂质区域或n型杂质区域。作为示例，源极/漏极图案SD可以由SiGe或Si形成，或者包括SiGe或Si。
第一栅电极GE1可以被提供为交叉第一有源区域AR1中的沟道图案CHP并在第一方向D1上延伸，第二栅电极GE2可以被提供为交叉第二有源区域AR2中的沟道图案CHP并在第一方向D1上延伸。第一栅电极GE1和第二栅电极GE2可以在第二方向D2上彼此间隔开。第一栅电极GE1和第二栅电极GE2中的每个可以与沟道图案CHP竖直地重叠。一对栅极间隔物GS可以设置在第一栅电极GE1和第二栅电极GE2中的每个的相反的侧表面上。栅极覆盖图案GP可以分别提供在第一栅电极GE1和第二栅电极GE2上。
第一栅电极GE1和第二栅电极GE2中的每个可以包括顺序堆叠的第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL。第一功函数金属图案WF1可以围绕第一至第三半导体图案SP1、SP2和SP3中的每个(例如见图17B)。例如，第一功函数金属图案WF1可以被提供为面对第一至第三半导体图案SP1、SP2和SP3中的每个的顶表面、底表面和相反的侧表面。例如，根据一示范性实施方式的晶体管可以是栅极环绕型(gate-all-aroundtype)场效应晶体管。
第一栅极绝缘图案GI1可以提供在第一至第三半导体图案SP1、SP2和SP3与第一栅电极GE1之间。第二栅极绝缘图案GI2可以提供在第一至第三半导体图案SP1、SP2和SP3与第二栅电极GE2之间。第一栅极绝缘图案GI1可以包括电介质图案DE和铁电图案FE，第二栅极绝缘图案GI2可以包括电介质图案DE。在一示范性实施方式中，第二栅极绝缘图案GI2不包括铁电图案FE。
第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以围绕第一至第三半导体图案SP1、SP2和SP3。第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以插设在有源图案AP的上部和第一功函数金属图案WF1之间。第一栅极绝缘图案GI1和第二栅极绝缘图案GI2中的每个可以插设在器件隔离层ST和第一功函数金属图案WF1之间。
电介质图案DE、铁电图案FE、第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL可以与参照图1和图2A至图2D描述的之前的示范性实施方式中的那些基本上相同。
第一空间SA1可以限定在第一有源区域AR1中的第一半导体图案SP1和第二半导体图案SP2之间。例如，第一空间SA1可以限定在半导体图案SP1、SP2和SP3中的彼此竖直相邻的每对之间。
电介质图案DE、铁电图案FE和第一功函数金属图案WF1可以填充第一空间SA1。电介质图案DE和铁电图案FE可以被提供为共形地填充第一空间SA1。第一功函数金属图案WF1可以填充第一空间SA1的没有被第一栅极绝缘图案GI1填充的其余区域。在一示范性实施方式中，第二功函数金属图案WF2和电极图案EL不填充第一空间SA1。第一空间SA1中的第一栅极绝缘图案GI1可以与源极/漏极图案SD接触(例如见图17A)。例如，第一空间SA1中的第一栅极绝缘图案GI1可以插设在第一栅电极GE1和源极/漏极图案SD之间。
第二空间SA2可以限定在第一有源区域AR1中的半导体图案中的最上面的一个(例如第三半导体图案SP3)上。第二空间SA2可以是由一对栅极间隔物GS、栅极覆盖图案GP和第三半导体图案SP3围绕的空间。
电介质图案DE、铁电图案FE、第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL可以填充第二空间SA2。填充第二空间SA2的电介质图案DE、铁电图案FE、第一功函数金属图案WF1、第二功函数金属图案WF2和电极图案EL的结构或形状可以类似于参照图1和图2A至图2D描述的之前的示范性实施方式。
第一层间绝缘层110和第二层间绝缘层120可以提供在基板100上。有源接触AC可以被提供为穿透第一层间绝缘层110和第二层间绝缘层120，并可以电连接到源极/漏极图案SD。
根据本发明构思的一示范性实施方式，半导体器件包括具有改善的亚阈值摆动特性和降低的操作电压的晶体管。半导体器件包括具有铁电图案的栅极绝缘图案。结果，根据本发明构思的示范性实施方式可以实现阈值电压从区域到区域彼此不同的晶体管。
尽管已经参照本发明构思的示范性实施方式具体示出和描述了本发明构思，但是本领域普通技术人员将理解，在不脱离如权利要求书限定的本发明构思的精神和范围的情况下可以在其中进行形式和细节上的各种变化。
本申请要求分别于2018年7月6日和2019年1月15日在韩国知识产权局提交的韩国专利申请第10-2018-0078865号和第10-2019-0005362号的优先权，其公开内容通过引用整体地结合于此。

Claims (19)

1.一种半导体器件，包括：
基板，包括第一有源区域和第二有源区域；
第一有源图案和第二有源图案，分别设置在所述第一有源区域和所述第二有源区域中；
器件隔离层，填充限定所述第一有源图案和所述第二有源图案的沟槽；
第一栅电极和第二栅电极，分别交叉所述第一有源图案和所述第二有源图案；以及
插设在所述第一有源图案和所述第一栅电极之间的第一栅极绝缘图案以及插设在所述第二有源图案和所述第二栅电极之间的第二栅极绝缘图案，
其中所述第一栅极绝缘图案包括第一电介质图案和设置在所述第一电介质图案上的第一铁电图案，
所述第二栅极绝缘图案包括第二电介质图案，
所述第一有源区域中的晶体管的阈值电压不同于所述第二有源区域中的晶体管的阈值电压，
所述第一有源图案和所述第二有源图案中的每个的上部突出在所述器件隔离层之上，以及
所述第一铁电图案设置在所述第一有源图案的所述上部的顶表面和相反的侧表面上，
其中所述第二栅极绝缘图案还包括设置在所述第二电介质图案上的第二铁电图案，以及
所述第一铁电图案与所述第二铁电图案在铁电材料和杂质浓度中的至少一个方面不同。
2.如权利要求1所述的半导体器件，其中所述第一铁电图案包括铪氧化物，所述铪氧化物包括锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种。
3.如权利要求2所述的半导体器件，其中所述第一铁电图案包括具有正交晶体结构的部分，并且所述具有正交晶体结构的部分与所述第一铁电图案的体积比在从10％至50％的范围内。
4.如权利要求1所述的半导体器件，其中所述第一电介质图案和所述第二电介质图案中的每个包括硅氧化物层、高k电介质层、或其中顺序堆叠所述硅氧化物层和所述高k电介质层的多层结构。
5.如权利要求1所述的半导体器件，其中所述第一栅电极和所述第二栅电极中的每个包括顺序堆叠的第一功函数金属图案、第二功函数金属图案和电极图案，
所述第一功函数金属图案包括金属氮化物层，并且
所述第二功函数金属图案包括包含铝或硅的金属碳化物层。
6.如权利要求5所述的半导体器件，其中所述第一功函数金属图案的顶表面低于所述电极图案的顶表面，并且
所述第二功函数金属图案覆盖所述第一功函数金属图案的所述顶表面。
7.如权利要求1所述的半导体器件，其中所述第二栅极绝缘图案不包括所述第一铁电图案。
8.如权利要求1所述的半导体器件，其中所述第一铁电图案的铁电材料不同于所述第二铁电图案的铁电材料。
9.如权利要求1所述的半导体器件，其中所述第一铁电图案的厚度不同于所述第二铁电图案的厚度。
10.一种半导体器件，包括：
基板，包括第一有源区域和第二有源区域；
第一有源图案和第二有源图案，分别设置在所述第一有源区域和所述第二有源区域中；
第一栅电极和第二栅电极，分别交叉所述第一有源图案和所述第二有源图案；以及
插设在所述第一有源图案和所述第一栅电极之间的第一栅极绝缘图案以及插设在所述第二有源图案和所述第二栅电极之间的第二栅极绝缘图案，
其中所述第一栅极绝缘图案包括第一电介质图案和设置在所述第一电介质图案上的第一铁电图案，
所述第二栅极绝缘图案包括第二电介质图案和设置在所述第二电介质图案上的第二铁电图案，并且
所述第一铁电图案在铁电材料和杂质浓度中的至少一个上不同于所述第二铁电图案。
11.如权利要求10所述的半导体器件，其中所述第一有源区域中的晶体管的阈值电压不同于所述第二有源区域中的晶体管的阈值电压。
12.如权利要求10所述的半导体器件，其中所述第一铁电图案和所述第二铁电图案中的每个包括铪氧化物，所述铪氧化物掺杂有锆(Zr)、硅(Si)、铝(Al)和镧(La)中的至少一种。
13.如权利要求10所述的半导体器件，其中所述第一栅极绝缘图案还包括设置在所述第一铁电图案上的第三铁电图案。
14.如权利要求10所述的半导体器件，还包括：
器件隔离层，填充限定所述第一有源图案和所述第二有源图案的沟槽，
其中所述第一有源图案和所述第二有源图案中的每个的上部突出在所述器件隔离层之上，
所述第一铁电图案设置在所述第一有源图案的所述上部的顶表面和相反的侧表面上，并且
所述第二铁电图案设置在所述第二有源图案的所述上部的顶表面和相反的侧表面上。
15.一种半导体器件，包括：
基板，包括第一有源区域和第二有源区域；
第一有源图案和第二有源图案，分别设置在所述第一有源区域和所述第二有源区域中；
第一栅电极和第二栅电极，分别交叉所述第一有源图案和所述第二有源图案；
栅极间隔物，设置在所述第一栅电极和所述第二栅电极中的每个的侧表面上；
第一电介质图案和第一铁电图案，插设在所述第一栅电极和所述栅极间隔物之间；以及
第二电介质图案以及第二铁电图案，其被插设在所述第二栅电极和所述栅极间隔物之间，
其中所述第一栅电极包括功函数金属图案和电极图案，该功函数金属图案包括金属氮化物层，
所述第一铁电图案在所述功函数金属图案的至少一个侧壁上且插设在所述第一电介质图案与所述功函数金属图案的所述至少一个侧壁之间，以及
所述第一铁电图案与所述第二铁电图案在铁电材料和杂质浓度中的至少一个方面不同。
16.如权利要求15所述的半导体器件，其中所述第一有源区域中的晶体管的阈值电压不同于所述第二有源区域中的晶体管的阈值电压。
17.如权利要求15所述的半导体器件，其中所述第二电介质图案的侧表面与所述栅极间隔物直接接触，并且
所述第二电介质图案的相反的侧表面与所述第二栅电极直接接触。
18.如权利要求15所述的半导体器件，
其中所述第一铁电图案的铁电材料不同于所述第二铁电图案的铁电材料。
19.如权利要求15所述的半导体器件，
其中所述第一铁电图案的厚度不同于所述第二铁电图案的厚度。
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