CN110690280B - Silicon controlled rectifier device and preparation method thereof - Google Patents

Silicon controlled rectifier device and preparation method thereof Download PDF

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CN110690280B
CN110690280B CN201910849675.6A CN201910849675A CN110690280B CN 110690280 B CN110690280 B CN 110690280B CN 201910849675 A CN201910849675 A CN 201910849675A CN 110690280 B CN110690280 B CN 110690280B
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anode layer
substrate
anode
isolation
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CN110690280A (en
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张潘德
赖首雄
蓝浩涛
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Shenzhen Dexin Semiconductor Technology Co ltd
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Shenzhen Dexin Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363—Thyristors

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  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

The invention belongs to the technical field of semiconductor devices and provides a silicon controlled device and a preparation method thereof, wherein a front anode layer at the first side of a substrate layer and a back anode layer at the second side of the substrate layer are arranged in a convex shape, a protruding part of the front anode layer is positioned between a base part of the front anode layer and the substrate layer, and a protruding part of the back anode layer is positioned between the base part of the back anode layer and the substrate layer, so that a front substrate isolation region is arranged between the front isolation layer and the protruding part of the front anode layer, and a back substrate isolation region is arranged between the back isolation layer and the protruding part of the back anode layer, therefore, the breakdown voltage of the silicon controlled device can be adjusted by adjusting the widths of the front substrate isolation region and the back substrate isolation region, thereby avoiding the need of replacing different silicon substrates aiming at different breakdown voltages in the preparation process, resulting in problems of increased manufacturing cost, complicated process, etc.

Description

Silicon controlled rectifier device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a silicon controlled rectifier device and a preparation method thereof.
Background
A Silicon Controlled Rectifier (SCR) is a high-power electrical component, also called a thyristor, and has the advantages of small size, high efficiency, long service life, and the like, and is mainly applied to low-frequency switching, for example, 50 or 60Hz power switching. The rated voltage of the thyristor is usually the smaller value of forward voltage or reverse voltage, and if transient overvoltage occurs in the circuit, the thyristor can be triggered or damaged, so the rated voltage is usually set to be 2-3 times of the working peak value.
However, since the breakdown voltage of the thyristor is generally determined by the concentration of the silicon substrate, if the breakdown voltage needs to be changed, the silicon substrate needs to be replaced, which leads to problems of increased manufacturing cost, complicated process, and the like.
Disclosure of Invention
The invention aims to provide a silicon controlled rectifier device and a preparation method thereof, aiming at improving the breakdown voltage of the silicon controlled rectifier on the premise of not changing a silicon substrate.
The invention provides a silicon controlled device, comprising: a substrate layer having a first conductivity type;
the positive anode layer is arranged on the first side of the substrate layer and has a second conduction type, the positive anode layer is in a convex structure, and a convex part of the positive anode layer is positioned between the base of the positive anode layer and the substrate layer;
the back anode layer is arranged on the second side of the substrate layer and has a second conductive type, the back anode layer is of a convex structure, a protruding part of the back anode layer is positioned between the base of the back anode layer and the substrate layer, and the second side of the substrate layer is opposite to the first side of the substrate layer;
a front side isolation layer arranged on the first side of the substrate layer, contacting the substrate layer, and dividing the front side anode layer into an effective front side anode layer and an ineffective front side anode layer; the depth of the front surface isolation layer is greater than the thickness of the front surface anode layer, and a front surface substrate isolation region is arranged between the front surface isolation layer and the protruding part of the front surface anode layer;
a back isolation layer disposed on a second side of the substrate layer, contacting the substrate layer, and dividing the back anode layer into an active back anode layer and an inactive back anode layer; the depth of the back isolating layer is greater than the thickness of the back anode layer, and a back substrate isolating region is arranged between the back isolating layer and the protruding part of the back anode layer;
a plurality of front side metal layers disposed on the active front side anode layer;
a plurality of front cathode regions disposed between the active front anode layer and the front metal layer and having a first conductivity type;
a back side metal layer disposed on the active back side anode layer; and
a back cathode region disposed between the active back anode layer and the back metal layer and having a first conductivity type.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type.
Optionally, the thickness of the base of the front anode layer is 10-30 um.
Optionally, the thickness of the protruding portion of the front anode layer is 25-35 um.
Optionally, the width of the front substrate isolation region is 1-15 um.
The embodiment of the application also provides a preparation method of the silicon controlled rectifier, which comprises the following steps:
step a: determining an anode region on a first side and a second side opposite to the first side of a substrate layer with a first conductivity type by using a first mask layer, and forming a first oxide layer and a second oxide layer with a masking effect by means of thermal oxidation;
step b: implanting second conductivity type impurity ions into a substrate layer by means of ion implantation under the masking of the first oxide layer and the second oxide layer to form a front anode layer on a first side of the substrate layer and a back anode layer on a second side of the substrate layer;
step c: removing the first oxide layer and the second oxide layer, and implanting second conductive type impurity ions into the substrate layer in an ion implantation manner so as to enable the front anode layer and the back anode layer to be in a convex shape;
step d: determining a plurality of front cathode regions on the front anode layer by using a second mask layer, determining a back cathode region on the back anode layer by using a third mask layer, implanting first conductive type impurity ions into the front cathode regions under the masking of the second mask layer to form a plurality of front cathode regions, and implanting first conductive type impurity ions into the back cathode regions under the masking of the third mask layer to form a back cathode region;
step e: removing the second mask layer and the third mask layer, determining a front isolation layer area on the front anode layer by adopting a fourth mask layer, and etching under the masking of the fourth mask layer to form a front isolation groove, wherein the depth of the front isolation groove is greater than the thickness of the front anode layer so as to divide the front anode layer into an effective front anode layer and an ineffective front anode layer, and a front substrate isolation area is arranged between a protruding part of the front anode layer and the front isolation groove; etching the back anode layer to form a back isolation groove in the same way so as to divide the back anode layer into an effective back anode layer and an ineffective back anode layer, and arranging a back substrate isolation region between a protruding part of the back anode layer and the back isolation groove;
step f: filling an insulating material in the front isolation groove to form a front isolation layer, and filling an insulating material in the back isolation groove to form a back isolation layer;
step g: and forming a plurality of front metal layers on the surfaces of the front cathode regions and the effective front anode layer, wherein the front metal layers are not contacted with each other, forming a back metal layer on the surface of the effective back anode layer, and the back cathode region is positioned between the back metal layer and the effective back anode layer.
Optionally, the step a includes: and determining a front anode area on the first side of the substrate layer with the first conductivity type by using a first mask layer, and forming a first oxidation layer with the thickness of 1-5um in a thermal oxidation mode.
Optionally, step b includes: implanting a boron source into the first side of the substrate layer at a temperature of 1200-1250 degrees celsius under the masking of the first oxide layer to form a front side anode layer.
Optionally, step c includes: and removing the first oxide layer, and injecting a boron source into the first side of the substrate layer at the temperature of 1200-1500 ℃ so that the first side of the substrate layer is covered by the front anode layer, wherein the front anode layer has various thicknesses.
Optionally, step f includes: and filling an insulating material in the front isolation groove in a glass coating mode.
In the silicon controlled device and the preparation method thereof provided by the invention, the front anode layer at the first side of the substrate layer and the back anode layer at the second side of the substrate layer are arranged in a convex shape, the protruding part of the front anode layer is positioned between the base part of the front anode layer and the substrate layer, and the protruding part of the back anode layer is positioned between the base part of the back anode layer and the substrate layer, so that a front substrate isolation region is arranged between the front isolation layer and the protruding part of the front anode layer, and a back substrate isolation region is arranged between the back isolation layer and the protruding part of the back anode layer, therefore, the breakdown voltage of the silicon controlled device can be adjusted by adjusting the width of the front substrate isolation region and the back substrate isolation region, and the increase of the manufacturing cost, the increase of the manufacturing cost and the like caused by the fact that different silicon substrates need to be replaced aiming at different breakdown voltages in the preparation process are avoided, The process is complex and the like.
Drawings
Fig. 1 is a schematic cross-sectional structural diagram of a thyristor device according to an embodiment of the present application;
fig. 2 is a schematic cross-sectional view at the base 211 of the front anode layer of a thyristor device provided in an embodiment of the present application;
fig. 3 is a schematic cross-sectional view of a thyristor device provided in an embodiment of the present application at a protruding portion 212 of a front anode layer;
fig. 4 is a parameter diagram of a thyristor device according to an embodiment of the present application;
FIG. 5 is a graph of breakdown voltage versus device parameter obtained from simulation;
FIG. 6 is another graph of simulated breakdown voltage versus device parameter;
fig. 7 is a schematic structural diagram of a first oxide layer 101 and a second oxide layer 102 formed on a substrate layer 10 in a manufacturing method provided in an embodiment of the present application;
fig. 8 is a schematic structural diagram of a front anode layer 21 and a back anode layer 22 formed on the substrate layer 10 in the preparation method provided in an embodiment of the present application;
fig. 9 is another schematic structural diagram after forming a front anode layer 21 and a back anode layer 22 on a substrate layer 10 in a preparation method provided in an embodiment of the present application;
fig. 10 is a schematic structural diagram of a front cathode region 31 formed in a front anode layer and a back cathode region 32 formed in a back anode layer in a preparation method provided in an embodiment of the present application;
fig. 11 is a schematic structural diagram of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure after forming a front side isolation trench 401 in a front side anode layer 21 and forming a back side isolation trench 402 in a back side anode layer 22;
fig. 12 is a schematic structural diagram of a front-side isolation trench 401 filled with an insulating material and a back-side isolation trench 402 filled with an insulating material in a manufacturing method according to an embodiment of the present disclosure;
fig. 13 is a schematic structural diagram of a plurality of front-side metal layers 51 formed on the front-side cathode regions 31 and the surfaces of the effective front-side anode layers and a back-side metal layer 52 formed on the surfaces of the effective back-side anode layers in the preparation method according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the description of the present invention, it is to be understood that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of technical features indicated are in fact significant. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
Generally, the breakdown voltage of a silicon controlled rectifier is determined by the doping concentration of a substrate layer, silicon substrates with different doping concentrations are adopted as the substrate layer according to different breakdown voltages, the higher the doping concentration of the silicon substrate is, the lower the breakdown voltage of the prepared silicon controlled rectifier is, if the breakdown voltage of the silicon controlled rectifier needs to be increased, the silicon substrate with the lower doping concentration is generally required to be replaced as the substrate layer, and the like, so that the problems of cost increase, complex process and the like are caused by generally adjusting original process parameters when the silicon substrate is replaced, in order to increase the breakdown voltage of the silicon controlled rectifier under the premise of not changing the concentration of the silicon substrate, the embodiment of the application provides a novel silicon controlled rectifier device, and aims to improve the breakdown voltage of the silicon controlled rectifier and increase the safety factor in design under the original process parameters, without affecting the functional characteristics of the silicon controlled rectifier.
Fig. 1 is a schematic structural diagram of a thyristor device according to an embodiment of the present application, and referring to fig. 1, the thyristor device in the embodiment includes: a substrate layer 10 having a first conductivity type; a front anode layer of the second conductivity type disposed on the first side of the substrate layer 10, wherein the front anode layer is in a "convex" structure, and the protruding portion 212 of the front anode layer is located between the base 211 of the front anode layer and the substrate layer 10; a back anode layer of the second conductivity type disposed on the second side of the substrate layer 10, wherein the back anode layer is in a "convex" structure, and the protruding portion 222 of the back anode layer is located between the base 221 of the back anode layer and the substrate layer 10; a front isolating layer 41 arranged on a first side of the substrate layer 10, in contact with the substrate layer 10, for dividing the front anode layer into an active front anode layer 211 and an inactive front anode layer 213; the depth of the front surface isolation layer 41 is greater than the thickness of the front surface anode layer, and a front surface substrate isolation region 11 is arranged between the front surface isolation layer 41 and the protruding part 212 of the front surface anode layer; a back isolation layer 42 disposed on a second side of the substrate layer 10, in contact with the substrate layer 10, for dividing the back anode layer into an active back anode layer and an inactive back anode layer; the depth of the back isolation layer 42 is greater than the thickness of the back anode layer, and a back substrate isolation region 12 is arranged between the back isolation layer 42 and the protruding part 222 of the back anode layer; a plurality of front side metal layers 51 disposed on the active front side anode layer; a plurality of front cathode regions 31 disposed between the active front anode layer and the front metal layer 51 and having a first conductivity type; a back side metal layer disposed on the active back side anode layer; and a back cathode region 32 of the first conductivity type disposed between the active back anode layer and the back metal layer 52.
In this embodiment, the first side of the substrate layer 10 is provided with a front anode layer, the front anode layer is in a "convex" structure, the protruding portion 212 of the front anode layer extends into the first side of the substrate layer 10, and the base portion 211 of the front anode layer covers the first side of the substrate layer 10, specifically, the front anode layer can have multiple thicknesses, for example, when the front anode layer has two thicknesses, the protruding portion 212 of the front anode layer can be used as a first front anode layer, the base portion 211 of the front anode layer can be used as a second front anode layer, the area of the second front anode layer is larger than that of the first front anode layer, a junction structure with a height difference is formed by overlapping the second front anode layer and the first front anode layer, further, the "convex" structure can also be a tower-shaped structure that gradually tapers from large to small, and the tower tip of the tower-shaped structure extends into the substrate layer 10, and at this time, the front anode layer can have more than two thicknesses. The back anode layer provided on the second side of the substrate layer 10 has a similar structure to the front anode layer described above and will not be described in detail here.
Fig. 2 is a schematic cross-sectional view at the base 211 of the front anode layer of a thyristor device provided in an embodiment of the present application, in which the front anode layer is divided into an active front anode layer and an inactive front anode layer 213 by a front isolating layer 41, see fig. 2, on the first side of the substrate layer 10. The plurality of front cathode regions 31 are separated by the effective front anode layer 211, and in one embodiment, there may be two front cathode regions 31, a first front cathode region 31 is adjacent to the front separation layer 41 and has a rectangular parallelepiped shape, and a second front cathode region 31 is located at the center of the effective front anode layer 211 and has a cylindrical shape. The second front cathode region 31 can be embedded in the first front cathode region 31 and isolated by the active front anode layer 211, since the front cathode region 31 is an N-type doped region and the active front anode layer 211 is a P-type doped region, providing a stable PN junction between the front cathode region 31 and the active front anode layer 211.
Further, fig. 3 is a schematic cross-sectional view of the protruding portion 212 of the front anode layer of the thyristor device according to an embodiment of the present disclosure, referring to fig. 3, a front substrate isolation region 11 is disposed between the front isolation layer 41 and the protruding portion 212 of the front anode layer, a width of the front substrate isolation region 11 is X, the front substrate isolation region 11 belongs to a portion of the substrate layer 10, the width X of the front substrate isolation region 11 determines a height difference degree of a PN junction formed between the front anode layer and the substrate layer 10, because the substrate layer 10 has the first conductive type, the front anode layer has the second conductive type, the substrate layer 10 and the front substrate isolation region 11 form the PN junction, and the breakdown voltage is adjusted by adjusting the thickness of the front anode layer and the width of the front substrate isolation region 11.
In one embodiment, referring to fig. 4, the width of the front substrate isolation region 11 is X, the thickness of the protruding portion 212 of the front anode layer is Y, the thickness of the base portion 211 of the front anode layer is Z, in the case of using the same silicon substrate as the substrate layer, the silicon controlled device is simulated by setting different X, Y, Z, fig. 5 is a relationship diagram of breakdown voltage and device parameters obtained by simulation, referring to fig. 5, when the thickness Y of the protruding portion 212 of the front anode layer is determined, the breakdown voltage of the silicon controlled device can be increased by decreasing the width X of the front substrate isolation region 11, and when the width X of the front substrate isolation region 11 is determined, the breakdown voltage of the silicon controlled device can be increased by increasing the thickness Y of the protruding portion 212 of the front anode layer, referring to fig. 5, when the thickness Y of the protruding portion 212 of the front anode layer is 30um, and the width X of the front substrate isolation region 11 is 15um, the breakdown voltage of the silicon controlled device is about 1450V, and the breakdown voltage of the silicon controlled device slowly increases along with the increase of junction temperature of a PN junction, when the thickness Y of the protruding part 212 of the anode layer of the front side is 30um, and the width X of the front side substrate isolation area 11 is gradually reduced to 0um, the breakdown voltage of the silicon controlled device is slightly increased compared with the breakdown voltage of the silicon controlled device with the X of 15um, and the general type in FIG. 5 is the breakdown voltage for preparing the silicon controlled device under the same substrate layer by adopting the traditional silicon controlled device structure.
In one embodiment, fig. 6 is another graph of the breakdown voltage and the device parameter obtained by simulation, and referring to fig. 6, when the thickness Y of the protruding portion 212 of the front anode layer and the thickness Z of the base portion 211 of the front anode layer are determined, the breakdown voltage of the thyristor device gradually decreases as the width X of the front substrate isolation region 11 gradually increases. When the width X of the front substrate isolation region 11 and the thickness Z of the base 211 of the front anode layer are determined, the breakdown voltage of the thyristor increases as the thickness Y of the protrusion 212 of the front anode layer increases, and when the width X of the front substrate isolation region 11 and the thickness Y of the protrusion 212 of the front anode layer are determined, the breakdown voltage of the thyristor increases as the thickness Z of the base 211 of the front anode layer increases. When the width X of the front substrate isolation region 11 is determined to be 25um, the thickness Y of the protruding portion 212 of the front anode layer is 25um, and the thickness Z of the base portion 211 of the front anode layer is 15um, the breakdown voltage of the thyristor device is the smallest in the multiple sets of simulation results, and the breakdown voltage is about 1225V, at this time, the thickness Y of the protruding portion 212 of the front anode layer is 35um, and the thickness Z of the base portion 211 of the front anode layer is 20um, the breakdown voltage of the thyristor device is the largest in the multiple sets of simulation results, and the breakdown voltage is about 1448V.
In one embodiment, the parameters of the back anode layer on the second side of the substrate layer 10 are the same as the parameters of the front anode layer, in particular, the thickness of the protrusions 222 of the back anode layer and the bases 221 thereof is the same as the thickness of the front anode layer during application, and further, the width of the back spacer 42 is the same as the width of the front spacer 41.
In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In the present embodiment, the first conductivity type is N-type, i.e., the semiconductor material is made to be an electron conductivity type semiconductor by doping the semiconductor material with impurity ions of N-type conductivity, and the second conductivity type is P-type, i.e., the semiconductor material is made to be a hole conductivity type semiconductor by doping the semiconductor material with impurity ions of P-type conductivity, wherein the impurity ions of N-type conductivity are N-type impurity ions such as arsenic ions, phosphorus ions, nitrogen ions, and the like, and the impurity ions of P-type conductivity are P-type impurity ions such as boron ions.
In one embodiment, the thickness Z of the base 211 of the front side anode layer is 10-30 um.
In one embodiment, the thickness Y of the projections 212 of the front anode layer is 25-35 um. In this embodiment, when the thickness Y of the protruding portion 212 of the front anode layer is 25-35um, the breakdown voltage of the scr device can be greatly increased.
In one embodiment, the width X of the front substrate isolation region is 1-15 um. In the present embodiment, when the width X of the front substrate isolation region is 1 to 15um, a higher breakdown voltage can be obtained.
In one embodiment, the front side isolation layer 41 is an insulating material. In this embodiment, referring to fig. 2, by dividing the front anode layer into the effective front anode layer and the ineffective front anode layer 213 by using an insulating material, since the depth of the front isolation layer 41 is greater than the thickness of the ineffective front anode layer 213, there is no electrical connection between the effective front anode layer and the ineffective front anode layer 213, and by dividing the epitaxial layer into the effective front anode layer and the ineffective front anode layer 213, the ineffective front anode layer 213 can be diced after the device manufacturing process is completed, thereby completing the preparation of a single thyristor device.
In one embodiment, the insulating material is silicon dioxide. In this embodiment, the front isolation layer 41 may be formed by etching a trench and then filling the trench with silicon dioxide, and specifically, silicon dioxide may be formed in the trench as the front isolation layer 41 by using a glass coating method after the trench is etched.
In one embodiment, the thickness of the front cathode region 31 is 10-25 um. In this embodiment, the thickness of the front cathode region 31 may be smaller than or equal to the thickness Z of the base 211 of the front anode layer, or may be larger than the thickness Z of the base 211 of the front anode layer, and a schematic horizontal cross-sectional structure of the thyristor device at the protruding portion 212 of the front anode layer is shown in fig. 3.
In one embodiment, the front metal layer is metallic aluminum.
In one embodiment, the back metal layer is metallic silver.
An embodiment of the present application further provides a method for manufacturing a silicon controlled device, where the method includes:
step a: the anode region is defined by a first mask layer on a first side and on a second side opposite to the first side of the substrate layer 10 having the first conductivity type, and a first oxide layer 101 and a second oxide layer 102 having a masking effect are formed by means of thermal oxidation, see fig. 7.
In this embodiment, the first mask layer is used to define a front anode region on the first side of the substrate layer 10 and a back anode region on the second side of the substrate layer 10, respectively, and the first oxide layer 101 and the second oxide layer 102 having a masking effect are formed by thermal oxidation, so as to prepare for implanting the second conductive type impurity ions into the substrate layer 10 in the next step.
In one embodiment, the substrate layer 10 may be a silicon substrate doped with impurity ions of the first conductivity type, and in particular, may be formed by implanting a phosphorus source into the silicon substrate.
In one embodiment, the step a includes: a front anode area is defined on a first side of a substrate layer 10 having a first conductivity type using a first mask layer and a first oxide layer 101 having a thickness of 1-5um is formed by means of thermal oxidation. Further, in this embodiment, the same preparation method may also be adopted to form the second oxide layer 102 on the second side of the substrate layer 10, wherein the thickness of the second oxide layer 102 is equal to the thickness of the first oxide layer 101.
Step b: a second conductivity type impurity is ion implanted into the substrate layer 10 under the masking of the first oxide layer 101 and the second oxide layer 102 by means of ion implantation to form a front side anode layer 21 at a first side of the substrate layer 10 and a back side anode layer 22 at a second side of the substrate layer, see fig. 8.
In this embodiment, the first mask layer is removed, and then the front anode layer 21 is formed on the first side of the substrate layer 10 by implanting the second conductive type impurity ions into the substrate layer 10, and the back anode layer 22 is formed on the second side of the substrate layer, in which case, due to the masking effect of the first oxide layer 101 and the second oxide layer 102, the edge portion of the substrate layer 10 is shielded by the oxide layer, the central region of the first side of the substrate layer 10 forms the front anode layer 21, and the central region of the second side of the substrate layer 10 forms the back anode layer 22.
In one embodiment, the step b comprises: a boron source is implanted into the first side of the substrate layer 10 at a temperature of 1200-1250 degrees celsius under the masking of the first oxide layer 101 to form a front side anode layer 21. Further, a back anode layer 22 may be formed on the second side of the substrate layer 10 in the same manner.
In one embodiment, the thickness of the front side anode layer 21 in step b is 40-80 um.
Step c: the first oxide layer 101 and the second oxide layer 102 are removed, and a second conductive type impurity is ion-implanted into the substrate layer 10, so that the front anode layer 21 and the back anode layer 22 are in a convex shape, as shown in fig. 9.
In this embodiment, after implanting the second conductive type impurity ions into the substrate layer 10 again, the front side anode layer 21 has a "convex" structure, with its projections 212 extending into the first side of the substrate layer 10 and with its base 211 overlying the first side of the substrate layer 10, in particular, the front side anode layer 21 can have a variety of thicknesses, for example, when the front side anode layer has two thicknesses, its protrusions 212 may be used as a first front side anode layer, and its base 211 as a second front side anode layer, the second front side anode layer having a larger area than the first front side anode layer, by superposing the second positive anode layer and the first positive anode layer to form a PN junction structure with high-low fall, furthermore, the convex structure can also be a tower-shaped structure which gradually reduces from large to small, the tip of which extends into the substrate layer 10, in which case the front anode layer 21 can have more than two thicknesses. The back anode layer provided on the second side of the substrate layer 10 has a similar structure to the front anode layer described above and will not be described in detail here.
In one embodiment, the step c comprises: and removing the first oxide layer, and injecting a boron source into the first side of the substrate layer at the temperature of 1200-1500 ℃ so that the first side of the substrate layer 10 is covered by the front anode layer, wherein the front anode layer 21 has various thicknesses.
In one embodiment, the implantation depth of the boron source is 10-30um in this embodiment, so that two times of implantation of the boron source form a PN junction structure with high and low drop.
In this embodiment, the base 211 of the front side anode layer is formed by implanting a boron source at a temperature of 1200-1500 degrees celsius into the first side of the substrate layer, the base 211 having a thickness Z of 10-30 um.
Step d: a plurality of front cathode regions are defined on the front anode layer 21 using a second mask layer, a rear cathode region is defined on the rear anode layer 22 using a third mask layer, and impurity ions of the first conductivity type are implanted into the plurality of front cathode regions under the mask of the second mask layer to form a plurality of front cathode regions 31, and impurity ions of the first conductivity type are implanted into the rear cathode region under the mask of the third mask layer to form a rear cathode region 32, as shown in fig. 10.
In the present embodiment, different cathode regions can be formed on both sides of the substrate layer 10 by using different mask layers, specifically, a plurality of front cathode regions can be defined on the front anode layer 21 by using a second mask layer to form a plurality of front cathode regions 31, and a back cathode region can be defined on the back anode layer 22 by using a third mask layer to implant the first conductivity type impurity ions into the back cathode region under the mask of the third mask layer to form the back cathode region 32.
In one embodiment, step d in this embodiment specifically includes: the front cathode region 31 is formed by implanting a phosphorus source in the front cathode region, wherein the phosphorus source is implanted to a depth of 10-25 um.
Step e: removing the second mask layer and the third mask layer, determining a front surface isolation layer region on the front surface anode layer 21 by using a fourth mask layer, and etching under the masking of the fourth mask layer to form a front surface isolation trench 401, wherein the depth of the front surface isolation trench 401 is greater than the thickness of the front surface anode layer 21 so as to divide the front surface anode layer 21 into an effective front surface anode layer and an ineffective front surface anode layer 213, and a front surface substrate isolation region 11 is arranged between a protruding part 212 of the front surface anode layer 21 and the front surface isolation trench; in the same manner, a back isolation trench 402 is etched in the back anode layer 22 to divide the back anode layer 22 into an effective back anode layer and an ineffective back anode layer 223, and a back substrate isolation region 12 is provided between the protruding portion 222 of the back anode layer 22 and the back isolation trench 402, as shown in fig. 11.
In this embodiment, a fourth mask layer is used to determine a front isolation layer region on the front anode layer 21, and an etching solution is used to etch under the masking of the fourth mask layer to form a front isolation trench 401, specifically, the etching solution used in the etching process is a mixed solution of nitric acid/hydrofluoric acid/glacial acetic acid, silicon dioxide is formed on the surface of the front anode layer 21, and then is etched and removed by the etching solution, so as to form the front isolation trench 401. Further, the same etching process may be used to form the back isolation trench 402, which is not described herein.
Step f: the front isolation trenches 401 are filled with an insulating material to form front isolation layers 41, and the back isolation trenches 402 are filled with an insulating material to form back isolation layers 42, as shown in fig. 12. Referring to fig. 2, in the present embodiment, on the first side of the substrate layer 10, the front side isolation layer 41 divides the front side anode layer into an active front side anode layer and an inactive front side anode layer 213, wherein the active front side anode layer is located in the area surrounded by the front side isolation trench 401. Further, fig. 3 is a schematic cross-sectional view of the protruding portion 212 of the front anode layer of the thyristor device according to an embodiment of the present disclosure, referring to fig. 3, a front substrate isolation region 11 is disposed between the front isolation layer 41 and the protruding portion 212 of the front anode layer, the front substrate isolation region 11 belongs to a portion of the substrate layer 10, a width of the front substrate isolation region 11 determines a degree of a height difference of a PN junction formed between the front anode layer and the substrate layer 10, since the substrate layer 10 has a first conductivity type and the front anode layer has a second conductivity type, a PN junction is formed between the substrate layer 10 and the front substrate isolation region 11, and a breakdown voltage is adjusted by adjusting a thickness of the front anode layer and a width of the front substrate isolation region 11.
In one embodiment, the step f comprises: and filling an insulating material in the front isolation trench 401 by adopting a glass coating mode. In this embodiment, referring to fig. 2, by dividing the front anode layer into the effective front anode layer and the ineffective front anode layer 213 by using an insulating material, since the depth of the front isolation layer 41 is greater than the thickness of the ineffective front anode layer 213, there is no electrical connection between the effective front anode layer and the ineffective front anode layer 213, and by dividing the epitaxial layer into the effective front anode layer and the ineffective front anode layer 213, the ineffective front anode layer 213 can be diced after the device manufacturing process is completed, thereby completing the preparation of a single thyristor device.
In one embodiment, the insulating material is silicon dioxide, and the front isolation layer 41 is formed by sintering at 800 ℃ and 500 ℃. the glass coating method has the advantages of high reliability and moisture resistance.
Step g: a plurality of front metal layers 51 are formed on the front cathode regions 31 and the active front anode layer, the front metal layers 51 are not in contact with each other, a back metal layer 52 is formed on the active back anode layer, and the back cathode region 32 is located between the back metal layer 52 and the active back anode layer, as shown in fig. 13.
In the silicon controlled device and the preparation method thereof provided by the invention, the front anode layer at the first side of the substrate layer and the back anode layer at the second side of the substrate layer are arranged in a convex shape, the protruding part of the front anode layer is positioned between the base part of the front anode layer and the substrate layer, and the protruding part of the back anode layer is positioned between the base part of the back anode layer and the substrate layer, so that a front substrate isolation region is arranged between the front isolation layer and the protruding part of the front anode layer, and a back substrate isolation region is arranged between the back isolation layer and the protruding part of the back anode layer, therefore, the breakdown voltage of the silicon controlled device can be adjusted by adjusting the width of the front substrate isolation region and the back substrate isolation region, and the increase of the manufacturing cost, the increase of the manufacturing cost and the like caused by the fact that different silicon substrates need to be replaced aiming at different breakdown voltages in the preparation process are avoided, The process is complex and the like.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (8)

1. A silicon controlled device, comprising: a substrate layer having a first conductivity type;
the positive anode layer is arranged on the first side of the substrate layer and has a second conduction type, the positive anode layer is in a convex structure, and a convex part of the positive anode layer is positioned between the base of the positive anode layer and the substrate layer; the convex structure is a tower-shaped structure with an orthographic projection area which is gradually reduced from large to small on the substrate layer, the protruding part has more than two orthographic projection areas on the substrate layer, and the protruding part of the tower-shaped structure extends into the substrate layer;
the back anode layer is arranged on the second side of the substrate layer and has a second conductive type, the back anode layer is of a convex structure, a protruding part of the back anode layer is positioned between the base of the back anode layer and the substrate layer, and the second side of the substrate layer is opposite to the first side of the substrate layer;
a front side isolation layer arranged on the first side of the substrate layer, contacting the substrate layer, and dividing the front side anode layer into an effective front side anode layer and an ineffective front side anode layer; the depth of the front surface isolation layer is greater than the thickness of the front surface anode layer, and a front surface substrate isolation region is arranged between the front surface isolation layer and the protruding part of the front surface anode layer;
a back isolation layer disposed on a second side of the substrate layer, contacting the substrate layer, and dividing the back anode layer into an active back anode layer and an inactive back anode layer; the depth of the back isolating layer is greater than the thickness of the back anode layer, and a back substrate isolating region is arranged between the back isolating layer and the protruding part of the back anode layer;
a plurality of front side metal layers disposed on the active front side anode layer;
a plurality of front cathode regions disposed between the active front anode layer and the front metal layer and having a first conductivity type;
a back side metal layer disposed on the active back side anode layer; and
a back cathode region disposed between the active back anode layer and the back metal layer and having a first conductivity type;
and in the plurality of positive cathode regions, a first positive cathode region is close to the positive isolation layer and is in a cuboid shape, a second positive cathode region is positioned at the central position of the effective positive anode layer and is in a cylindrical shape, and the second positive cathode region is embedded into the first positive cathode region.
2. The silicon controlled device as claimed in claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
3. The silicon controlled device of claim 1, wherein the front side substrate isolation region has a width of 1-15 um.
4. A preparation method of a silicon controlled rectifier device is characterized by comprising the following steps:
step a: determining an anode region on a first side and a second side opposite to the first side of a substrate layer with a first conductivity type by using a first mask layer, and forming a first oxide layer and a second oxide layer with a masking effect by means of thermal oxidation;
step b: implanting second conductivity type impurity ions into the substrate layer by means of ion implantation under the masking of the first oxide layer and the second oxide layer to form a base of a front anode layer at a first side of the substrate layer and a base of a back anode layer at a second side of the substrate layer;
step c: removing the first oxide layer and the second oxide layer, and implanting second conductive type impurity ions into a substrate layer in an ion implantation mode to form protruding parts of the front anode layer and the back anode layer; the anode layer on the front side and the anode layer on the back side are in a convex structure, the convex structure is a tower-shaped structure with an orthographic projection area gradually reduced from large to small on the substrate layer, the protruding part has more than two orthographic projection areas on the substrate layer, and the protruding part of the tower-shaped structure extends into the substrate layer;
step d: determining a plurality of front cathode regions on the front anode layer by using a second mask layer, determining a back cathode region on the back anode layer by using a third mask layer, implanting first conductive type impurity ions into the front cathode regions under the masking of the second mask layer to form a plurality of front cathode regions, and implanting first conductive type impurity ions into the back cathode regions under the masking of the third mask layer to form a back cathode region;
step e: removing the second mask layer and the third mask layer, determining a front isolation layer area on the front anode layer by adopting a fourth mask layer, and etching under the masking of the fourth mask layer to form a front isolation groove, wherein the depth of the front isolation groove is greater than the thickness of the front anode layer so as to divide the front anode layer into an effective front anode layer and an ineffective front anode layer, and a front substrate isolation area is arranged between a protruding part of the front anode layer and the front isolation groove; etching the back anode layer to form a back isolation groove in the same way so as to divide the back anode layer into an effective back anode layer and an ineffective back anode layer, wherein a back substrate isolation region is arranged between a protruding part of the back anode layer and the back isolation groove;
step f: filling an insulating material in the front isolation groove to form a front isolation layer, and filling an insulating material in the back isolation groove to form a back isolation layer;
step g: forming a plurality of front metal layers on the surfaces of the front cathode regions and the effective front anode layer, wherein the front metal layers are not contacted with each other, forming a back metal layer on the surface of the effective back anode layer, and the back cathode region is positioned between the back metal layer and the effective back anode layer;
and in the plurality of positive cathode regions, a first positive cathode region is close to the positive isolation layer and is in a cuboid shape, a second positive cathode region is positioned at the central position of the effective positive anode layer and is in a cylindrical shape, and the second positive cathode region is embedded into the first positive cathode region.
5. The method of claim 4, wherein step a comprises: and determining a front anode area on the first side of the substrate layer with the first conductivity type by using a first mask layer, and forming a first oxidation layer with the thickness of 1-5um in a thermal oxidation mode.
6. The method of claim 4, wherein step b comprises: a boron source is implanted into the first side of the substrate layer at a temperature of 1200-1250 degrees celsius under the masking of the first oxide layer to form a base of the front side anode layer.
7. The method of claim 4, wherein step c comprises: and removing the first oxide layer, and injecting a boron source into the first side of the substrate layer at the temperature of 1200-1500 ℃ so as to enable the first side of the substrate layer to be covered by the front anode layer, wherein the protruding part of the front anode layer has more than two types of orthographic projection areas on the substrate layer.
8. The method of claim 4, wherein step f comprises: and filling an insulating material in the front isolation groove in a glass coating mode.
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