CN110690236A - Anti-creeping deep depletion image sensor pixel unit structure and manufacturing method - Google Patents
Anti-creeping deep depletion image sensor pixel unit structure and manufacturing method Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
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- H01L27/144—Devices controlled by radiation
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- H01L27/144—Devices controlled by radiation
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- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract
The invention discloses an anti-creeping pixel unit structure of a deep depletion image sensor, which comprises a P-shaped substrate arranged on a substrate‑An N well and a photodiode on the front surface of the silicon substrate, a deep trench isolation arranged between the N well and the photodiode, and a P‑P on the back side of a silicon substrate++Injecting a substrate layer; electrically isolating the N-well from the photodiode by making the depth of the deep trench isolation greater than the injection depth of the N-well and the photodiode, and connecting the well potential of the N-well to a power supply voltage to connect P++Implanting a substrate layer with negative bias to form a channel between the N well and the P well‑Silicon substrate and P++And a reverse biased PN junction is formed between the injected substrate layers. The invention can reduce pixel noise, reduce electric leakage and improve the performance of the image sensor. The invention also discloses a manufacturing method of the anti-creeping deep depletion image sensor pixel unit structure.
Description
Technical Field
The invention relates to the technical field of solid-state image sensors, in particular to an anti-creeping deep depletion image sensor pixel unit structure and a manufacturing method thereof.
Background
An image sensor refers to a device that converts an optical signal into an electrical signal, and image sensor chips generally used in large-scale commercial applications include two major types, a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS) image sensor chip.
The absorption coefficient of the silicon material for incident light decreases with increasing wavelength. Conventional CMOS image sensor pixel cells typically use filter layers of the three primary colors red, green, and blue. Wherein the wavelength of the blue light is 450 nanometers, the wavelength of the green light is 550 nanometers, and the wavelength of the red light is 650 nanometers. The red light is absorbed most deeply and the blue light is the least deep. Blue light is absorbed at the position closest to the silicon surface, the absorption coefficient is highest, red light enters the silicon substrate deepest and can enter the silicon substrate about 2.3 mu m, the absorption coefficient is lowest, green light is between the absorption coefficient and the absorption coefficient, and the absorption thickness of near infrared light is required to be more than 2.3 mu m. Meanwhile, in the application of the current security monitoring, machine vision and intelligent traffic system, the light wavelength of the infrared supplementary lighting at night is concentrated in the range of 850nm to 940nm, and the pixel unit of the conventional back-illuminated CMOS image sensor is insensitive to the light of the wavelength. Therefore, a new back-illuminated pixel unit structure and a forming method need to be designed to improve the sensitivity of the near-infrared band and improve the night vision effect of the product.
An image sensor pixel unit using a clamped photodiode (PPD) structure is widely used in high-performance imaging due to low readout noise, high conversion gain, and low dark current. For applications requiring high quantum efficiency in near infrared and soft X-ray bands, the thickness of the silicon layer of the active sensor usually reaches tens of even hundreds of microns, and by applying a reverse bias voltage to the back of the silicon substrate, the thick silicon layer is completely depleted, thereby eliminating the electric field-free region in the conventional image sensor, so that the photogenerated charges generated in the silicon substrate can be collected in time. The magnitude of the reverse bias voltage depends on the resistivity and thickness of the semiconductor substrate and can far exceed any other voltage in the system, forming a deeply depleted pixel structure that has been used in hybrid CMOS image sensors or CCDs.
However, the above-described structure has a problem that a leak is easily formed. For an active pixel sensor, as shown in fig. 1, the control transistor of the pixel cell needs to be formed in the P-well 22 beside the clamped photodiode 26. The final P-well is pulled off at 0v substrate potential 21, which is negatively biased20 is added to P++Implanted on the substrate 23 to increase the depletion depth under the clamped photodiode 26. This structure will result in a 0v substrate potential 21 and P for the P-well 22++A large current flows between the negative bias voltages 20 implanted into the substrate 23 from the P well 22 on the front side of the silicon wafer to the P on the back side of the silicon wafer++And (4) contacting. To eliminate this parasitic current, conventional structures are at a high resistance P-An N-type lightly doped implant 25, also called dde (depletion extension) structure, is added in the substrate 24 under the P-well 22 of the pixel cell to align the P-well 22 and the P-well++The leakage path between the implanted substrates 23 forms a pinch-off. However, such DDE has the defects that the potential thereof is influenced by the potential of the photodiode, and the process window of implantation energy and dose is very small, so that a leakage path is easily formed in the pixel operation process, resulting in the degradation of the performance of the image sensor.
Therefore, it is necessary to design a method for thoroughly preventing P-well extraction and P++A method of implanting a leakage path between substrates.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned defects in the prior art, and provides a structure of a pixel unit of a deep depletion image sensor and a method for fabricating the same.
In order to achieve the purpose, the technical scheme of the invention is as follows:
the invention provides an anti-creeping pixel unit structure of a deep depletion image sensor, which comprises: are arranged in parallel at a P-An N-well and a photodiode on the front side of the silicon substrate, a deep trench isolation provided between the N-well and the photodiode, and a P-well-P on the back side of a silicon substrate++Injecting a substrate layer; wherein the deep trench is isolated at the P-The depth in the silicon substrate is greater than the injection depth of the N trap and the photodiode so as to electrically isolate the N trap and the photodiode, and the potential of the trap of the N trap is connected with a power supply voltage so as to connect the P++Implanting a substrate layer with a negative bias to form a channel between the N-well and the P-Silicon substrate and P++And a reverse biased PN junction is formed between the injected substrate layers.
Further, a fixed charge layer is arranged along the surface of the inner wall of the deep groove isolation.
Further, the fixed charge layer carries a negative fixed charge for the P outside the deep trench isolation-A positive charge is induced in the silicon substrate.
Further, the material of the fixed charge layer is a high dielectric constant material.
Further, the material of the fixed charge layer is hafnium oxide or zirconium oxide.
Further, the photodiode is a clamped photodiode.
Further, still include: is arranged at the P-A transfer tube and a floating drain on the front side of the silicon substrate.
The invention also provides a manufacturing method of the anti-creeping deep depletion image sensor pixel unit structure, which comprises the following steps:
providing a P-A silicon substrate on the P-Forming a trench structure isolated by a deep trench on the front surface of the silicon substrate, and enabling the depth of the trench to be greater than the maximum injection depth of an N well to be formed and a photodiode;
depositing a fixed charge layer on the surface of the inner wall of the groove and enabling the fixed charge layer to have negative fixed charges;
filling a dielectric layer in the groove to form a deep groove isolation structure;
the P on both sides of the deep trench isolation by photolithography and ion implantation-Respectively forming an N well and a photodiode on the front surface of the silicon substrate, and enabling the depth of the N well and the depth of the photodiode to be smaller than the depth of the deep groove isolation;
using conventional procedures, in said P-A transmission tube and a suspended drain electrode of the pixel unit are formed on the front surface of the silicon substrate;
the P is added-Thinning the back of the silicon substrate to the required thickness;
the P after thinning is processed by an injection and annealing process-Forming P on the back surface of the silicon substrate++And injecting the substrate layer.
Further, the photodiode is a clamped photodiode.
Further, the material of the fixed charge layer is hafnium oxide or zirconium oxide, and the hafnium oxide or zirconium oxide is made to have negative fixed charges through adjustment of a process menu.
The invention has the following remarkable characteristics:
(1) the manufacturing of the pixel cell transistor is performed by using an N-well, i.e. the associated control transistor of the pixel cell is changed from an NMOS to a PMOS transistor. The noise of the PMOS tube is less than that of the NMOS tube, so the noise characteristic of the pixel is correspondingly improved. The well potential of the N well is connected with the power supply voltage, so that the N well and the P well are connected-Silicon substrate and P++Injecting a negative bias between the two layers to form a reverse biased PN junction to avoid forming the P well and P shown in FIG. 1++And injecting a leakage path between the substrate layers.
(2) The clamp-off voltage in the clamp photodiode is usually between 1-2V, and the power supply potential of the N-well is usually 3.3V, i.e. the potential in the clamp photodiode is different from the N-well connected with the power supply voltage. In order to prevent electric leakage between the clamping type photodiode and the N trap, the invention adopts deep groove isolation with the depth larger than the injection depth of the N trap or the clamping type photodiode to isolate the N trap and the clamping type photodiode, because the deep groove isolation depth is larger than the N trap and the clamping type photodiode, and the bottom of the deep groove isolation is high-resistance P-A silicon substrate, thus avoiding leakage between the two.
(3) Meanwhile, the fixed charge layer is used on the inner wall of the deep groove isolation, the fixed charge layer can be made of high-dielectric constant materials such as hafnium oxide or zirconium oxide and is adjusted through a process menu to be provided with fixed negative charges, the fixed negative charges induce positive charges in the silicon substrate on the outer side of the groove isolation, the positive charges can further prevent electric leakage between the N well and the clamping type photodiode, dark current of the clamping type photodiode can be reduced, and therefore performance of a pixel unit can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a pixel unit of a conventional deep depletion image sensor.
Fig. 2 is a schematic diagram of a pixel unit structure of an anti-creeping deep depletion image sensor according to a preferred embodiment of the invention.
Fig. 3 is a partially enlarged structural view of the vicinity of the deep trench isolation region a in fig. 2.
Fig. 4-11 are schematic process steps of a method for fabricating an anti-creeping deep depletion image sensor pixel unit structure according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 2, fig. 2 is a schematic diagram illustrating a structure of a pixel unit of an anti-creeping deep depletion image sensor according to a preferred embodiment of the present invention. As shown in FIG. 2, the pixel unit structure of the anti-creeping deep depletion image sensor of the present invention is arranged at a high resistance P-On a silicon substrate 1. The method specifically comprises the following steps: arranged in parallel in the horizontal direction at a high resistance P-An N well 2 and a photodiode 3 on the front surface of a silicon substrate 1; p arranged between the N well 2 and the photodiode 3-A deep trench isolation 8 for electrically isolating the N-well 2 from the photodiode 3 on the front surface of the silicon substrate 1; is arranged at high resistance P-The pixel unit structure of the image sensor comprises a transmission tube (grid) 4, a suspended drain 5 and the like on the front surface of a silicon substrate 1; and is provided at P-P on the back side of silicon substrate 1++A substrate layer 9 is implanted.
The photodiode 3 may employ a clamp photodiode 3. The deep trench isolation 8 is filled with a dielectric layer 6. Deep trench isolation 8 at P-The depth of the silicon substrate 1 is larger than that of the N well 2 and the photodiode 3 at P-The implantation depth in the silicon substrate 1.
Wherein the deep trench isolation 8 is at P-The depth in the silicon substrate 1 is greater than the injection depth of the N well 2 and the photodiode 3, so that the N well 2 and the photodiode 3 are electrically isolated. The clamp voltage of the clamp photodiode 3 is usually between 1-2V, and the power supply potential of the N-well 2 is usually 3.3V, i.e. the potential of the clamp photodiode 3 is different from the N-well 2 connected to the power supply voltage. In order to prevent leakage between the clamp photodiode 3 and the N-well 2, the present invention performs isolation between the N-well 2 and the clamp photodiode 3 by using a deep trench isolation 8 having a depth greater than the depth of the N-well 2 or the implant depth of the clamp photodiode 3. Because the depth of the deep groove isolation 8 is larger than the depth of the N trap 2 and the clamping type photodiode 3, and the bottom of the deep groove isolation 8 is high-resistance P-The silicon substrate 1, so that the occurrence of leakage between the N-well 2 and the clamped photodiode 3 is completely avoided.
In addition, the invention uses the N well 2 to manufacture the pixel unit transistor, namely, the related control transistor of the pixel unit is changed from an NMOS transistor to a PMOS transistor. The noise of the PMOS tube is less than that of the NMOS tube, so the noise characteristic of the pixel is correspondingly improved. As shown in FIG. 2, since the well potential of the N well 2 is connected to the power supply voltage, the N well 2 and the P well-Silicon substrate 1 and P++Implanted between the negative bias voltages applied to the substrate layer 9 to form reverse-biased PN junctions, thereby avoiding the formation of P-wells and P-wells as shown in FIG. 1++And injecting a leakage path between the substrate layers.
Please refer to fig. 2 and fig. 3. As a preferred embodiment, a fixed charge layer 7 may be further provided along the inner wall surface of the deep trench isolation 8. The fixed charge layer 7 may be made of a high dielectric constant material such as hafnium oxide or zirconium oxide, and may be negatively charged by adjusting a process recipe. P outside the deep trench isolation 8 for these negative fixed charges-Positive charges are induced in the silicon substrate 1, which can further prevent leakage between the N-well 2 and the clamp photodiode 3, and can reduce dark current of the clamp photodiode 3, improving the performance of the pixel cell.
The following describes a method for fabricating an anti-creeping deep depletion image sensor pixel unit structure in detail by using the detailed embodiment and the accompanying drawings.
Referring to fig. 4-11, fig. 4-11 are schematic process steps of a method for fabricating a pixel cell structure of an anti-creeping deep depletion image sensor according to a preferred embodiment of the invention. The method for manufacturing an anti-creeping deep depletion image sensor pixel unit structure of the invention can be used for manufacturing the anti-creeping deep depletion image sensor pixel unit structure shown in fig. 3, and can specifically comprise the following steps:
first, as shown in FIG. 4, at a high impedance P-Etching of a deep groove isolation structure groove 8 'is carried out on the front surface of the silicon substrate 1, and the depth of the formed groove 8' is larger than the maximum injection depth of the N well 2 and the clamping type photodiode 3 to be formed later.
Next, as shown in fig. 5, deposition of the fixed charge layer material 7 'is performed on the inner wall surface of the trench 8'. The fixed charge layer material 7 'can use high dielectric constant material such as hafnium oxide or zirconium oxide, and the fixed charge layer material 7' can be made to have negative fixed charge through adjustment of process menu.
Then, as shown in fig. 6, a deposition and chemical mechanical polishing process of the dielectric layer material is performed in the trench 8', and only the dielectric layer material in the deep trench isolation 8 structure is remained, so as to form the deep trench isolation 8 structure having the fixed charge layer 7 and the dielectric layer 6 therein.
Next, as shown in FIG. 7, high resistance P is formed on the deep trench isolation 8 side by photolithography and ion implantation-An N well 2 is formed on the front surface of the silicon substrate 1 and is used for manufacturing a pixel unit control transistor in the following process, and the injection depth of the N well 2 is smaller than the lower end depth of the deep groove isolation 8.
Next, as shown in FIG. 8, a high resistance P is formed on the other side of the deep trench isolation 8 with respect to the N well 2 by photolithography and ion implantation-The clamp photodiode 3 is formed on the front surface of the silicon substrate 1, and also the implantation depth of the clamp photodiode 3 is made smaller than the lower end depth of the deep trench isolation 8.
Next, as shown in FIG. 9, a conventional process may be used to form a high resistance P-Transfer tubes 4 and floating drains of pixel cells formed on the front side of the silicon substrate 15。
Next, as shown in FIG. 10, the high resistance P can be formed by grinding, etching, and chemical mechanical polishing-The back side of the silicon substrate 1 is thinned to a desired thickness.
Finally, as shown in FIG. 11, the thinned high resistance P can be obtained by implantation and laser annealing-P is formed on the back surface of the silicon substrate 1++A substrate layer 9 is implanted.
In summary, the present invention prevents the P-well and P-well of the conventional pixel by forming the control transistor in the deeply depleted pixel using the PMOS in the N-well++Injecting into a leakage channel formed when different potentials are applied between the substrates; meanwhile, the N trap and the clamping photodiode are isolated by using the deep groove isolation filled with the fixed charge layer, so that the noise of the pixel is reduced, the electric leakage is reduced, and the performance of the image sensor is improved.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. An anti-creeping deep depletion image sensor pixel unit structure is characterized by comprising: are arranged in parallel at a P-An N-well and a photodiode on the front side of the silicon substrate, a deep trench isolation provided between the N-well and the photodiode, and a P-well-P on the back side of a silicon substrate++Injecting a substrate layer; wherein the deep trench is isolated at the P-The depth in the silicon substrate is greater than the injection depth of the N trap and the photodiode so as to electrically isolate the N trap and the photodiode, and the potential of the trap of the N trap is connected with a power supply voltage so as to connect the P++Implanting a substrate layer with a negative bias to form a channel between the N-well and the P-Silicon substrate and P++And a reverse biased PN junction is formed between the injected substrate layers.
2. The anti-creeping deep depletion image sensor pixel unit structure of claim 1, wherein a fixed charge layer is provided along the inner wall surface of the deep trench isolation.
3. The anti-creeping deep depletion image sensor pixel unit structure of claim 2, wherein the fixed charge layer has a negative fixed charge for the P outside the deep trench isolation-A positive charge is induced in the silicon substrate.
4. The anti-creeping deep depletion image sensor pixel unit structure of claim 2, wherein the fixed charge layer material is a high dielectric constant material.
5. The anti-creeping deep depletion image sensor pixel unit structure according to claim 2, wherein the fixed charge layer material is hafnium oxide or zirconium oxide.
6. The anti-creeping deep depletion image sensor pixel unit structure of claim 1, wherein the photodiode is a clamped photodiode.
7. The anti-creeping deep depletion image sensor pixel unit structure according to claim 1, further comprising: is arranged at the P-A transfer tube and a floating drain on the front side of the silicon substrate.
8. A method for manufacturing an anti-creeping deep depletion image sensor pixel unit structure is characterized by comprising the following steps:
providing a P-A silicon substrate on the P-Forming a trench structure isolated by a deep trench on the front surface of the silicon substrate, and enabling the depth of the trench to be greater than the maximum injection depth of an N well to be formed and a photodiode;
depositing a fixed charge layer on the surface of the inner wall of the groove and enabling the fixed charge layer to have negative fixed charges;
filling a dielectric layer in the groove to form a deep groove isolation structure;
the P on both sides of the deep trench isolation by photolithography and ion implantation-Respectively forming an N well and a photodiode on the front surface of the silicon substrate, and enabling the depth of the N well and the depth of the photodiode to be smaller than the depth of the deep groove isolation;
using conventional procedures, in said P-A transmission tube and a suspended drain electrode of the pixel unit are formed on the front surface of the silicon substrate;
the P is added-Thinning the back of the silicon substrate to the required thickness;
the P after thinning is processed by an injection and annealing process-Forming P on the back surface of the silicon substrate++And injecting the substrate layer.
9. The method of claim 8, wherein the photodiode is a clamped photodiode.
10. The method of claim 8, wherein the fixed charge layer is made of hafnium oxide or zirconium oxide, and the hafnium oxide or zirconium oxide is negatively charged by adjusting a process recipe.
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| CN113363273A (en) * | 2021-05-31 | 2021-09-07 | 武汉新芯集成电路制造有限公司 | Photosensitive array and imaging device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113363273A (en) * | 2021-05-31 | 2021-09-07 | 武汉新芯集成电路制造有限公司 | Photosensitive array and imaging device |
| CN113363273B (en) * | 2021-05-31 | 2023-11-24 | 武汉新芯集成电路制造有限公司 | Photosensitive array and imaging device |
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