CN110931578A

CN110931578A - Photoelectric detector

Info

Publication number: CN110931578A
Application number: CN201910594827.2A
Authority: CN
Inventors: 罗文勋; 徐英杰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2018-09-20
Filing date: 2019-07-03
Publication date: 2020-03-27

Abstract

A photodetector is provided. The photodetector includes a first well having a first doping type disposed in a semiconductor substrate. A second well having a second doping type opposite to the first doping type is provided in the semiconductor substrate on one side of the first well. A first doped buried region having a second doping type is disposed in the semiconductor substrate, wherein the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having a second doping type is disposed in the semiconductor substrate in a vertical direction between the first doped buried region and the first well, wherein the second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

Description

Photoelectric detector

Technical Field

The embodiment of the invention relates to a photoelectric detector.

Background

Many of today's electronic devices, such as smart phones (smartphones), digital cameras (digital cameras), biomedical imaging devices (biomedical imaging devices), automated imaging devices (automated imaging devices), and the like, include image sensors. The image sensor includes one or more photodetectors (e.g., photodiodes (photodiodes), phototransistors (phototransistors), photoresistors (photoresistors), etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation. Some types of image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared with a CCD image sensor, a CMOS image sensor is favored because of low power consumption, small size, fast data processing, direct data output, and low manufacturing cost. Some types of CMOS image sensors include front-side illuminated (FSI) image sensors and backside illuminated (BSI) image sensors.

Disclosure of Invention

Embodiments of the present invention provide a photodetector that includes a first well, a second well, a first doped buried region, and a second doped buried region. The first well includes a first doping type and is disposed in the semiconductor substrate. The first well extends into the semiconductor substrate from a first side of the semiconductor substrate. The second well is disposed in the semiconductor substrate on one side of the first well. The second well includes a second doping type, the second doping type being opposite to the first doping type. The second well extends into the semiconductor substrate from the first side of the semiconductor substrate. The first doped buried region includes a second doping type and is disposed in the semiconductor substrate. A first doped buried region extends laterally through the semiconductor substrate under the first well and the second well. The second doped buried region includes a second doping type. A second doped buried region is disposed in the semiconductor substrate and is disposed between the first doped buried region and the first well in a vertical direction. The second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

An embodiment of the present invention provides a method of forming a photodetector, including: forming a first doped buried region comprising a first doping type in a semiconductor substrate; forming a second doped buried region comprising the first doping type over the first doped buried region, wherein the second doped buried region is formed to comprise a concentration of the first doping type different from the first doped buried region; forming a pair of first wells comprising the first doping type in the semiconductor substrate over the second doped buried region, wherein the pair of first wells are laterally spaced apart; forming a second well comprising a second doping type over the second doped buried region in the semiconductor substrate, the second doping type being opposite to the first doping type, wherein the second well is formed between the pair of first wells, and wherein a bottom of the second well contacts a top of the second doped buried region such that a photodetector p-n junction exists along the bottom of the second well and the top of the second doped buried region; forming a pair of first electrodes including a first doping type in a semiconductor substrate, wherein the pair of first electrodes are respectively formed in a pair of first wells; and forming a second electrode including a second doping type in the second well.

Embodiments of the present invention provide a photodetector that includes a pair of first wells, a second well, a pair of cathodes, an anode, a first doped buried region, and a second doped buried region. The first wells comprise a first doping type and are disposed in an epitaxial structure, wherein a pair of the first wells are laterally spaced apart and the epitaxial structure is disposed on the first layer of semiconductor material. The second well is disposed in the epitaxial structure between the pair of first wells. The second well includes a second doping type opposite the first doping type. A pair of cathodes is disposed in the epitaxial structure, wherein the pair of cathodes is disposed in the pair of first wells, respectively. An anode is disposed in the second well. The first doped buried region includes a first doping type and is disposed in the first semiconductor material layer. A first doped buried region extends laterally through the first layer of semiconductor material under the pair of cathode and anode. The second doped buried region includes the first doping type. A second doped buried region is disposed in the epitaxial structure and the first layer of semiconductor material between the first doped buried region and the second well. The second doped buried region has a lower concentration of the first doping type than the first doped buried region. The second doped buried region contacts the second well such that a photodetector p-n junction exists along the second doped buried region and the second well.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates a cross-sectional view of some embodiments of a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

Fig. 2 shows a cross-sectional view of some more detailed embodiments of the CMOS image sensor shown in fig. 1.

Fig. 3 illustrates a cross-sectional view of some alternative embodiments of the CMOS image sensor shown in fig. 2.

Fig. 4 through 15 illustrate a series of cross-sectional views of some embodiments of a method of forming the CMOS image sensor of fig. 3.

Figure 16 illustrates a flow diagram of some embodiments of a method of forming the CMOS image sensor illustrated in figure 3.

Detailed Description

The present disclosure will now be described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the structures shown are not necessarily drawn to scale. It should be understood that this detailed description and the corresponding drawings are not intended to limit the scope of the disclosure in any way, and that they are merely provided as examples to illustrate some of the ways in which the inventive concepts may be made apparent.

The present disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature "over" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of illustration, spatially relative terms such as "below …", "below", "lower", "above …", "upper", and the like may be used herein to describe one element or feature's relationship to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Some Complementary Metal Oxide Semiconductor (CMOS) image sensors include a single-photon avalanche diode (SPAD) disposed in a semiconductor substrate. SPADs are photodetectors configured to absorb incident radiation (e.g., near-infrared (NIR) radiation) and output an electrical signal having a relatively large avalanche current compared to the amount of photo-generated charge carriers (charge carriers) generated in the photodetector (e.g., due to absorption of photons). The SPAD includes a pair of first wells having a first doping type (e.g., n-type doping) disposed in a semiconductor substrate. A second well having a second doping type (e.g., p-type doping) opposite the first doping type is disposed in the semiconductor substrate between the first wells. A doped buried layer extending between the first wells is disposed in the semiconductor substrate below the second wells. The second well contacts the doped buried layer in a vertical direction between the first wells. Thus, there is a p-n junction between the second well and the doped buried layer. Thus, a depletion region (depletion region) is formed along the second well and the doped buried layer (e.g., due to a p-n junction between the second well and the doped buried layer).

One challenge facing CMOS image sensors is the Photon Detection Probability (PDP). For CMOS image sensors that include near-infrared SPADs (NIR-SPADs), a PDP is the probability that a NIR-SPAD will successfully detect (e.g., output an electrical signal) a given input (e.g., on the order of a single photon) that propagates through space at near-infrared (NIR) wavelengths (e.g., between about 750 nanometers (nm) and about 2.5 microns (μm)). One possible solution for improving NIR-SPAD PDP is: the p-n junction between the second well and the doped buried region is arranged deeper in the semiconductor substrate (e.g., spaced further from the surface of the semiconductor substrate) than in a shallow p-n junction NIR-SPAD (e.g., an NIR-SPAD having a p-n junction disposed near the surface of the semiconductor substrate).

A p-n junction set deeper in the semiconductor substrate may improve the PDP of the NIR-SPAD due to the NIR radiation penetrating deeper into the semiconductor substrate and having a higher impact ionization rate (e.g. due to the wavelength of the NIR radiation), since the depletion region of the NIR-SPAD is arranged in a portion of the semiconductor substrate where the probability of transferring photo-generated charge carriers to the depletion region is higher. Accordingly, the CMOS image sensor may have an improved PDP. However, by placing the p-n junction between the second well and the doped buried region deeper in the semiconductor substrate, timing resolution of the CMOS image sensor may be negatively impacted.

For CMOS image sensors including NIR-SPAD, timing resolution is the statistical uncertainty that occurs when measuring the electrical signal output by NIR-SPAD. For example, if the timing resolution is zero, each electrical signal output by the NIR-SPAD will be output at the expected output signal time based on the time that the photogenerated charge carriers are generated in the NIR-SPAD. One factor that negatively impacts timing resolution is that photogenerated charge carriers may be generated in the semiconductor substrate at different locations between the top of the second well and the doped buried layer. The time taken for the photogenerated charge carriers to travel from the different locations to the depletion region is proportional to the distance of the photogenerated charge carrier generation location from the depletion region. The NIR-SPAD may output an electrical signal that deviates from the expected output signal time (e.g., occurs before or after) depending on the location of generation of photo-generated charge carriers (e.g., in, near, or relatively far from the depletion region). Thus, as the p-n junction is disposed deeper in the semiconductor substrate, the performance of the CMOS image sensor may be degraded by timing resolution because of the increased minimum distance from the depletion region in which the NIR-SPAD can detect a given input signal (e.g., with respect to signal photons).

In various embodiments, the present application relates to a CMOS image sensor having a second doped buried region disposed between a first doped buried region having a first doping type and a first well having a second doping type opposite the first doping type, the second doped buried region having the first doping type. The first well is disposed in the semiconductor substrate. A first doped buried region is disposed in the semiconductor substrate below the first well. A second doped buried region is disposed in the semiconductor substrate between the first wells. The second doped buried region contacts the first well.

Since the second doped buried region contacts the first well and has an opposite doping type to the first well, there is a p-n junction between the second doped buried region and the first well. Thus, a depletion region is formed along the second doped buried region and the first well. Since the depletion region is disposed along the second doped buried region and the first well, the depletion region is disposed more centrally in the semiconductor substrate between the first doped buried layer and the top of the first well, while the depletion region may still be disposed deeper in the semiconductor substrate than in a CMOS image sensor having a shallow p-n junction NIR-SPAD. Since the depletion region is disposed deeper in the semiconductor substrate than in the CMOS image sensor having the shallow p-n junction NIR-SPAD, the CMOS image sensor of the present application may have an improved PDP compared to the CMOS image sensor having the shallow p-n junction NIR-SPAD. Furthermore, since the depletion region is disposed more centrally in the semiconductor substrate between the first doped buried layer and the top of the first well, the different locations at which photogenerated charge carriers may be generated may be more evenly spaced apart in or from the depletion region. Thus, the CMOS image sensor of the present application may have improved timing resolution due to the more uniform time it takes for photo-generated charge carriers to travel from the different locations to the depletion region.

Fig. 1 illustrates a cross-sectional view of some embodiments of a Complementary Metal Oxide Semiconductor (CMOS) image sensor 100, the CMOS image sensor 100 having a second doped buried region disposed between a first doped buried region having a first doping type and a first well having a second doping type opposite the first doping type, the second doped buried region having the first doping type.

As shown in fig. 1, the CMOS image sensor 100 includes a semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 may include any type of semiconductor body (e.g., single crystal silicon/bulk cmos (cmos bulk), silicon germanium (SiGe), Silicon On Insulator (SOI), etc.).

A pair of first wells 104 is provided in the semiconductor substrate 102. The first wells 104 are laterally spaced apart from each other and extend into the semiconductor substrate 102 from a first side of the semiconductor substrate 102, respectively. In some embodiments, the first well 104 is a region of the semiconductor substrate 102 that includes a first doping type (e.g., n-type doping). In still other embodiments, the first well 104 may be a single well that is annular in shape when viewed from above.

A pair of first electrodes 106 is provided in the semiconductor substrate 102. First electrodes 106 are respectively disposed in the first wells 104. In some embodiments, the first electrode 106 is a region of the semiconductor substrate 102 that includes a first doping type (e.g., n-type doping). In other embodiments, the first electrode 106 has a higher concentration of the first doping type than the first well 104. In still other embodiments, the first electrode 106 may be a cathode.

A second well 108 is disposed in the semiconductor substrate 102 between the first wells 104. In some embodiments, the second well 108 is a region of the semiconductor substrate 102 that includes a second doping type (e.g., p-type doping) that is opposite the first doping type. In other embodiments, the second well 108 extends into the semiconductor substrate from the first side of the semiconductor substrate 102. In still other embodiments, the first well 104 may be spaced apart from the second well 108 on opposite sides of the second well 108, respectively. In such an embodiment, lightly doped regions 109 may separate the first well 104 from the second well 108, respectively. In some embodiments, the lightly doped region 109 is a region of the semiconductor substrate 102 that includes a second doping type (e.g., p-type doping). In other embodiments, the lightly doped region 109 has a concentration of the second doping type lower than the second well 108. In other embodiments, the lightly doped region 109 is an intrinsic region (e.g., undoped) of the semiconductor substrate 102.

A second electrode 110 is disposed in the second well 108. In some embodiments, the second electrode 110 is a region of the semiconductor substrate 102 that includes a second doping type (e.g., p-type doping). In other embodiments, the second electrode 110 has a higher concentration of the second doping type than the second well 108. In still other embodiments, the second electrode 110 may be an anode.

A first doped buried region 112 is disposed in the semiconductor substrate 102 below the first well 104 and the second well 108. In some embodiments, the first doped buried region 112 is a region of the semiconductor substrate 102 that includes a first doping type (e.g., n-type doping). In other embodiments, the first doped buried region 112 is vertically spaced apart from the first well 104 and the second well 108. In still other embodiments, the first doped buried region 112 extends laterally through the semiconductor substrate 102 under the first well 104 and the second well 108.

In some embodiments, the first doped buried region 112 is disposed above the semiconductor region 113. In some embodiments, the semiconductor region 113 is a region of the semiconductor substrate 102 that includes a second doping type (e.g., p-type doping). In other embodiments, the semiconductor region 113 has a concentration of the second doping type lower than the second well 108. In still other embodiments, the semiconductor region 113 has a concentration of the second doping type substantially similar to the lightly doped region 109. In other embodiments, the semiconductor region 113 is an intrinsic region (e.g., undoped) of the semiconductor substrate 102.

A second doped buried region 114 is disposed in the semiconductor substrate 102 between the first doped buried region 112 and the second well 108. In some embodiments, the second doped buried region 114 is a region of the semiconductor substrate 102 that includes a first doping type (e.g., n-type doping). In some embodiments, the second doped buried region 114 has a concentration of the first doping type that is different from the first doped buried region 112. In other embodiments, the second doped buried region 114 has a lower concentration of the first doping type than the first doped buried region 112. In still other embodiments, the second doped buried region 114 extends laterally through the semiconductor substrate 102 above the first doped buried region 112 and below the first well 104 and the second well 108.

In still other embodiments, the second doped buried region 114 contacts the first doped buried region 112, the first well 104, and the second well 108. Since the second doped buried region 114 has a different doping type than the second well 108 and contacts the second well 108, there is a p-n junction between the second doped buried region 114 and the second well 108. Thus, a depletion region 116 having a built-in electric field (build-in electric field) is formed along the second well 108 and the second doped buried region 114.

In some embodiments, the photodetector 118 includes a first well 104, a second well 108, and a second doped buried region 114. The photodetector 118 is configured to absorb incident radiation 120 (e.g., photons) and output an electrical signal corresponding to the incident radiation. In some embodiments, the photodetector 118 is configured to absorb incident radiation 120 having a Near Infrared (NIR) wavelength, for example, between about 750 nanometers (nm) and about 2.5 micrometers (μm). In some embodiments, the photodetector 118 may be, for example, a photodiode, a phototransistor, a photoresistor, and the like. More specifically, in some embodiments, the photodetector 118 may be, for example, an Avalanche Photodiode (APD) or a single photon avalanche photodiode (SPAD).

In some embodiments, during operation of the CMOS image sensor 100, an external reverse bias voltage greater than the avalanche breakdown voltage of the photodetector 118 is applied to the photodetector 118 (e.g., by applying a positive voltage to the first electrode 106 and a negative voltage to the second electrode 110). Since the photodetector 118 absorbs incident radiation 120 (e.g., photons), different locations L may be present throughout the photodetector 118_ATo L_DTo form photo-generated charge carriers. In some embodiments, the different position L_ATo L_DIncluding a first position L_AA second position L_BA third position L_CAnd a fourth position L_D. In other embodiments, if the distance between the top of the first doped buried region 112 and the top surface of the semiconductor substrate 102 is x, the first location L_ACan be disposed about 0.01x to about 0.45x from the top surface of the semiconductor substrate 102, a second location L_BMay be disposed about 0.46x to about 0.57x from the top surface of the semiconductor substrate 102, a third location L_CMay be disposed about 0.58x to about 0.86x from the top surface of the semiconductor substrate 102, and a fourth location L_DMay be disposed about 0.87x to about 0.97x from the top surface of the semiconductor substrate 102. In still other embodiments, the distance between the top of the first doped buried region 112 and the top surface of the semiconductor substrate 102 may be between about 2.5 μm and about 4.5 μm.

In some embodiments, a single photogenerated charge carrier (e.g., generated as a result of absorption of a photon by the photodetector 118) may be generated from the different location L due to an external reverse bias applied to the photodetector 118 that is greater than the avalanche breakdown voltage_ATo L_DOne of which is transmitted to the depletion region 116 so that the photodetector 118 outputs an electrical signal having an avalanche current. In some embodiments, the photodetector 118 outputs an electrical signal with an avalanche current due to the built-in electric field of the depletion region 116 sweeping the photogenerated charge carriers from the p-n junction between the second doped buried region 114 and the second well 108, triggering self-sustaining avalanche (self-sustaining avalanche). In other embodiments, the photodetector 118 may output an electrical signal to a quenching circuit (not shown)Shown) (e.g., a passive circuit or an active circuit) configured to sense the electrical output and restore the photodetector 118 to its operating state (pre-electrical signal output operating condition) prior to the electrical signal output.

Since the second doped buried region 114 is disposed between the second well 108 and the first doped buried region 112 and contacts the second well 108, a depletion region 116 (e.g., formed due to a p-n junction between the second well 108 and the second doped buried region 114) may be formed approximately midway between the bottom of the second electrode 110 and the top of the first doped buried region 112. Since the depletion region 116 is formed approximately midway between the bottom of the second electrode 110 and the top of the first doped buried region 112, the first location L_AAnd a fourth position L_DApproximately uniformly spaced from the depletion region 116. Thus, photogenerated charge carriers are transported from the first location L_AOr a fourth position L_DThe time taken to transfer to the depletion region is about the same. Therefore, the timing resolution of the CMOS image sensor 100 can be improved. Furthermore, because the depletion region is disposed along the second doped buried region 114 and the second well 108, the depletion region 116 may be disposed deeper in the semiconductor substrate 102 than in a CMOS image sensor having a shallow p-n junction NIR-SPAD (e.g., an NIR-SPAD having a p-n junction disposed near the surface of the semiconductor substrate). Accordingly, the CMOS image sensor 100 may have an improved Photon Detection Probability (PDP) compared to a CMOS image sensor having a shallow p-n junction NIR-SPAD since the depletion region 116 is disposed deeper in the semiconductor substrate 102 than in a CMOS image sensor having a shallow p-n junction NIR-SPAD.

As shown in fig. 2, the second well 108 is disposed between the first wells 104 in the semiconductor substrate 102. In some embodiments, opposing sides of the second well 108 may be laterally spaced apart by about 4 μm to about 18 μm. In some embodiments, the second doped buried region 114 is disposed between the first doped buried region 112 and the second well 108. In other embodiments, the first doped buried region 112 has a higher concentration of the first doping type than the second doped buried region 114. In still other embodiments, the second doped buried region 114 has a higher concentration of the first doping type than the first well 104.

A pair of third wells 202 is provided in the semiconductor substrate 102. The third well 202 is a region of the semiconductor substrate 102 having a first doping type (e.g., n-type doping). In some embodiments, the third wells 202 are respectively disposed in the first wells 104. In some embodiments, third wells 202 separate first electrodes 106 from first wells 104, respectively. In some embodiments, the third wells 202 are separated from the second doped buried regions 114 by the first wells 104, respectively. In other embodiments, third well 202 has a higher concentration of the first doping type than first well 104. In still other embodiments, the third well 202 has a concentration of the first doping type lower than the first electrode 106.

A pair of first pickup wells (pick-up wells) 204 are provided in the semiconductor substrate 102. The pickup well 204 is a region of the semiconductor substrate 102 having a second doping type (e.g., p-type doping). In some embodiments, the first pickup well 204 is configured to provide a bias voltage to the semiconductor substrate 102. In other embodiments, the first wells 104 separate the first pickup wells 204 from the second wells 108, respectively. In other embodiments, the first pickup wells 204 are laterally spaced apart from the second wells 108, respectively. In still other embodiments, the lightly doped region 109 has a concentration of the second doping type that is lower than the first pickup well 204.

In some embodiments, the bottoms of the first pickup wells 204 may be disposed below the bottoms of the first wells 104, respectively. In other embodiments, the bottom of the first pickup well 204 may be disposed between the bottom of the first doped buried region 112 and the top of the first doped buried region 112. In some embodiments, the first pickup wells 204 may contact the first wells 104, respectively. In other embodiments, the first pickup well 204 may also contact the first and second doped buried

regions

112 and 114. In such an embodiment, the sides of the first pickup well 204 facing the second well 108 may contact the second and first doped buried

regions

114, 112, respectively, below the bottom of the first well 104 and contact the first well 104, respectively, above the bottom of the first well 104.

A pair of second pickup wells 206 is provided in the semiconductor substrate 102. The second pickup well 206 is a region of the semiconductor substrate 102 having a second doping type (e.g., p-type doping). In some embodiments, the second pickup wells 206 are disposed in the first pickup wells 204, respectively. In other embodiments, the second pickup well 206 has a higher concentration of the second doping type than the first pickup well 204. In still other embodiments, the first pickup wells 204 separate the second pickup wells 206 from the first wells 104, respectively.

A pair of pickup well contacts 208 is provided in the semiconductor substrate 102. The pickup well contact 208 is a region of the semiconductor substrate 102 having a second doping type (e.g., p-type doping). In some embodiments, the pickup well contacts 208 are disposed in the second pickup wells 206, respectively. In some embodiments, the second pickup well 206 may separate the pickup well contacts 208 from the first pickup well 204, respectively. In other embodiments, the pickup well contact 208 may have a higher concentration of the second doping type than the second pickup well 206. In still other embodiments, a silicide structure (not shown) may be disposed on the pickup well contact 208.

A plurality of isolation structures 210 are disposed in the semiconductor substrate 102. The isolation structure 210 may be, for example, a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, or the like. In some embodiments, some of the isolation structures 210 are disposed between the first electrode 106 and the first pickup well contact 208, respectively. In some embodiments, portions of the first well 104, the third well 202, the first pickup well 204, the second pickup well 206, the first doped buried region 112, and/or the second doped buried region 114 may be disposed directly below the ones of the isolation structures 210. In such an embodiment, the first well 104 may contact the first pickup well 204 under the some of the isolation structures 210. In other such embodiments, the sides of some of the isolation structures 210 may be laterally spaced apart from the sides of the first well 104 by about 0.2 μm to about 1.0 μm. In still other such embodiments, the first doped buried region 112 and/or the second doped buried region 114 may contact the first pickup well 204 under the ones of the isolation structures 210. In some embodiments, some other ones 210 of the isolation structures 210 are disposed on opposite sides of the first pickup well contact 208 from the second well 108, respectively. In such embodiments, portions of the first pickup well 204 and/or portions of the second pickup well 206 may be disposed directly below some of the isolation structures 210.

An interlayer dielectric (ILD) layer 212 is disposed over the semiconductor substrate 102, the first well 104, the second well 108, and the first pickup well 204. In some embodiments, ILD layer 212 may have a substantially planar upper surface. In other embodiments, ILD layer 212 includes one or more of the following: low dielectric constant (low-k) dielectric layers (e.g., dielectric having a dielectric constant less than about 3.9), ultra-low dielectric constant dielectric layers, oxides (e.g., SiO)₂) And the like. In addition, a plurality of conductive contacts 214 are disposed in the ILD layer 212. In some embodiments, the conductive contact 214 extends through the ILD layer 212 to contact the first electrode 106, the second electrode 110, and/or the pickup well contact 208, respectively.

An inter-metal dielectric (IMD) layer 216 is disposed on ILD layer 212 and conductive contact 214. In some embodiments, IMD layer 216 includes one or more of: low dielectric constant dielectric layers, ultra-low dielectric constant dielectric layers, oxides, and the like. In addition, a plurality of conductive features 218 (e.g., conductive lines and/or vias) are disposed in IMD layer 216. In some embodiments, a plurality of IMD layers 216 may be stacked on ILD layer 212, and additional conductive features 218 may be disposed in each of the plurality of IMD layers 216. In such an embodiment, about 4 to about 10 IMD layers 216 may be stacked on ILD layer 212 to reduce light attenuation (light attenuation) caused by the plurality of IMD layers 216 and conductive features 218 respectively disposed in the plurality of IMD layers 216.

A passivation layer 220 is disposed over IMD layer 216 and conductive feature 218. In some embodiments, the passivation layer 220 may comprise, for example, an oxide, nitride, oxynitride, polymer, or the like. In other embodiments, interconnect structure 222 may include ILD layer 212, conductive contact 214, IMD layer 216, conductive feature 218, and passivation layer 220. In still other embodiments, the interconnect structure 222 is configured to provide electrical connections between various devices disposed throughout the CMOS image sensor 100.

As shown in fig. 3, the semiconductor substrate 102 includes an epitaxial structure 302 disposed on a first layer of semiconductor material 304. In some embodiments, the first semiconductor material layer 304 comprises a crystalline semiconductor material (e.g., a single crystal silicon wafer, silicon, gallium arsenide wafer, etc.). In some embodiments, the first layer of semiconductor material 304 is intrinsic (e.g., undoped). In other embodiments, the first semiconductor material layer 304 may include a second doping type (e.g., p-type doping). In some embodiments, the epitaxial structure 302 includes a second doping type. In some embodiments, the epitaxial structure region 305 separates the first well 104 from the second well 108. In other embodiments, the epitaxial structure 302 may be intrinsic. In other embodiments, the epitaxial structure 302 may have a resistivity between about 6 ohm-centimeters (ohm-centimeters) and about 14 ohm-centimeters. In still other embodiments, the epitaxial structure 302 may have a thickness between about 3 μm and about 7 μm.

In some embodiments, the second doped buried region 114 is disposed in both the epitaxial structure 302 and the first layer of semiconductor material 304. In some embodiments, the first doped buried region 112 is disposed in the first layer of semiconductor material 304. In other embodiments, the first well 104, the third well 202, the first electrode 106, the first pickup well 204, the second pickup well 206, the pickup well contact 208, the isolation structure 210, the second well 108, and the second electrode 110 are disposed in the epitaxial structure 302. In still other embodiments, the bottom of the second doped buried region 114 is disposed below the bottom of the first pickup well 204.

In some embodiments, the isolation structures 210 include an isolation structure liner (liner)306 and an isolation structure dielectric 308, respectively. Isolation structure dielectric308 are respectively disposed on the spacer structure liners 306. In some embodiments, an isolation structure liner 306 separates the isolation structure dielectric 308 from the epitaxial structure 302, respectively. In other embodiments, the isolation structure liner 306 may comprise, for example, a nitride, an oxide, an oxynitride, or the like. In still other embodiments, the isolation structure dielectric 308 may comprise an oxide (e.g., SiO)₂)。

In some embodiments, a microlens 310 is disposed on the passivation layer 220. The microlenses are configured to focus incident radiation (e.g., photons) toward the photodetectors 118. In other embodiments, the microlenses 310 may be disposed on the backside of the semiconductor substrate 102 (e.g., on a side of the semiconductor substrate 102 opposite the side of the semiconductor substrate 102 on which the interconnect structures 222 are disposed).

As shown in fig. 4, a first doped buried region 112 is formed in the first layer of semiconductor material 304. The first doped buried region 112 is a region of the first layer of semiconductor material 304 that includes a first doping type (e.g., n-type doping). In some embodiments, the first doped buried region 112 may be formed by a first selective ion implantation process (selective ion implantation process) that selectively implants ions into the first semiconductor material layer 304 using a masking layer (not shown).

In some embodiments, the first selective ion implantation for forming the first doped buried region 112 may include implanting ions at an energy of between about 50 kiloelectron volts (keV) and about 150keV to about 5.0 x 10¹⁴Ion/cm²And about 5.0X 10¹⁵Ion/cm²Antimony ions are implanted into the first semiconductor material layer 304 at a dosage in between. In some embodiments, the first selective ion implantation for forming the first doped buried region 112 may also include implanting ions at an ion energy between about 30keV and about 100keV to about 1.0 x 10¹³Ion/cm²And about 1.0X 10¹⁵Ion/cm²Between the dosage of phosphorus ion implantationInto the first semiconductor material layer 304. In other embodiments, a first drive-in anneal (e.g., Rapid Thermal Anneal (RTA), furnace anneal (burn anneal), etc.) may be performed on the first layer of semiconductor material 304 to activate the ions implanted by the first selective ion implantation. In still other embodiments, the first drive-in anneal may be included in nitrogen (N)₂) The first layer of semiconductor material 304 is heated to a temperature between about 900 c and about 1200 c for about 30 minutes to about 130 minutes in an ambient.

As shown in fig. 5, an initial doped layer 502 is formed in the first layer of semiconductor material 304 and over the first doped buried region 112. The initially doped layer 502 is a region of the first layer of semiconductor material 304 that includes a first doping type (e.g., n-type doping). In some embodiments, the initially doped layer 502 is formed to have a concentration of the first doping type that is lower than the first doped buried region 112. In some embodiments, the initial doped layer 502 may be formed by a second selective ion implantation process 504, the second selective ion implantation process 504 utilizing a masking layer (not shown) to selectively implant ions into the first doped buried region 112. In other embodiments, the second selective ion implantation process 504 may include implanting ions having an energy between about 5.0 x 10 at an ion energy between about 20keV and about 100keV¹³Ion/cm²And about 1.0X 10¹⁵Ion/cm²With a dosage of phosphorus ions implanted into the first doped buried region 112.

As shown in fig. 6, an epitaxial structure 302 is formed on the first layer of semiconductor material 304 and the initially doped layer 502. In some embodiments, the epitaxial structure 302 may be formed to have a resistivity between about 6 ohm-centimeters and about 14 ohm-centimeters. In some embodiments, the epitaxial structure 302 may have a thickness between about 3 μm and about 7 μm. In other embodiments, epitaxial structure 302 may be formed by, for example, vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), solid-phase epitaxy (SPE), reduced pressure chemical vapor deposition (RP-CVD) epitaxy, Metal Organic Vapor Phase Epitaxy (MOVPE), or similar epitaxy processes. In still other embodiments, a planarization process (e.g., chemical-mechanical planarization (CMP)) may be performed on the upper surface of the epitaxial structure 302 to form a planar upper surface. In some embodiments, the semiconductor substrate 102 includes an epitaxial structure 302 and a first layer of semiconductor material 304.

As shown in fig. 7, a plurality of trenches 702 are formed in the epitaxial structure 302. In some embodiments, trenches 702 are laterally spaced apart and extend into epitaxial structure 302 from a first side of epitaxial structure 302, respectively. In some embodiments, some of the trenches 702 at least partially vertically overlap the first doped buried region 112.

In some embodiments, the process of forming the trench 702 includes etching (e.g., dry etching and/or wet etching) the epitaxial structure 302. In some embodiments, the etching may be performed using the isolation structure patterned stack 704 formed on the epitaxial structure 302. In some embodiments, the isolation structure patterned stack 704 may include a nitride layer disposed over the epitaxial structure 302 and a mask layer disposed on the nitride layer. Epitaxial structure 302 is then exposed to one or more etchants that remove portions of the nitride layer of isolation structure patterned stack 704 not covered by the mask layer and portions of epitaxial structure 302 not covered by the mask layer to form trench 702. Subsequently, the masking layer of the isolation structure patterned stack 704 may be removed. In still other embodiments, the patterned stack of isolation structures may be formed on the epitaxial structure 302 using one or more deposition processes (e.g., Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), thermal oxidation (thermal oxidation), sputtering (sputtering), etc.).

Fig. 7 also illustrates the formation of isolation structure liners 306 that line trenches 702, respectively. The isolation structure liner 306 may comprise, for example, a nitride, an oxide, an oxynitride, or the like. In some embodiments, the isolation structure liner 306 may be deposited and/or grown on the epitaxial structure 302 by, for example, thermal oxidation, CVD, PVD, ALD, sputtering, and the like. In some embodiments, after forming the isolation structure liners 306 in the trenches 702, respectively, an isolation structure liner anneal 706(RTA, furnace anneal, etc.) may be performed on the semiconductor substrate 102 to reduce defects at the interface between the isolation structure liners 306 and the epitaxial structure 302. In other embodiments, the isolation structure liner anneal 706 may include heating the semiconductor substrate 102 to a temperature between about 900 ℃ and about 1200 ℃ for about 200 minutes to about 300 minutes. In still other embodiments, the isolation structure liner anneal 706 also diffuses ions of the initially doped layer 502 into the epitaxial structure 302 to form the second doped buried region 114.

As shown in fig. 8, an isolation structure dielectric 308 is formed in the trench 702 and on the isolation structure liner 306, respectively, to form a plurality of isolation structures 210 in the epitaxial structure 302. In some embodiments, the isolation structure dielectric 308 may comprise an oxide (e.g., SiO)₂). In other embodiments, the isolation structure dielectric 308 has an upper surface that is coplanar with an upper surface of the isolation structure liner 306 and an upper surface of the epitaxial structure 302.

In some embodiments, the process of forming the isolation structure dielectric 308 includes depositing and/or growing (e.g., by CVD, PVD, ALD, thermal oxidation, sputtering, etc.) an isolation structure dielectric layer (not shown) on the isolation structure liner 306 and on the nitride layer of the isolation structure patterned stack 704 such that the isolation structure dielectric layer fills the trench 702. Subsequently, a planarization process (e.g., CMP) is performed on the isolation structure dielectric layer to remove an excess portion of the isolation structure dielectric layer. In some embodiments, the planarization process may expose the nitride layer of the isolation structure patterned stack 704. After the planarization process, the nitride layer of the isolation structure patterned stack 704 may be stripped away.

As shown in fig. 9, a pair of first wells 104 are formed in the epitaxial structure 302. The first well 104 is a region of the epitaxial structure 302 that includes a first doping type (e.g., n-type doping). In some embodiments, the first well 104 is formed to have a concentration of the first doping type lower than the second doped buried typeAnd into zone 114. In some embodiments, first well 104 may be formed by a third selective ion implantation process that utilizes a masking layer (not shown) to selectively implant ions into epitaxial structure 302. In other embodiments, the third ion implantation process may include implanting ions having an energy between about 1.0 x 10 at between about 2200keV and about 2800keV¹²Ion/cm²And about 8.0X 10¹²Ion/cm²With a dose of phosphorus ions implanted into the epitaxial structure 302.

Fig. 9 also shows that a pair of first pickup wells 204 are formed in the epitaxial structure 302. The pickup well 204 is a region of the epitaxial structure 302 that includes a second doping type (e.g., p-type doping). In some embodiments, the pickup well 204 contacts the second doped buried region 114 and the first well 104, respectively. In some embodiments, the pickup well 204 may be formed by a fourth selective ion implantation process that utilizes a masking layer (not shown) to selectively implant ions into the epitaxial structure 302. In other embodiments, the fourth ion implantation process may include implanting ions having an energy between about 1.0 x 10 at an energy between about 400keV and about 800keV¹²Ion/cm²And about 5.0X 10¹²Ion/cm²With a dose of boron ions implanted into the epitaxial structure 302.

As shown in fig. 10, second wells 108 are formed in epitaxial structure 302 between first wells 104. The second well 108 is a region of the epitaxial structure 302 that includes a second doping type (e.g., p-type doping). In some embodiments, the second well 108 may be formed to have a higher concentration of the second doping type than the first pickup well 204. In other embodiments, the second well 108 may be formed to be laterally spaced apart from the first well 104. In still other embodiments, the photodetector 118 includes the first well 104, the second well 108, and the second doped buried region 114.

In some embodiments, the second well 108 may be formed by a fifth selective ion implantation process that utilizes a masking layer (not shown) to selectively implant ions into the epitaxial structure 302. In other embodiments, the fifth ion implantation process may includeWill be between about 1.0 x 10 at ion energies between about 1000keV and about 2000keV¹³Ion/cm²And about 1.0X 10¹⁴Ion/cm²With a dose of boron ions implanted into the epitaxial structure 302. In other embodiments, a second drive-in anneal (e.g., RTA, furnace anneal, etc.) may be performed on the semiconductor substrate 102 to activate the ions implanted by the third selective ion implantation process, the fourth selective ion implantation process, and/or the fifth selective ion implantation process. In still other embodiments, the second drive-in anneal may be included at N₂The first layer of semiconductor material 304 is heated to a temperature between about 800 ℃ and about 1200 ℃ for about 30 minutes to about 120 minutes in an ambient.

As shown in fig. 11, a pair of third wells 202 are formed in the epitaxial structure 302. The third well 202 is a region of the epitaxial structure 302 that includes a first doping type (e.g., n-type doping). In some embodiments, the third wells 202 are formed in the first wells 104, respectively. In some embodiments, third well 202 is formed to have a higher concentration of the first doping type than first well 104. In other embodiments, the third well 202 may be formed by a sixth selective ion implantation process that selectively implants ions into the epitaxial structure 302 using a masking layer (not shown).

Fig. 11 also shows that a pair of second pickup wells 206 are formed in the epitaxial structure 302. The second pickup well 206 is a region of the epitaxial structure 302 that includes a second doping type (e.g., p-type doping). In some embodiments, the second pickup wells 206 are formed in the first pickup wells 204, respectively. In some embodiments, the second pickup well 206 is formed to have a higher concentration of the second doping type than the first pickup well 204. In other embodiments, second pickup well 206 may be formed by a seventh selective ion implantation process that selectively implants ions into epitaxial structure 302 using a masking layer (not shown).

As shown in fig. 12, a pair of first electrodes 106 is formed in the epitaxial structure 302. The first electrode 106 is a region of the epitaxial structure 302 that includes a first doping type (e.g., n-type doping). In some embodiments, the first electrodes 106 are formed in the third wells 202, respectively. In other embodiments, the first electrode 106 may be formed to have a higher concentration of the first doping type than the third well 202. In still other embodiments, the first electrode 106 may be formed by an eighth selective ion implantation process that utilizes a masking layer (not shown) to selectively implant ions into the epitaxial structure 302.

Fig. 12 also shows that a second electrode 110 and a pair of pickup well contacts 208 are formed in the epitaxial structure 302. Second electrode and pickup well contact 208 is a region of epitaxial structure 302 that includes a second doping type (e.g., p-type doping). In some embodiments, the second electrode 110 may be formed to have a higher concentration of the second doping type than the second well 108. In some embodiments, the pickup well contact 208 may be formed to have a higher concentration of the second doping type than the second pickup well 206. In other embodiments, second electrode 110 and pickup well contact 208 may be formed by a ninth selective ion implantation process that utilizes a masking layer (not shown) to selectively implant ions into epitaxial structure 302. In other embodiments, the second electrode 110 and the pickup well contact 208 may be formed by separate ion implantation processes using separate mask layers (not shown). In still other embodiments, a silicide structure (not shown) (e.g., nickel silicide, titanium silicide, cobalt silicide, etc.) may be formed on first electrode 106, second electrode 110, and/or pickup well contact 208 by a suitable silicide process (e.g., a self-aligned silicide process).

As shown in fig. 13, an interlayer dielectric (ILD) layer 212 is formed on the epitaxial structure 302. In some embodiments, ILD layer 212 comprises one or more of the following: low dielectric constant dielectric layers, ultra-low dielectric constant dielectric layers, oxides, and the like. In other embodiments, ILD layer 212 may be deposited by, for example, CVD, PVD, ALD, sputtering, and the like. In still other embodiments, the ILD layer 212 may be subjected to a planarization process (e.g., CMP) to form a substantially planar upper surface.

Also shown in fig. 13, conductive contacts 214 are formed in ILD layer 212. In some embodiments, the process of forming the conductive contact 214 includes a first etch of the ILD layer 212 to form a contact opening corresponding to the conductive contact 214. In some embodiments, the etch may be performed using a mask layer (not shown) formed over ILD layer 212. In other embodiments, the process includes filling the contact openings with a conductive material (e.g., tungsten). In still other embodiments, the contact openings may be filled by: a conductive layer is deposited or grown (e.g., by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, etc.) to cover ILD layer 212 and fill the contact openings, and then a planarization process (e.g., CMP) is performed on ILD layer 212. In various embodiments, the process may be part of a single damascene-like process or a dual damascene-like process.

As shown in fig. 14, an inter-metal dielectric (IMD) layer 216 is formed on the ILD layer 212. In some embodiments, IMD layer 216 comprises a low-k dielectric layer, an ultra-low-k dielectric layer, or an oxide, for example. In some embodiments, IMD layer 216 may be deposited or grown on ILD layer 212 by, for example, CVD, PVD, ALD, sputtering, and the like. In other embodiments, IMD layer 216 may be subjected to a planarization process (e.g., CMP) to form a substantially planar upper surface.

A plurality of conductive features 218 (e.g., conductive lines and vias) are formed in IMD layer 216. In some embodiments, the process of forming conductive feature 218 includes etching IMD layer 216 to form a conductive feature opening. In some embodiments, the etch may be performed using a mask layer (not shown) formed over IMD layer 216. In some embodiments, the process includes filling the conductive feature openings with a conductive material (e.g., copper, aluminum, etc.). In other embodiments, the conductive feature openings may be filled by: a conductive layer is deposited or grown (e.g., by CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, etc.) to cover IMD layer 216 and fill the conductive feature openings, and then IMD layer 216 is planarized (e.g., CMP). In still other embodiments, a plurality of IMD layers 216 each having a plurality of conductive features 218 disposed in IMD layer 216 may be formed stacked on ILD layer 212. In such an embodiment, about 4 to about 10 IMD layers 216 may be stacked on ILD layer 212 to reduce optical attenuation caused by the plurality of IMD layers 216 and corresponding conductive features 218 disposed in IMD layers 216.

Fig. 14 also shows that a passivation layer 220 is formed over IMD layer 216 and some of conductive features 218. In some embodiments, the passivation layer 220 may comprise, for example, an oxide, nitride, oxynitride, polymer, or the like. In other embodiments, the passivation layer 220 may be formed by CVD, PVD, ALD, sputtering, spin on process (spin on process), and the like. In still other embodiments, interconnect structure 222 includes ILD layer 212, conductive contact 214, IMD layer 216, conductive feature 218, and passivation layer 220.

As shown in fig. 15, a microlens 310 is formed on the passivation layer 220. In some embodiments, the microlenses 310 can be formed by depositing (e.g., by a spin-on method or a deposition process) a microlens material on the passivation layer 220. A microlens template (not shown) having a curved upper surface is patterned over the microlens material. In other embodiments, the microlens template may comprise a photoresist material that is exposed, developed, and baked using a distributed exposure dose (e.g., for a negative photoresist, more light is exposed at the bottom of the flexures and less light is exposed at the top of the flexures) to form the rounded shape. In other embodiments, microlenses 310 are then formed by selectively etching the microlens material according to a microlens template. In still other embodiments, the microlenses 310 can be formed on the backside of the semiconductor substrate 102 (e.g., on a side of the semiconductor substrate 102 opposite the side of the semiconductor substrate 102 on which the interconnect structures 222 are disposed).

As shown in fig. 16, a flow chart 1600 of some embodiments of a method of forming the CMOS image sensor of fig. 3 is provided. While the flowchart 1600 shown in fig. 16 is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments described herein, and one or more of the acts illustrated herein may be performed in one or more separate acts and/or phases.

At act 1602, a first doped buried region comprising a first doping type is formed in a first layer of semiconductor material. Figure 4 illustrates a cross-sectional view of some embodiments corresponding to act 1602.

At act 1604, an initial doped buried layer comprising a first doping type is formed in the first doped buried layer. Figure 5 illustrates a cross-sectional view of some embodiments corresponding to act 1604.

At act 1606, an epitaxial structure is formed on the first layer of semiconductor material. Figure 6 illustrates a cross-sectional view of some embodiments corresponding to act 1606.

At act 1608, the epitaxial structure and the first layer of semiconductor material are annealed, which diffuses ions of the initial doped buried layer into the epitaxial structure to form a second doped buried region disposed above the first doped buried region. Figure 7 illustrates a cross-sectional view of some embodiments corresponding to act 1608.

At act 1610, isolation structures are formed in the epitaxial structure. Fig. 7-8 show a series of cross-sectional views of some embodiments corresponding to act 1610.

At act 1612, a pair of first wells, a pair of first pickup wells, a second well, a pair of third wells, a pair of second pickup wells, a pair of first electrodes, a second electrode, and a pair of pickup well contacts are formed in the epitaxial structure, wherein the second well includes a second doping type opposite the first doping type and contacts a second doped buried region located between the first doped buried region and the second electrode. Fig. 9-12 show a series of cross-sectional views of some embodiments corresponding to act 1612.

At act 1614, an interconnect structure is formed over the epitaxial structure. Figures 13-14 illustrate a series of cross-sectional views of some embodiments corresponding to act 1614.

At act 1616, microlenses are formed over the interconnect structure. Figure 15 illustrates a cross-sectional view of some embodiments corresponding to act 1616.

In some embodiments, the present application provides a photodetector. The photodetector includes a first well having a first doping type disposed in the semiconductor substrate, wherein the first well extends into the semiconductor substrate from a first side of the semiconductor substrate. A second well having a second doping type opposite to the first doping type is provided in the semiconductor substrate on a side of the first well, wherein the second well extends from the first side of the semiconductor substrate into the semiconductor substrate. A first doped buried region having a second doping type is disposed in the semiconductor substrate, wherein the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well. A second doped buried region having a second doping type is provided in the semiconductor substrate, the second doped buried region being located between the first doped buried region and the first well in a vertical direction. The second doped buried region contacts the first well such that a photodetector p-n junction exists along the second doped buried region and the first well.

In the above photodetector, the second doped buried region has a concentration of the second doping type different from that of the first doped buried region.

In the above photodetector, the second doped buried region has a concentration of the second doping type lower than that of the first doped buried region.

In the above photodetector, the method further includes: a pickup well comprising a first doping type disposed in the semiconductor substrate and laterally separated from the first well by a second well, wherein the pickup well contacts the second well and the second doped buried region.

In the above photodetector, a side of the pickup well facing the first well continuously contacts the second well, the second doped buried region, and the first doped buried region.

In the above photodetector, the method further includes: an isolation structure disposed over the second doped buried region between the first well and the second well.

In the above photodetector, wherein the isolation structure is spaced apart from the second doped buried region in the vertical direction.

In the above photodetector, wherein a side of the second well facing the first well extends vertically from the second doped buried region to a bottom surface of the isolation structure.

In the above photodetector, the method further includes: a first electrode including a first doping type disposed in the first well; a second electrode comprising a second doping type disposed in the second well, wherein the second electrode is laterally spaced apart from the first electrode; and a third well including a second doping type disposed in the second well and separating the second electrode from the second well, wherein the second well separates the third well from the second doped buried region.

In other embodiments, the present application provides a method of forming a photodetector. The method includes forming a first doped buried region having a first doping type in a semiconductor substrate. A second doped buried region having the first doping type is formed in and over the first doped buried region, wherein the second doped buried region is formed to include a concentration of the first doping type different from the first doped buried region. A pair of first wells having a first doping type are formed in a semiconductor substrate, wherein the first wells are laterally spaced apart from each other. Forming a second well having a second doping type opposite the first doping type in the semiconductor substrate over the second doped buried region, wherein the second well is formed between the first wells, and wherein a bottom of the second well contacts a top of the second doped buried region such that a photodetector p-n junction exists along the bottom of the second well and the top of the second doped buried region. A pair of first electrodes having a first doping type is formed in a semiconductor substrate, wherein the first electrodes are respectively formed in the first wells. A second electrode having a second doping type is formed in the second well.

In the above method of forming a photodetector, wherein the semiconductor substrate comprises an epitaxial structure disposed on a first layer of semiconductor material; a first doped buried region formed in the layer of semiconductor material; a second doped buried region formed in both the first semiconductor material layer and the epitaxial structure; and the first well, the second well, the first electrode and the second electrode are formed in the epitaxial structure.

In the above method of forming a photodetector, wherein forming the second doped buried region comprises: forming an initial doped layer comprising a first doping type in the first layer of semiconductor material, wherein the initial doped layer is formed over the first doped buried region; after forming the initial doped layer, forming an epitaxial structure on the first semiconductor material layer and the initial doped layer; and after forming an epitaxial structure on the first layer of semiconductor material and the initially doped layer, diffusing ions of the initially doped layer into the epitaxial structure to form a second doped buried region.

In the above method of forming a photodetector, further comprising: forming a plurality of trenches in the epitaxial structure; forming isolation structure liners lining the trenches, respectively; after forming the isolation structure liner, performing an annealing process on the semiconductor substrate to improve defects at an interface between the isolation structure liner and the epitaxial structure, wherein the annealing process further diffuses ions of the initially doped layer into the epitaxial structure to form a second doped buried region; and forming an isolation structure dielectric filling the trench on the isolation structure liner to form a plurality of isolation structures in the epitaxial structure.

In the above method of forming a photodetector, further comprising: a pickup well including the second doping type is formed in the epitaxial structure, the pickup well being laterally separated from the second well by one of the first wells, wherein the pickup well contacts one of the second doped buried region and the first well.

In the above method of forming a photodetector, further comprising: a third well including the first doping type is formed in one of the first wells, wherein the third well is separated from the second doped buried region by the one of the first wells.

In yet other embodiments, the present application provides a photodetector. The photodetector includes a pair of first wells having a first doping type disposed in the epitaxial structure. The first wells are laterally spaced apart from each other. An epitaxial structure is disposed on the first layer of semiconductor material. A second well having a second doping type opposite to the first doping type is disposed in the epitaxial structure between the first wells. A pair of cathodes is disposed in the epitaxial structure, wherein the cathodes are disposed in the first wells, respectively. An anode is disposed in the second well. A first doped buried region having a first doping type is disposed in the first layer of semiconductor material, wherein the first doped buried region extends laterally through the first layer of semiconductor material under the pair of cathode and anode. A second doped buried region of the first doping type is disposed in the epitaxial structure and the first layer of semiconductor material between the first doped buried region and the second well, wherein the second doped buried region has a lower concentration of the first doping type than the first doped buried region. The second doped buried region contacts the second well such that a photodetector p-n junction exists along the second doped buried region and the second well.

In the above photodetector, a pair of the first wells are respectively spaced apart from opposite sides of the second well and respectively contact the second doped buried region.

In the above photodetector, the second doped buried region contacts a bottom of the first well.

In the above photodetector, the method further includes: a pickup well including a second doping type disposed in the epitaxial structure and separated from the second well by one of the pair of first wells, and wherein a bottom of the pickup well is disposed below a bottom of one of the pair of first wells.

In the above photodetector, a side of the pickup well facing the second well contacts the second doped buried region located below a bottom of one of the pair of first wells and contacts a side of one of the first wells located above the bottom of one of the pair of first wells.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A photodetector, comprising:

a first well comprising a first doping type disposed in a semiconductor substrate, wherein the first well extends into the semiconductor substrate from a first side of the semiconductor substrate;

a second well including a second doping type disposed in the semiconductor substrate on a side of the first well, the second doping type being opposite the first doping type, wherein the second well extends into the semiconductor substrate from the first side of the semiconductor substrate;

a first doped buried region comprising the second doping type disposed in the semiconductor substrate, wherein the first doped buried region extends laterally through the semiconductor substrate beneath the first well and the second well; and

a second doped buried region including the second doping type disposed in the semiconductor substrate and vertically between the first doped buried region and the first well, wherein the second doped buried region contacts the first well such that a photodetector p-n junction is present along the second doped buried region and the first well.