CN111446269B - CMOS image sensor structure and manufacturing method - Google Patents
CMOS image sensor structure and manufacturing method Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14689—MOS based technologies
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses a CMOS image sensor structure, comprising from bottom to top: the semiconductor device comprises a P + type substrate, a first P type lightly doped layer, a second P type lightly doped layer and a P well; the first P-type lightly doped layer between the second P-type lightly doped layers is provided with a first N-type middle doped layer, the first N-type middle doped layer is sequentially provided with an N-type lightly doped layer and a third N-type middle doped layer, the second N-type middle doped layer is arranged inside the P well, the third N-type middle doped layer and one P well on one side of the third N-type middle doped layer are provided with P-type heavily doped layers, the other P well on the other side of the third N-type middle doped layer is provided with a charge transfer transistor grid, the charge transfer transistor grid is partially overlapped with the third N-type middle doped layer, and the third N-type middle doped layer, the N-type lightly doped layer and the first N-type middle doped layer form an N region of a photodiode PN junction. The invention can reduce leakage current and inhibit crosstalk between pixels. The invention also discloses a manufacturing method of the CMOS image sensor structure.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a CMOS image sensor structure and a manufacturing method thereof.
Background
The photodiode PN junction depth of a typical CMOS image sensor is difficult to exceed 3 microns, which is about 12% quantum efficiency for incident light having a wavelength of 850 nm. Even if aluminum having the highest reflectance is used as the back surface reflection layer, the quantum efficiency does not exceed 21%.
Referring to fig. 1, two adjacent CMOS image sensor pixel cell structures built on a P + substrate 20 are shown. In the figure, a P-type lightly doped layer (a first P-type lightly doped layer) 21 is arranged on a P + type substrate 20, a P-well (a P-type isolation region) 25 is arranged on the P-type lightly doped layer 21, a photodiode PN junction of a pixel unit is arranged between the P-wells 25, the photodiode PN junction comprises an N-type middle doped layer (a third N-type middle doped layer) 15 and an N-type lightly doped layer 26 which form an N region of the PN junction, two adjacent CMOS image sensor pixel units are symmetrical in structure and are isolated from each other by the P-well 25, and the N-type middle doped layers 15 of the two pixel units are provided with a P-type heavily doped layer 28; a pixel unit peripheral circuit is arranged on the other P well positioned on two sides and comprises a charge transfer transistor grid 5, a reset transistor grid 9 and a source drain 7; the device is covered with a dielectric layer 6. In order to improve the quantum efficiency of the near infrared band, the depth of the PN junction of the photodiode can be increased. Wherein the N-type medium doped layer 15 is depleted after reset, providing an electron potential well for storing electrons; the N-type lightly doped layer 26 is partially depleted even if it is not reset, and it is the main photoelectric generation region when the long wave is incident, and at the same time, it generates an electric field pointing to the back surface, and separates the photo-generated electron-hole pairs, so that the photo-generated electrons drift toward the potential well, and the photo-generated holes drift toward the back surface, therefore the N-type lightly doped layer 26 needs to be of high resistance N-type. When the wavelength of incident light is 850 nm, if the quantum efficiency is required to reach 50%, the thickness of the N-type lightly doped layer 26 is about 16 microns, and the injection depth of the P-well 25 in the region of the N-type medium doped layer 15 is required to reach more than 15 microns, which exceeds the energy limit of the implanter when the P-well 25 is injected. According to the prior art, the N-type lightly doped layer 26 needs to be extended, the N-type medium doped layer 15 is implanted, and the steps are repeated at least twice after annealing and cleaning. Therefore, the process is complicated, and defects are easily generated, increasing dark current. If the applied voltage is 3.3V, the highest potential of the PN junction is 3V after reset, the average drift electric field of the N-type lightly doped layer 26 pointing to the electron potential well cannot exceed 2000V/cm, and the electric field is not large enough to effectively inhibit crosstalk between pixels. Since the P-well 25 is implanted with a lateral profile, about 0.6 times the ion range, the above structure can only be used in the case of larger pixels.
The references "Konstantin d. Stefanov, andrew s. Clarke, and Andrew d. Holland filled Depleted Pinned photo diode CMOS Image Sensor With reversed Substrate Bias IEEE ELECTRON DEVICE leds, vol.38, no.1, JANUARY 2017" (costatin d. Stetvonov, anderu s. Clark and anderward d. Hollander using Reverse Substrate Bias) disclose a CMOS Image Sensor DEVICE structure as shown in fig. 2. To improve the quantum efficiency of the near infrared band, a P-type High resistance epitaxial silicon (P-) layer under the PN junction N region of a photodiode (PPD (N)))The replacement PPD (n) acts as the host for the depletion region. In this case, a negative voltage V is applied to the p-type layer BSB . The electrical path between the P-type high resistance epitaxial silicon layer and the P-well (P-well) is pinched off by PPD (N) and DDE (N), the P-well and a voltage V BSB With only a small amount of leakage current in between. With the structure, when the resistivity of the P-type high-resistance epitaxial silicon layer is 1000 ohm cm, the thickness can be 16 microns, the average drift electric field is slightly lower than 5000V/cm, and the quantum efficiency of incident light of 850 nanometers can reach 47%. If a good back reflection layer is used, the quantum efficiency can reach 67%. However, the drift electric field of the P-type high-resistance epitaxial silicon layer with about half thickness is lower than 5000V/cm, and the P-type high-resistance epitaxial silicon layer at the part is easy to cause crosstalk between pixels. Meanwhile, the P-type high-resistance epitaxial silicon layer in fig. 2 is grown on a P + + type substrate (P + + substrate), the P + + type substrate is externally connected with an applied negative voltage through a P well, and the diffusion of photogenerated carriers cannot be limited by using technologies such as back deep trench isolation. If metal contact is made on the back surface of the structure in fig. 2, the depth of deep trench isolation also needs 8 microns, so that crosstalk between pixels can be effectively inhibited. Reference "James R. Janesick Scientific Charge-Coupled Devices SPIE Press 2000" (James R. Janesick Scientific Charge-Coupled device SPIE Press 2000) indicates that cross-talk between pixels can be effectively suppressed when the vertical drift electric field is greater than 5000V/cm.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and to provide a CMOS image sensor structure and a method for manufacturing the same.
In order to realize the purpose, the technical scheme of the invention is as follows:
a CMOS image sensor structure, comprising:
a P + type substrate;
the first P type lightly doped layer is arranged on the P + type substrate;
the second P-type lightly doped layer is arranged on the first P-type lightly doped layer;
the P well is arranged on the second P-type lightly doped layer, and the second N-type medium doped layer is arranged in the P well;
the first N-type middle doped layer is arranged on the first P-type middle doped layer between the second P-type middle doped layers, and the N-type middle doped layer and the third N-type middle doped layer are sequentially arranged on the first N-type middle doped layer;
the P-type heavily doped layer is arranged on the third N-type middle doped layer and one P well on one side of the third N-type middle doped layer;
a charge transfer transistor grid arranged on the other P well on the other side of the third N-type middle doping layer;
the grid electrode of the charge transfer transistor is partially overlapped with the third N-type middle doped layer, and the third N-type middle doped layer, the N-type light doped layer and the first N-type middle doped layer form an N region of a PN junction of the photodiode.
Further, the first P-type lightly doped layer is an epitaxial layer with the resistivity larger than 1000 ohm-cm and the thickness larger than 15 micrometers.
Further, the doping concentration of the first N-type middle doping layer is higher than 3 x 10 14 /cm 3 And is lower than 2X 10 15 /cm 3 。
Further, the implantation dosage of the first N-type medium doped layer is more than 3 x 10 10 /cm 2 And less than 5X 10 11 /cm 2 。
Further, the first N-type middle doped layer is an epitaxial layer with the thickness larger than 0.4 micrometer and smaller than 1 micrometer.
Further, the N-type lightly doped layer is an epitaxial layer with the resistivity larger than 100 ohm-cm, the thickness larger than 2 micrometers and smaller than 5 micrometers.
Furthermore, the second N-type middle doped layer is formed by single or multiple implantation and diffusion, and the doping concentration of the second N-type middle doped layer is greater than 3 x 10 16 /cm 3 And less than 5X 10 17 /cm 3 。
Further, the doping concentration of the P well between the second N-type middle doping layer and the N-type lightly doped layer is less than 3 x 10 16 /cm 3 。
Furthermore, the second P-type lightly doped layer is formed by single or multiple implantation and diffusion, and the total implantation dose is more than 510 11 /cm 2 And less than 2X 10 12 /cm 2 。
A CMOS image sensor structure fabrication method, comprising:
providing a P + type substrate, and epitaxially forming a first P type lightly doped layer on the P + type substrate;
epitaxially forming a first N-type middle doping layer on the first P-type light doping layer;
epitaxially forming an N-type lightly doped layer on the first N-type middle doped layer;
injecting and forming two second P-type lightly doped layers in the first N-type middle doped layer, so that the upper and lower boundaries of the second P-type lightly doped layers are respectively connected with the N-type lightly doped layer and the first P-type lightly doped layer;
injecting and forming two P wells in the N-type lightly doped layer above the second P-type lightly doped layer;
injecting into the P well to form a second N-type middle doped layer;
forming a charge transfer transistor gate on one of the P-well surfaces;
implanting the N-type lightly doped layer between the two P wells to form a third N-type medium doped layer;
performing first injection of a P-type heavily doped layer on the third N-type medium doped layer and on the other P well;
forming side walls on two sides of the grid electrode of the charge transfer transistor;
performing second injection on the P-type heavily doped layer to form a P-type heavily doped layer;
and carrying out source-drain injection to form a source-drain.
According to the technical scheme, the second N-type middle doping layer is formed in the P well, so that after a positive voltage is applied, the second N-type middle doping layer and the first N-type middle doping layer clamp off a current channel between a front P-type region (a P-type heavily doped layer, a P well) and a back P + type region (a P + type substrate) of the device after resetting, and the application of the negative voltage on the back of the device is possible. In addition, the first P-type lightly doped layer can be used as a main photoelectric action region, and the thickness of the first P-type lightly doped layer can be determined by the negative voltage applied to the back surface of the device and the resistivity of the first P-type lightly doped layer. If the resistivity of the first P-type lightly doped layer is 1000 ohm-cm and the negative voltage is-8V, the thickness of the first P-type lightly doped layer can reach more than 20 micrometers, the quantum efficiency of incident light with the wavelength of 850 nanometers can reach more than 63% on the premise that a reflecting layer is not used, and further reach 80% when a good reflecting layer is used. If the negative voltage is-15V, under the premise of keeping the quantum efficiency equal, the crosstalk between the pixels can be reduced to below 2.1% from more than 5%. Meanwhile, in order to effectively prevent crosstalk between pixels, a second P-type lightly doped layer is added between first N-type middle doped layers below second N-type middle doped layers, so that a horizontal electric field pointing to a P well isolation region below the first N-type middle doped layers is obviously enhanced after the second P-type lightly doped layers are added, and the crosstalk between pixels is more favorably inhibited.
Drawings
Fig. 1 is a schematic diagram of a conventional CMOS image sensor.
Fig. 2 is a schematic structural diagram of a conventional charge coupled device.
Fig. 3 is a schematic structural diagram of a CMOS image sensor according to a preferred embodiment of the invention.
Detailed Description
The following provides a more detailed description of embodiments of the present invention, with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following detailed description of the present invention, please refer to fig. 3, wherein fig. 3 is a schematic diagram of a CMOS image sensor according to a preferred embodiment of the present invention. As shown in fig. 3, a CMOS image sensor structure of the present invention includes:
a P + type substrate 20;
a first P-type lightly doped layer 21 disposed on the P + -type substrate 20;
a second P-type lightly doped layer 31 disposed on the first P-type lightly doped layer 21;
a P well 25 disposed on the second P-type lightly doped layer 31, and a second N-type medium doped layer 27 disposed inside the P well 25;
the first N-type middle doping layer 24 is arranged on the first P-type middle doping layer 21 between the second P-type middle doping layers 31, and the N-type middle doping layer 26 and the third N-type middle doping layer 15 are sequentially arranged on the first N-type middle doping layer 24;
a P-type heavily doped layer 28 disposed on the third N-type medium doped layer 15 and one of the P wells 25 on one side thereof;
and a charge transfer transistor gate 5 arranged on the other P well 25 on the other side of the third N-type middle doped layer 15.
Wherein, the charge transfer transistor grid 5 is partially overlapped with the third N-type middle doping layer 15. The third N-type middle doped layer 15, the N-type light doped layer 26 and the first N-type middle doped layer 24 form an N region of a PN junction of the photodiode; the first P-type lightly doped layer 21 serves as the main photoelectric active region.
Fig. 3 shows an example of building two adjacent CMOS image sensor pixel cell structures, which are symmetrical and separated by an isolation layer formed by the P-well 25 and the second P-type lightly doped layer 31.
In the present invention, a positive voltage is applied to the second N-type undoped layer 27; the N-type lightly doped layer 26 and the first N-type middle doped layer 24 are disposed to maintain the reset N-type lightly doped layer 26 at a higher potential, and together with the applied positive voltage on the second N-type middle doped layer 27, the current between the P + -type region (P + -type substrate 20) on the back side and the P-type region (P-type heavily doped layer 28, P well 25) on the front side of the CMOS image sensor device structure of the present invention is blocked, so that the voltage of minus 15V can be applied to the P + -type substrate 20 on the back side.
In order to achieve the purpose of deeply depleting the first P-type lightly doped layer 21, an epitaxial high-resistance P-type lightly doped layer with a resistivity greater than 1000 ohm-cm and a thickness greater than 15 μm is required for the first P-type lightly doped layer 21.
The arrangement of the first N-type middle doped layer 24 improves the N-type lightly doped layer 26 and the second N-type lightly doped layer after resetThe potential of the two N-type middle doped layers 27 on the same horizontal line makes it possible to block the current between the P + type substrate 20 on the back side of the device and the P well 25 on the front side. The first N-type medium doped layer 24 should be more heavily doped than the N-type lightly doped layer 26 but must be depleted after reset. Therefore, the doping concentration of the first N-type middle doping layer 24 is required to be lower than 2 × 10 15 /cm 3 And the thickness is less than 1 micron. When the first N-type medium doping layer 24 is formed by implantation, the implantation dose is less than 5 × 10 11 /cm 2 。
To prevent the back negative voltage from penetrating into the bottom of the third N-type middle doped layer 15 and causing punch-through, the doping concentration of the first N-type middle doped layer 24 needs to be higher than 3 × 10 14 /cm 3 If formed by epitaxy, the thickness is greater than 0.4 microns. And the first N-type middle doped layer 24 is formed by implantation, the implantation dosage is larger than 3 × 10 10 /cm 2 。
To prevent the first N-type undoped layer 24 from being completely depleted and the N-type lightly doped layer 26 and the second N-type lightly doped layer 27 from being at a higher potential on the same horizontal line after the reset, the resistivity of the N-type lightly doped layer 26 needs to be greater than 100 ohm-cm.
In order to prevent punch-through between the second N-type undoped layer 27 and the source/drain (N-type heavily doped region) of the charge transfer transistor, when the N-type lightly doped layer 26 is formed by epitaxy, its thickness needs to be greater than 2 μm; meanwhile, in order to prevent the first N-type undoped layer 24 from being completely depleted, the thickness of the N-type lightly doped layer 26 should also satisfy the requirement of less than 5 μm.
The second N-type undoped layer 27 may be formed by single or multiple implantation and diffusion. In order to effectively block the current between the back P-type and the front P-well 25, the higher the doping concentration of the P-well 25 (P-type isolation region) between the second N-type middle doping layer 27 and the N-type light doping layer 26 is, the smaller the distance between the second N-type middle doping layer 27 and the N-type light doping layer 26 is. Since the second N-type middle doped layer 27 and the N-type lightly doped layer 26 cannot be self-aligned, the doping concentration of the P-well 25 between the second N-type middle doped layer 27 and the N-type lightly doped layer 26 should be less than 3 × 10 to avoid the alignment problem 16 /cm 3 (ii) a And the lateral profile of the implantation of the region P-well 25 and the second N-type medium doped layer 27 is determined, so that the second N-typeThe doping concentration of the middle doping layer 27 needs to be less than 5 × 10 17 /cm 3 . Meanwhile, the second N-type middle doped layer 27 cannot be depleted at a high voltage, and in order to control the size of the second N-type middle doped layer 27, the doping concentration of the second N-type middle doped layer 27 needs to be greater than 3 × 10 16 /cm 3 。
As an example, the device front side voltage is 0V, the back side voltage is-15V, and the net doping of the first P-type lightly doped layer 21 is about 1X 10 13 /cm 3 But with an electron concentration of about 1X 10 3 /cm 3 Hole concentration of about 1X 10 4 /cm 3 Therefore, the first N-type undoped layer 24 and the second N-type undoped layer 27 effectively block the current between the P-type layer on the back side and the P-well 25 on the front side.
When minus 15V is added on the back surface, even if the thickness of the first P-type lightly doped layer 21 reaches 20 microns, the vertical electric field of the whole first P-type lightly doped layer 21 from the electron potential well to the back surface P-type layer is more than 6000V/cm, so that the crosstalk between pixels can be effectively inhibited.
In order to effectively prevent crosstalk between pixel units (pixels), a second P-type lightly doped layer 31 is added between the first N-type middle doped layers 24 and below the second N-type middle doped layer 27 in the P well 25, so that a horizontal electric field pointing to an isolation region of the P well 25 below the first N-type middle doped layer 24 is obviously enhanced after the second P-type lightly doped layer 31 is added, and crosstalk between pixels is favorably inhibited.
The second P-type lightly doped layer 31 as the crosstalk inhibition enhancement region adopts P-type lightly doped, and the total injection dose of the second P-type lightly doped layer 31 must be more than 5 multiplied by 10 for compensating the external pressure of the first N-type middle doped layer 24 to press the N type through single or multiple times of P-type impurity high-energy injection 11 /cm 2 (ii) a In order to avoid breakdown between N type of the second N type middle doped layer 27 and P type of the second P type lightly doped layer 31, the total implantation dose of the second P type lightly doped layer 31 can not exceed 2 × 10 12 /cm 2 。
A method for fabricating a CMOS image sensor structure according to the present invention is described in detail with reference to fig. 3.
A CMOS image sensor structure manufacturing method of the present invention can be used for manufacturing a CMOS image sensor structure shown in fig. 3, which is described by taking the formation of one pixel unit on the right side of the figure as an example, and the manufacturing method can include the following steps:
a P + type substrate 20 is provided. First, a first P-type lightly doped layer 21 is formed on a P + type substrate 20 by epitaxy, and the resistivity of the first P-type lightly doped layer 21 is greater than 1000 ohm-cm and the thickness is greater than 15 μm.
Then, the first N-type middle doping layer 24 may be formed on the first P-type lightly doped layer 21 by continuing the epitaxial process, and the doping concentration of the first N-type middle doping layer 24 may be lower than 2 × 10 15 /cm 3 And the thickness is less than 1 micron.
Then, an N-type lightly doped layer 26 is formed on the first N-type medium doped layer 24 by epitaxy, and the resistivity of the formed N-type lightly doped layer 26 is greater than 100 ohm-cm and the thickness is less than 5 μm.
Shallow trench isolation (not shown) is formed.
Next, a plurality of second P-type lightly doped layers 31 are implanted into the first N-type medium doped layer 24, and the upper and lower boundaries of the second P-type lightly doped layers 31 are in contact with the N-type lightly doped layer 26 and the first P-type lightly doped layer 21, respectively.
Next, a P well 25 is formed by implantation in N-type lightly doped layer 26 over second P-type lightly doped layer 31.
Next, a second N-type undoped layer 27 is implanted inside the P well 25.
Next, a gate oxide layer is grown on the surface of the formed device structure, and polysilicon is deposited on the gate oxide layer, and by etching, the charge transfer transistor gate 5 and the reset transistor gate 9 in the peripheral circuit structure are formed on the surfaces of the P-wells 25 on both sides as shown.
Next, source-drain LDD implantation of the peripheral circuit is performed on the P-well 25 under both sides of the charge transfer transistor gate 5 and the reset transistor gate 0.
Next, a third N-type undoped layer 15 is implanted into the N-type lightly doped layer 26 between the two P wells 25, so that the third N-type undoped layer 15 is formed on the N-type lightly doped layer 26.
A first implant of a heavily P-doped layer 28 is then carried out on the third N-type undoped layer 15 and on one of the P-wells 25 (one P-well 25 is shown between the two picture elements).
Next, spacers are formed on both sides of the charge transfer transistor gate 5 and the reset transistor gate 9.
Next, a second implantation of the P-type heavily doped layer 28 is performed to form the P-type heavily doped layer 28 (the P-type heavily doped layer 28 is formed at an upper position of the third N-type medium doped layer 15 and the P well 25). Wherein the P-type heavily doped layers 28 of the two adjacent pixels on the left and right can be connected.
Subsequently, source-drain implantation is performed to form source-drains 7 of the charge transfer transistor and the reset transistor.
Annealing is performed.
Thereafter, a dielectric layer 6 or the like may be formed on the surface of the formed device structure.
The above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above embodiment, so that any equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A CMOS image sensor structure, comprising:
a P + type substrate;
the first P-type lightly doped layer is arranged on the P + type substrate;
the second P-type lightly doped layer is arranged on the first P-type lightly doped layer;
the P well is arranged on the second P-type lightly doped layer, and the second N-type medium doped layer is arranged in the P well;
the first N-type middle doped layer is arranged on the first P-type middle doped layer between the second P-type middle doped layers, and the N-type middle doped layer and the third N-type middle doped layer are sequentially arranged on the first N-type middle doped layer;
the P-type heavily doped layer is arranged on the third N-type middle doped layer and one of the P wells on one side of the third N-type middle doped layer;
a charge transfer transistor gate disposed on the other P well on the other side of the third N-type middle doped layer;
the grid electrode of the charge transfer transistor is partially overlapped with the third N-type middle doped layer, and the third N-type middle doped layer, the N-type light doped layer and the first N-type middle doped layer form an N region of a PN junction of the photodiode.
2. The CMOS image sensor structure of claim 1, wherein the first P-type lightly doped layer is an epitaxial layer having a resistivity greater than 1000 ohm-cm and a thickness greater than 15 microns.
3. The CMOS image sensor structure of claim 1, wherein the doping concentration of the first N-type medium doping layer is higher than 3 x 10 14 /cm 3 And is lower than 2X 10 15 /cm 3 。
4. The CMOS image sensor structure of claim 1, wherein the first N-type mid-doped layer has an implant dose greater than 3 x 10 10 /cm 2 And is less than 5X 10 11 /cm 2 。
5. The CMOS image sensor structure of claim 1, wherein the first N-type medium doped layer is an epitaxial layer having a thickness greater than 0.4 microns and less than 1 micron.
6. The CMOS image sensor structure of claim 1, wherein the N-type lightly doped layer is an epitaxial layer having a resistivity greater than 100 ohm-cm, a thickness greater than 2 microns, and less than 5 microns.
7. The CMOS image sensor structure of claim 1, wherein said second N-type middle doped layer is formed by single or multiple implantation and diffusion with a doping concentration greater than 3 x 10 16 /cm 3 And is less than 5X 10 17 /cm 3 。
8. The CMOS image sensor structure of claim 1, wherein the doping concentration of the P-well between the second N-type middle doped layer and the N-type lightly doped layer is less than 3 x 10 16 /cm 3 。
9. The CMOS image sensor structure of claim 1, wherein the second P-type lightly doped layer is formed by single or multiple implantation and diffusion, and the total dose of implantation is greater than 5 x 10 11 /cm 2 And is less than 2X 10 12 /cm 2 。
10. A CMOS image sensor structure manufacturing method is characterized by comprising the following steps:
providing a P + type substrate, and epitaxially forming a first P type lightly doped layer on the P + type substrate;
epitaxially forming a first N-type middle doped layer on the first P-type light doped layer;
epitaxially forming an N-type lightly doped layer on the first N-type middle doped layer;
injecting and forming two second P-type lightly doped layers in the first N-type middle doped layer, so that the upper and lower boundaries of the second P-type lightly doped layers are respectively connected with the N-type lightly doped layer and the first P-type lightly doped layer;
injecting and forming two P wells in the N-type lightly doped layer above the second P-type lightly doped layer;
injecting into the P well to form a second N-type middle doped layer;
forming a charge transfer transistor gate on one of the P-well surfaces;
implanting the N-type lightly doped layer between the two P wells to form a third N-type medium doped layer;
performing first injection of a P-type heavily doped layer on the third N-type medium doped layer and on the other P well;
forming side walls on two sides of the grid electrode of the charge transfer transistor;
performing second injection on the P-type heavily doped layer to form a P-type heavily doped layer;
and carrying out source-drain injection to form a source drain.
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| EP2216817A1 (en) * | 2009-02-05 | 2010-08-11 | STMicroelectronics (Crolles 2) SAS | Back side illuminated image sensor |
| CN103346161A (en) * | 2013-06-24 | 2013-10-09 | 上海华力微电子有限公司 | Method for improving picture signal quality of overlapping backside illuminated CMOS imaging sensor |
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