CN110690130A - Three-dimensional heterogeneous stacking method - Google Patents
Three-dimensional heterogeneous stacking method Download PDFInfo
- Publication number
- CN110690130A CN110690130A CN201910904875.7A CN201910904875A CN110690130A CN 110690130 A CN110690130 A CN 110690130A CN 201910904875 A CN201910904875 A CN 201910904875A CN 110690130 A CN110690130 A CN 110690130A
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- layer
- cushion layer
- tin
- metal
- chip module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81051—Forming additional members
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
Abstract
The invention discloses a three-dimensional heterogeneous stacking method, which specifically comprises the following steps: 101) a cushion layer manufacturing step, 102) a retreating step, 103) a removing step and 104) an anti-overflow step; the invention provides a three-dimensional heterogeneous stacking method which can ensure that the metal of the salient point or the welding ring and the welding pad has a certain distance to provide enough space for the solder.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a three-dimensional heterogeneous stacking method.
Background
The microwave millimeter wave radio frequency integrated circuit technology is the basis of modern national defense weaponry and internet industry, and along with the rapid rise of the economy of internet plus such as intelligent communication, intelligent home, intelligent logistics, intelligent transportation and the like, the microwave millimeter wave radio frequency integrated circuit which bears the functions of data access and transmission also has huge practical requirements and potential markets.
However, for a high-frequency micro-system, the area of the antenna array is smaller and smaller, and the distance between the antennas needs to be kept within a certain range, so that the whole module has excellent communication capability. However, for an analog device chip such as a radio frequency chip, the area of the analog device chip cannot be reduced by the same magnification as that of a digital chip, so that a radio frequency micro system with a very high frequency will not have enough area to simultaneously place a PA/LNA, and the PA/LNA needs to be stacked.
In practical application, the module stacking process is generally a process of performing metal fusion bonding on metal dams on the upper surface and the lower surface of a module, for a wafer-level bonding process and a large-size chip bonding process, extremely harsh bonding conditions are required to avoid tin overflow on the surfaces of the metal dams or the surfaces of interconnection pads in the bonding process of the wafer-level bonding process and the large-size chip bonding process, for some dams with larger areas, the problem that tin overflow does not occur on all chips is basically not achieved, once tin overflow occurs, the amount of tin on the surfaces of the dams is greatly reduced, and therefore the subsequent metal fusion process is very unfavorable.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides a three-dimensional heterogeneous stacking method.
The technical scheme of the invention is as follows:
a three-dimensional heterogeneous stacking method specifically comprises the following steps:
101) a cushion layer manufacturing step: depositing silicon oxide or silicon nitride on the upper surface of the carrier plate, or directly thermally oxidizing to form a cushion layer, wherein the thickness of the cushion layer ranges from 10nm to 100 um; or a cushion layer is manufactured on the upper surface of the carrier plate through physical sputtering, magnetron sputtering, evaporation plating process or metal electroplating;
removing part of the cushion layer through photoetching and etching processes, and forming salient points or welding rings on the rest cushion layer; the etching process comprises dry etching and wet etching;
102) and a second treatment step: manufacturing a seed layer on the cushion layer, coating photoresist on the seed layer, removing part of the seed layer through a developing process to expose a region to be electroplated, and electroplating metal and top layer soldering tin; and the upper surface of the electroplated metal forms a structure consistent with the salient points or the welding rings;
103) removing: removing the photoresist and removing the seed layer by a wet method; coating soldering flux, and cleaning the soldering flux after refluxing to obtain bumps or solder rings with solder layers on the surfaces;
104) an anti-overflow step: arranging the chip on the soldering tin in the step 103) to form a new chip module, and welding the new chip module and the traditional chip module to enable the bumps or the welding rings of the new chip module and the traditional chip module to be tightly combined to form a groove area so as to finish three-dimensional stacking of the anti-overflow tin structure.
Furthermore, the cushion layer is of one-layer or multi-layer structure, and the cushion layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; the seed layer, the electroplated metal and the soldering tin are all of one-layer or multi-layer structures, the thickness ranges from 1nm to 100um, and the materials are one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Compared with the prior art, the invention has the advantages that: according to the invention, the protection patterns with different heights are manufactured around the cofferdam or the welding pad, so that the protection patterns can be preferentially contacted to form a block in the bonding process of a wafer or a chip, and thus, a certain distance is reserved between the salient point or the welding ring and the pad metal to provide enough space for the soldering tin, and further, the three-dimensional stacking of the anti-overflow tin structure is provided by the subsequent metal melting.
Drawings
FIG. 1 is a schematic view of a carrier board provided with bumps or solder rings according to the present invention;
FIG. 2 is a schematic view of the seed layer of FIG. 1 according to the present invention;
FIG. 3 is a schematic illustration of the present invention FIG. 2 set up with electroplated metal;
FIG. 4 is a schematic view of the top solder layer of FIG. 3 according to the present invention;
FIG. 5 is a schematic view of the present invention;
FIG. 6 is a schematic illustration of FIG. 2 of the present invention with another electroplated metal;
FIG. 7 is a schematic view of the top solder layer of FIG. 6 according to the present invention;
FIG. 8 is a schematic view of another embodiment of the present invention;
FIG. 9 is a schematic diagram of a carrier plate with pits according to the present invention;
FIG. 10 is a schematic view of the seed layer of FIG. 9 according to the present invention;
FIG. 11 is a schematic view of the plated metal and top layer solder of the arrangement of FIG. 9 of the present invention;
fig. 12 is a schematic view of a third embodiment of the present invention.
The labels in the figure are: a carrier plate 101, bumps or solder loops 102, a seed layer 103, plated metal 104, top layer solder 105 and dimples 106.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
Example 1:
as shown in fig. 1 to 8, a three-dimensional heterogeneous stacking method specifically includes the following steps:
101) a cushion layer manufacturing step: depositing silicon oxide or silicon nitride on the upper surface of the carrier plate 101, or directly thermally oxidizing to form a cushion layer, wherein the thickness of the cushion layer ranges from 10nm to 100 um; or a cushion layer is made on the upper surface of the carrier plate 101 by physical sputtering, magnetron sputtering, evaporation process or metal plating. The cushion layer can be one layer or multiple layers, and when the cushion layer is made of metal, the cushion layer can be made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like. The cushion layer may be formed by stacking a plurality of metal and inorganic layers.
Removing part of the cushion layer through photoetching and etching processes, and forming salient points or welding rings 102 on the rest cushion layer; the etching process includes dry etching and wet etching.
102) And a second treatment step: the seed layer 103 is formed on the pad layer, and has a thickness ranging from 1nm to 100um, and a structure of the seed layer may be one layer or multiple layers, and a metallic material may be one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, and the like. The seed layer 103 is coated with photoresist, a part of the seed layer 103 is removed through a developing process to expose a region to be electroplated, the electroplated metal 104 and the top solder 105 are positioned in the region to be electroplated, and the upper surface of the electroplated metal 104 forms a structure consistent with the bump or the solder ring. Wherein, the thickness of the electroplated metal 104 ranges from 1nm to 100um, the structure of the electroplated metal can be one layer or a plurality of layers, and the material can be one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel and the like; the thickness of the soldering tin ranges from 1nm to 100um, the structure of the soldering tin can be one layer or a plurality of layers, and the tin metal can also be mixed by one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, nickel, gallium metal alloy and the like. The upper surface of the plated metal 104 forms a structure corresponding to the bump or the solder ring, and generally is a metal column with the bump or the solder ring in the middle formed on the upper surface of the plated metal 104, or a metal column with the bump or the solder ring extending from the edge formed on the upper surface of the plated metal 104.
103) Removing: removing the photoresist and removing the seed layer 103 by a wet method; and coating the soldering flux, and cleaning the soldering flux after reflowing to obtain the salient points or the welding rings 102 with the soldering tin on the surface.
104) An anti-overflow step: arranging a chip on the soldering tin in the step 103) to form a new chip module, and welding the new chip module with the traditional chip module, or arranging the chip on the soldering tin in the step 103) to form a new chip module, and welding the new chip module with the new chip module; the two bumps or welding rings 102 are tightly combined to form a groove area, so that the three-dimensional stacking of the anti-solder-overflow structure is completed. I.e., the areas not on the backing layer, are supported by the high bumps or solder rings 102 to avoid the extrusion of the top solder due to the excessive pressure, thereby completing the three-dimensional stacking of the anti-wicking structure.
Example 2:
as shown in fig. 9 to 12, it is substantially the same as embodiment 1 except that a bump or bead 102 is replaced with a dimple 106. Firstly, manufacturing a pit 106 on the upper surface of the carrier plate 101, wherein the pit 106 can be defined through photoetching and developing processes, and then removing the area through a dry etching process or a wet etching process to form the pit 106; the depth of the pits 106 ranges from 1nm to 100um, and their length and width ranges from 1um to 10000 um. The corresponding concave pits 106 are also arranged on the upper surface of the metal column formed by the electroplated metal 104, and the three-dimensional stack of the anti-overflow tin structure is formed by the same processing as that of the embodiment 1.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (2)
1. A three-dimensional heterogeneous stacking method is characterized in that: the method specifically comprises the following steps:
101) a cushion layer manufacturing step: depositing silicon oxide or silicon nitride on the upper surface of the carrier plate, or directly thermally oxidizing to form a cushion layer, wherein the thickness of the cushion layer ranges from 10nm to 100 um; or a cushion layer is manufactured on the upper surface of the carrier plate through physical sputtering, magnetron sputtering, evaporation plating process or metal electroplating;
removing part of the cushion layer through photoetching and etching processes, and forming salient points or welding rings on the rest cushion layer; the etching process comprises dry etching and wet etching;
102) and a second treatment step: manufacturing a seed layer on the cushion layer, coating photoresist on the seed layer, removing part of the seed layer through a developing process to expose a region to be electroplated, and electroplating metal and top layer soldering tin; and the upper surface of the electroplated metal forms a structure consistent with the salient points or the welding rings;
103) removing: removing the photoresist and removing the seed layer by a wet method; coating soldering flux, and cleaning the soldering flux after refluxing to obtain bumps or solder rings with solder layers on the surfaces;
104) an anti-overflow step: arranging the chip on the soldering tin in the step 103) to form a new chip module, and welding the new chip module and the traditional chip module to enable the bumps or the welding rings of the new chip module and the traditional chip module to be tightly combined to form a groove area so as to finish three-dimensional stacking of the anti-overflow tin structure.
2. The three-dimensional heterogeneous stacking method according to claim 1, wherein: the cushion layer is of one-layer or multi-layer structure, and the material is one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; the seed layer, the metal column and the soldering tin are of one-layer or multi-layer structures, the thickness ranges from 1nm to 100um, and the materials are one or a mixture of more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910904875.7A CN110690130A (en) | 2019-09-24 | 2019-09-24 | Three-dimensional heterogeneous stacking method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910904875.7A CN110690130A (en) | 2019-09-24 | 2019-09-24 | Three-dimensional heterogeneous stacking method |
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| CN110690130A true CN110690130A (en) | 2020-01-14 |
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| JPS6489345A (en) * | 1987-09-29 | 1989-04-03 | Fujitsu Ltd | Metal bump and manufacture thereof |
| CN1601712A (en) * | 2003-09-23 | 2005-03-30 | 三星电子株式会社 | Reinforced solder bump structure and method for forming a reinforced solder bump |
| US20070045869A1 (en) * | 2005-08-30 | 2007-03-01 | Kwun-Yao Ho | Chip package and bump connecting structure thereof |
| US20120306104A1 (en) * | 2011-05-31 | 2012-12-06 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Interconnect Structure With Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties |
| CN103187387A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Bump structure, electronic package contact structure and manufacturing method thereof |
| TW201405680A (en) * | 2012-07-25 | 2014-02-01 | Taiwan Semiconductor Mfg | Bump structure and a method for forming the same |
| CN103579149A (en) * | 2012-08-01 | 2014-02-12 | 颀邦科技股份有限公司 | Semiconductor structure and manufacturing process thereof |
| CN103855116A (en) * | 2012-12-06 | 2014-06-11 | 富士通株式会社 | Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus |
| US20140264890A1 (en) * | 2013-03-15 | 2014-09-18 | Globalfoundries Inc. | Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure |
| US9837346B2 (en) * | 2014-08-27 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging device having plural microstructures disposed proximate to die mounting region |
-
2019
- 2019-09-24 CN CN201910904875.7A patent/CN110690130A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6489345A (en) * | 1987-09-29 | 1989-04-03 | Fujitsu Ltd | Metal bump and manufacture thereof |
| CN1601712A (en) * | 2003-09-23 | 2005-03-30 | 三星电子株式会社 | Reinforced solder bump structure and method for forming a reinforced solder bump |
| US20070045869A1 (en) * | 2005-08-30 | 2007-03-01 | Kwun-Yao Ho | Chip package and bump connecting structure thereof |
| US20120306104A1 (en) * | 2011-05-31 | 2012-12-06 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Interconnect Structure With Conductive Pads Having Expanded Interconnect Surface Area for Enhanced Interconnection Properties |
| CN103187387A (en) * | 2011-12-30 | 2013-07-03 | 财团法人工业技术研究院 | Bump structure, electronic package contact structure and manufacturing method thereof |
| TW201405680A (en) * | 2012-07-25 | 2014-02-01 | Taiwan Semiconductor Mfg | Bump structure and a method for forming the same |
| CN103579149A (en) * | 2012-08-01 | 2014-02-12 | 颀邦科技股份有限公司 | Semiconductor structure and manufacturing process thereof |
| CN103855116A (en) * | 2012-12-06 | 2014-06-11 | 富士通株式会社 | Electronic component, electronic apparatus including the same, and manufacturing method of the electronic apparatus |
| US20140264890A1 (en) * | 2013-03-15 | 2014-09-18 | Globalfoundries Inc. | Novel pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure |
| US9837346B2 (en) * | 2014-08-27 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging device having plural microstructures disposed proximate to die mounting region |
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Application publication date: 20200114 |