CN110690125A - 一种foplp晶圆整体封装方法 - Google Patents
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Abstract
本发明提供一种FOPLP晶圆整体封装方法,包括:在整片的晶圆片背面上贴蓝膜后进行划片切割得到晶圆片板件;对蓝膜进行处理,使蓝膜扩张;将一个或数个晶圆片板件贴在载板上,并撕掉蓝膜;对晶圆片板件进行塑封;对塑封板件进行拆键合操作,并测量裸芯片偏移量;将塑封板件经过贴介电层、溅射金属种子层、贴感光干膜的工序,结合测得的偏移量修正曝光参数;通过曝光显影、电镀沉铜、闪蚀刻的工序完成RDL层的制作;在RDL层上植锡球,切割得到单个的芯片。本发明采用板级封装技术完成晶圆型芯片的封装,单个面板产出的封装芯片是传统晶圆级封装的几倍,解决了芯片封装出现漂移、间距不一致的问题,不仅工艺效率高、成本低,且可靠性好。
Description
技术领域
本发明涉及板级扇出型封装技术领域,尤其涉及一种FOPLP晶圆整体封装方法。
背景技术
随着微电子封装技术的发展,芯片尺寸越来越小,晶体管数量越来越高,传统的BGA封装难以满足小型化的趋势,随之衍生出了扇出型封装技术。扇出型封装技术可分为晶圆级封装(WLCSP)技术和板级封装(FOPLP)技术;晶圆级扇出型封装是先将晶圆片整体封装后再切割成单个芯片,具有小而薄的特点,而板级扇出型封装是采用大面积的载板,将大量挑选过的芯片放在载板上进行整体封装,再切割成单个芯片,具有低成本的特点。
由于晶圆级封装具有小而薄的特点,通常芯片表面没有塑封保护层,其可靠性不及板级扇出型封装的芯片,运用范围非常有限。而相较于晶圆级封装,板级扇出型封装的载板面积较大,可放入大量芯片同时封装,成本较低,也能放入被动元件或多种芯片,以实现更复杂的封装。此外,板级扇出型封装还具有可制作多层RDL、容易实现系统级封装及3D堆叠封装、耐高温、多I/O口等特点。
由此可知,板级扇出型封装技术是未来封装技术的主流,但如何将板级扇出型封装技术应用在晶圆片整体封装,使得晶圆片的封装具有板级扇出型封装的优点成为业界急需解决的一大难题。
发明内容
本发明提供一种封装工艺效率高、成本低、且可靠性好的FOPLP晶圆整体封装方法。
本发明采用的技术方案为:一种FOPLP晶圆整体封装方法,其包括以下步骤:
(1)在整片的晶圆片的背面贴上蓝膜,再将晶圆片朝上(die up)进行划片切割,得到多块裸芯片组成的晶圆片板件;
(2)对上述蓝膜进行处理,使蓝膜扩张,蓝膜上的裸芯片也跟着扩张到指定间距;
(3)将一个或数个晶圆片板件朝下(die down)贴在布置有临时键合胶的载板上,再撕掉蓝膜,形成裸芯片-临时键合胶-载板的结构;
(4)对上述结构进行塑封形成塑封板件,并对其进行研磨减薄;
(5)对塑封板件进行拆键合操作,并将塑封板件倒置,利用die shift AOI设备测量裸芯片的偏移量;
(6)在塑封板件上贴介电层、再依次经过激光打孔、溅射金属种子层、贴感光干膜的工序,结合之前的测量的裸芯片偏移量修正曝光参数;
(7)对塑封板件进行曝光显影得到可布置RDL层的凹槽、再依次经过电镀沉铜,去感光干膜,闪蚀刻完成RDL层的制作;
(8)在塑封板件表面涂油墨,并在RDL层上植锡球,然后切割得到单个封装好的芯片。
进一步地,步骤(1)中,所述蓝膜的面积大于或等于整片的所述晶圆片的面积。
进一步地,步骤(1)中,对整片的所述晶圆片进行划片切割时可为不完全切割,利用蓝膜扩张时的张力作用使所述裸芯片分离。
进一步地,步骤(2)中,对所述蓝膜进行处理的方式为热处理、拉伸处理的一种或两种,并利用机械装置进行辅助,使裸芯片能扩张到指定间距。
进一步地,步骤(2)中,扩张后,相邻的所述裸芯片之间的间距为0.01mm~100mm。
进一步地,步骤(3)中,贴在所述载板上的所述裸芯片种类为一种或数种。
进一步地,步骤(3)中,所述的载板为方形的板级载板,其尺寸大小为100mm*100mm到1000mm*1000mm之间。
相较于现有技术,本发明的FOPLP圆精整体封装方法具有以下优点:
1.采用板级封装技术完成晶圆片的封装,利用板级封装载板承载多块已切割的裸芯片进行整体塑封,实现了同时对单个或多个已切割的裸芯片进行封装,单个面板产出的封装芯片是传统晶圆级封装的几倍,有效提高了晶圆级封装效率,同时使得晶圆片的封装具有板级封装的高可靠性和低成本的优点。
2.采用了板级封装技术对晶圆片进行塑封,可以扩大单次晶圆片的封装数量,从而有效降低成本;适用于裸芯片单个面积小、数量多的晶圆片进行整体封装。
3.减少了筛选、分拣、排列布置晶圆片等操作步骤,有效提高封装效率。
4.利用die shift AOI设备测量并修正相关参数,可解决裸芯片扩张后间距不一致、塑封后芯片偏移的问题。
附图说明
附图是用来提供对本发明的进一步理解,并构成说明书的一部分,与下面的具体实施方式一起用于解释本发明,但不应构成对本发明的限制。在附图中,
图1:本发明FOPLP圆精整体封装方法的步骤流程图;
图2:本发明FOPLP圆精整体封装方法的流程示意图。
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
如图1和图2所示,本发明的FOPLP晶圆整体封装方法,包括以下步骤:
(1)在整片的晶圆片的背面贴上蓝膜,再将晶圆片朝上(die up)进行划片切割,得到多块裸芯片2组成的晶圆片板件。该步骤中,蓝膜1的面积大于或等于整片的晶圆片的面积。对整片的晶圆片进行划片切割时可为不完全切割,利用蓝膜1扩张时的张力作用使裸芯片2分离。
(2)对上述蓝膜1进行处理,使蓝膜1扩张,蓝膜1上的裸芯片2也跟着扩张到指定间距。在该步骤中,将蓝膜1经过热处理或拉伸处理的一种或两种,并利用机械装置进行辅助,使裸芯片2能扩张到指定间距。扩张后,相邻的裸芯片2之间的间距为0.01mm~100mm。
(3)将一个或数个裸芯片2芯片朝下(die down)贴在布置有临时键合胶4的载板3上,再撕掉蓝膜1,形成裸芯片2-临时键合胶4-载板3的结构。在该步骤中,贴在载板3上的裸芯片2种类为一种或数种;载板3为方形的板级载板,其尺寸大小为100mm*100mm到1000mm*1000mm之间。
(4)对上述结构进行塑封(Molding)形成塑封板件5,并对其进行研磨减薄(grinding);
(5)对塑封板件5进行拆键合操作,并将塑封板件5倒置,利用die shift AOI设备测量裸芯片2偏移量。
(6)在塑封板件5上贴介电层6、再依次经过激光打孔、溅射金属种子层7、贴感光干膜8的工序,结合之前测量的裸芯片2的偏移量修正曝光参数。在该步骤中,金属种子层7厚度为0.1nm~10um之间;且金属种子层7可制作一层或数层。
(7)对塑模板件5减小曝光显影得到可布置RDL层10(重布线层)的凹槽9,再依次经过电镀沉铜、去感光干膜8、闪蚀刻的工序,完成RDL层10的制作。
(8)在塑模板件5的表面涂油墨,并在RDL层10上植锡球,然后切割得到单个封装好的芯片。
综上,本发明的FOPLP圆精整体封装方法具有以下优点:
1.采用板级封装技术完成晶圆片的封装,利用板级封装载板3承载多块已切割的晶圆片进行整体塑封,实现了同时对单个或多个已切割的晶圆片进行封装,单个面板产出的封装芯片是传统晶圆级封装的几倍,有效提高了晶圆级封装效率,同时使得晶圆片的封装具有板级封装的高可靠性和低成本的优点。
2.采用了板级封装技术对晶圆片进行塑封,可以扩大单次晶圆片的封装数量,从而有效降低成本;适用于裸芯片单个面积小、数量多的晶圆片进行整体封装。
3.减少了筛选、分拣、排列布置晶圆片等操作步骤,有效提高封装效率。
4.利用die shift AOI设备测量并修正相关参数,可解决裸芯片2扩张后间距不一致、塑封后芯片偏移的问题。
只要不违背本发明创造的思想,对本发明的各种不同实施例进行任意组合,均应当视为本发明公开的内容;在本发明的技术构思范围内,对技术方案进行多种简单的变型及不同实施例进行的不违背本发明创造的思想的任意组合,均应在本发明的保护范围之内。
Claims (7)
1.一种FOPLP晶圆整体封装方法,其特征在于,包括以下步骤:
(1)在整片的晶圆片的背面贴上蓝膜,再将晶圆片朝上进行划片切割,得到多块裸芯片组成的晶圆片板件;
(2)对上述蓝膜进行处理,使蓝膜扩张,蓝膜上的裸芯片也跟着扩张到指定的间距;
(3)将一个或数个晶圆片板件朝下贴在布置有临时键合胶的载板上,再撕掉蓝膜,形成裸芯片-临时键合胶-载板的结构;
(4)对上述结构进行塑封形成塑封板件,并对其进行研磨减薄;
(5)对塑封板件进行拆键合操作,并将塑封板件倒置,利用die shift AOI设备测量裸芯片的偏移量;
(6)在塑封板件上贴介电层、再依次经过激光打孔、溅射金属种子层、贴感光干膜的工序,结合之前的测量的裸芯片偏移量修正曝光参数;
(7)对塑封板件进行曝光显影得到可布置RDL层的凹槽、再依次经过电镀沉铜,去感光干膜,闪蚀刻完成RDL层的制作;
(8)在塑封板件表面涂油墨,并在RDL层上植锡球,然后切割得到单个封装好的芯片。
2.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(1)中,所述蓝膜的面积大于或等于整片的所述晶圆片的面积。
3.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(1)中,对整片的所述晶圆片进行划片切割时可为不完全切割,利用所述蓝膜扩张时的张力作用使所述裸芯片分离。
4.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(2)中,对所述蓝膜进行处理的方式为热处理、拉伸处理的一种或两种,并利用机械装置进行辅助,使所述裸芯片能扩张到指定的间距。
5.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(2)中,扩张后,相邻的所述裸芯片之间的间距为0.01mm~100mm。
6.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(3)中,贴在所述载板上的所述裸芯片种类为一种或数种。
7.如权利要求1所述的FOPLP晶圆整体封装方法,其特征在于:步骤(3)中,所述的载板为方形的板级载板,其尺寸大小为100mm*100mm到1000mm*1000mm之间。
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112908870A (zh) * | 2021-02-01 | 2021-06-04 | 杭州晶通科技有限公司 | 一种能够消除芯片位移差的晶圆级扇出型封装方法 |
CN113764547A (zh) * | 2021-08-30 | 2021-12-07 | 东莞市中麒光电技术有限公司 | 一种Mini-LED器件的制作方法 |
CN115083903A (zh) * | 2022-07-21 | 2022-09-20 | 山东中清智能科技股份有限公司 | 一种晶圆的切割方法以及单芯片封装体 |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740351A (zh) * | 2008-11-26 | 2010-06-16 | 日东电工株式会社 | 切割模片接合膜以及半导体器件的生产方法 |
TW201638258A (zh) * | 2015-02-06 | 2016-11-01 | Lintec Corp | 黏著片及半導體裝置的製造方法 |
CN107644821A (zh) * | 2016-07-20 | 2018-01-30 | 三星电子株式会社 | 测量芯片的未对准的方法、扇出面板级封装及其制造方法 |
-
2019
- 2019-09-10 CN CN201910851357.3A patent/CN110690125A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101740351A (zh) * | 2008-11-26 | 2010-06-16 | 日东电工株式会社 | 切割模片接合膜以及半导体器件的生产方法 |
TW201638258A (zh) * | 2015-02-06 | 2016-11-01 | Lintec Corp | 黏著片及半導體裝置的製造方法 |
CN107644821A (zh) * | 2016-07-20 | 2018-01-30 | 三星电子株式会社 | 测量芯片的未对准的方法、扇出面板级封装及其制造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112908870A (zh) * | 2021-02-01 | 2021-06-04 | 杭州晶通科技有限公司 | 一种能够消除芯片位移差的晶圆级扇出型封装方法 |
CN112908870B (zh) * | 2021-02-01 | 2023-08-18 | 杭州晶通科技有限公司 | 一种能够消除芯片位移差的晶圆级扇出型封装方法 |
CN113764547A (zh) * | 2021-08-30 | 2021-12-07 | 东莞市中麒光电技术有限公司 | 一种Mini-LED器件的制作方法 |
CN115083903A (zh) * | 2022-07-21 | 2022-09-20 | 山东中清智能科技股份有限公司 | 一种晶圆的切割方法以及单芯片封装体 |
CN117276094A (zh) * | 2023-10-12 | 2023-12-22 | 江苏柒捌玖电子科技有限公司 | 一种晶圆级封装方法及芯链封装结构 |
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