CN110688333A - PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method - Google Patents

PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method Download PDF

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Publication number
CN110688333A
CN110688333A CN201910933066.9A CN201910933066A CN110688333A CN 110688333 A CN110688333 A CN 110688333A CN 201910933066 A CN201910933066 A CN 201910933066A CN 110688333 A CN110688333 A CN 110688333A
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data
length
tlp
packet
address
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Inventor
吴世勇
苏庆会
王凯霖
王斌
李银龙
徐诺
刘武忠
廖正赟
彭金辉
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Zhengzhou Xinda Jiean Information Technology Co Ltd
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Zhengzhou Xinda Jiean Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The invention provides a DMA data transmission system and method based on PCIE, the system includes: the system comprises PCIE equipment and a host, wherein the PCIE equipment carries out data interaction with the host through a PCIE bus; the PCIE device: the device comprises a DMA module, a data processing module and a data processing module, wherein the DMA module is used for reading data in the host and/or writing data in the PCIE equipment into the host; according to the invention, only the first address and the length of the data to be transmitted need to be assigned to the DMA module at one time, and the first address and the length of the remaining data to be transmitted are calculated and updated in real time every time the TLP data packet or the TLP request packet is subsequently encapsulated, so that the length of the current TLP data packet or the TLP request packet can be calculated in real time according to the first address and the length of the current data to be transmitted, and each encapsulated TLP data packet or TLP request packet does not cross a 4KB boundary. The invention solves the problem that the TLP packet is discarded when crossing the 4KB boundary by a hardware mode, and has high transmission efficiency.

Description

PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method
Technical Field
The invention relates to the technical field of computers, in particular to a DMA data transmission system and method based on PCIE.
Background
With the development of modern society technology, a PCIE (peripheral component interconnect express) bus is widely used as a high performance I/O bus in computer systems, and almost all commercial and industrial computer manufacturers provide PCIE bus interfaces in the computer systems produced by the PCIE bus. The PCIE bus standard will replace the original PCI and AGP buses, and become a standard bus interface of a new generation of computer systems. The PCIE bus uses high-speed differential signals and adopts an end-to-end bidirectional transmission mode, namely receiving and sending respectively occupy a pair of differential pairs, and the transmission mode greatly improves the transmission rate.
When the PCIE transaction layer performs high-speed data interaction with the host memory (for example, DMA read data or DMA write data), the DMA read/write data is first encapsulated by the PCIE transaction layer into at least one TLP packet, and if a TLP packet crosses a 4KB boundary, the TLP packet will not hit a target address of the host memory and will be discarded. The traditional solution is to determine the target address crossing the 4KB boundary by software and to transfer the target address to the DMA controller to complete the operation, and the above method needs the CPU to configure the DMA controller many times, which increases the burden of the CPU and causes additional overhead of software processing.
Disclosure of Invention
In view of the above problems, it is necessary to provide a PCIE-based DMA data transmission system and method, which solve the problem that a TLP packet is discarded when crossing a 4KB boundary in a hardware manner.
In a first aspect, the present invention provides a PCIE-based DMA data transmission system, where the system includes: the system comprises PCIE equipment and a host, wherein the PCIE equipment carries out data interaction with the host through a PCIE bus;
the PCIE device: the device comprises a DMA module, a data processing module and a data processing module, wherein the DMA module is used for reading data in the host and/or writing data in the PCIE equipment into the host;
when the DMA module reads data in the host, the DMA module receives a first address and a data size of data to be read, which are fed back by the host, and formulates an encapsulation rule of a TLP request packet by combining a predetermined Payload, so that each encapsulated TLP request packet does not cross a 4KB boundary;
when the DMA module writes data into the host, the DMA module receives the first address of the to-be-written area fed back by the host, and formulates an encapsulation rule of the TLP data packet by combining the data size of the to-be-written data and a predetermined Payload, so that each TLP data packet after encapsulation does not cross a 4KB boundary.
Further, the Payload is a maximum length of an allowed encapsulation of a TLP request packet or a TLP data packet, which is negotiated and established by the PCIE device and the host.
Further, the first address of the data to be read is preset as a1The length of data to be read is b1When the first address a1When the boundary length of 4KB is greater than or equal to the Payload, the Payload and the data length b to be read are taken from the encapsulation length of the current TLP request packet1The smallest of the above; when the first address a1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP request packet takes the first address a1Length to 4KB boundary and data length to be read b1The smallest one of them.
Further, after the previous TLP request packet is encapsulated, a new first address a needs to be redefined for subsequent data to be readiAnd a new length b of data to be readiThen the new head address aiRequesting packets for a previous TLPFirst address ai-1Plus the length of the previous TLP request packet, the new data length b to be readiLength b of data to be read corresponding to previous TLP request packeti-1Minus the length of the previous TLP request packet.
Further, the first address of the area to be written is preset as c1Length of data to be written is d1When the first address c1When the boundary length of 4KB is greater than or equal to the Payload, the encapsulation length of the current TLP data packet is the Payload and the data length d to be written1The smallest of the above; when the first address c1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP packet takes the head address c1Length to 4KB boundary and length of data to be written d1The smallest one of them.
Further, after the previous TLP packet is encapsulated, a new head address c needs to be redefined for a subsequent to-be-written areaiRedefining the length d of the subsequent data to be writteniThen new head address ciIs the head address c of the previous TLP packeti-1Plus the length of the previous TLP packet, the new length d of data to be writteniThe length d of data to be written corresponding to the previous TLP data packeti-1The length of the previous TLP packet is subtracted.
Further, the number of the 4KB boundaries is m, each 4KB boundary represents a physical address of the host, and the length of the physical address of the nth 4KB boundary is n × 4096, and n is less than or equal to m.
Furthermore, the PCIE device further includes a data processing module, where the data processing module is configured to receive and process the data read by the DMA module from the host, and after the processing is completed, the DMA module writes the processed data into the host.
The second aspect of the present invention further provides a PCIE-based DMA data transmission method, where the method includes:
the host feeds back the initial address and the data size of the data to be read to the DMA module;
the DMA module formulates an encapsulation rule of the TLP request packet according to the first address and the data size of the data to be read and in combination with a predetermined Payload, so that each TLP request packet after encapsulation does not cross a 4KB boundary;
the DMA module encapsulates the TLP request packet according to the encapsulation rule of the TLP request packet, and sends the TLP request packet after encapsulation to the host;
and the host returns a TLP completion packet carrying data to complete the process of reading the data from the host by the DMA module.
Further, the method further comprises:
the host feeds back the first address of the area to be written to the DMA module;
the DMA module establishes a TLP data packet encapsulation rule according to the head address of the area to be written and the size of the data volume to be written and in combination with a predetermined Payload, so that each TLP data packet after encapsulation does not cross a 4KB boundary;
and the DMA module encapsulates the data to be written into a TLP data packet according to the encapsulation rule of the TLP data packet, and transmits the encapsulated TLP data packet to the host so as to complete the process of writing the data into the host by the DMA module.
The PCIE-based DMA data processing system and method provided by the invention solve the problem that a TLP packet is discarded when crossing a 4KB boundary in a hardware mode, and compared with the traditional software solution mode, the hardware mode provided by the invention does not need a CPU (central processing unit) to configure a DMA controller for many times, thereby reducing the burden of the CPU, improving the data transmission efficiency and further saving the data processing cost.
Drawings
Fig. 1 is a block diagram of a PCIE-based DMA data transfer system according to the present invention.
FIG. 2 is a schematic diagram illustrating the encapsulation rule of a TLP request packet according to the present invention.
Fig. 3 shows a flowchart of a PCIE-based DMA data reading method according to the present invention.
Fig. 4 shows a flowchart of a PCIE-based DMA data writing method according to the present invention.
Detailed Description
In order to make the present invention clearer, the technical solution of the present invention is further described in detail by the following embodiments.
Fig. 1 is a block diagram of a PCIE-based DMA data transfer system according to the present invention.
As shown in fig. 1, a first aspect of the present invention provides a PCIE-based DMA data transmission system, a PCIE device and a host, where the PCIE device performs data interaction with the host through a PCIE bus;
the PCIE device: the device comprises a DMA module, a data processing module and a data processing module, wherein the DMA module is used for reading data in the host and/or writing data in the PCIE equipment into the host;
when the DMA module reads data in the host, the DMA module receives a first address and a data size of data to be read, which are fed back by the host, and formulates an encapsulation rule of a TLP request packet by combining a predetermined Payload, so that each encapsulated TLP request packet does not cross a 4KB boundary;
when the DMA module writes data into the host, the DMA module receives the first address of the to-be-written area fed back by the host, and formulates an encapsulation rule of the TLP data packet by combining the data size of the to-be-written data and a predetermined Payload, so that each TLP data packet after encapsulation does not cross a 4KB boundary.
According to an embodiment of the present invention, the Payload may be a maximum length of an allowed encapsulation of a TLP request packet or a TLP data packet, where the maximum length is defined by the PCIE device and the host in a negotiation manner. Preferably, the Payload may be 128 bytes, 256 bytes, but is not limited thereto.
It should be noted that the TLP data packets contain data, that is, in the process of writing data by the DMA module, the data to be written is directly encapsulated into a plurality of TLP data packets and transmitted to the host. When the DMA module reads data, a plurality of TLP request packets are first encapsulated according to a head address, a data size, and a predetermined Payload of the data to be read, each TLP request packet has a predetermined start address and a predetermined load size, and the host can load data according to the start address and the load size of the TLP request packet and transmit a TLP completion packet carrying the data back to the DMA module.
Further, the host includes a memory and a CPU, where the memory is used to store data for the DMA module to read, and/or receive data written by the DMA module; the CPU is used for pre-setting the first address and the data size of the data to be read in the memory into the DMA module, and/or pre-setting the first address of the area to be written in the memory into the DMA module.
When the DMA module reads data in the host, the first address of the data to be read may be preset as a1The length of data to be read is b1When the first address a1When the boundary length of 4KB is greater than or equal to the Payload, the Payload and the data length b to be read are taken from the encapsulation length of the current TLP request packet1The smallest of the above; when the first address a1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP request packet takes the first address a1Length to 4KB boundary and data length to be read b1The smallest one of them.
Further, after the previous TLP request packet is encapsulated, a new first address a needs to be redefined for subsequent data to be readiAnd a new length b of data to be readiThen the new head address aiFirst address a of a previous TLP request packeti-1Plus the length of the previous TLP request packet, the new data length b to be readiLength b of data to be read corresponding to previous TLP request packeti-1Minus the length of the previous TLP request packet. It can be understood that the head address of the data to be read and the length of the data to be read can be sequentially updated and changed according to the progress of encapsulating the TLP request packet, the invention only needs to assign the head address and the length of the data to be read to the DMA module once, and the length and the head address of the remaining data to be read are calculated and updated in real time every time the TLP request packet is encapsulated, so that the length of the current TLP request packet can be calculated in real time according to the length and the head address of the current data to be read subsequently.
When the DMA module writes data into the host, the first address of the area to be written may be preset to be c1Length of data to be written is d1When the first address c1When the boundary length of 4KB is greater than or equal to the Payload, the encapsulation length of the current TLP data packet is the Payload and the data length d to be written1The smallest of the above; when the first address c1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP packet takes the head address c1Length to 4KB boundary and length of data to be written d1The smallest one of them.
Further, after the previous TLP packet is encapsulated, a new head address c needs to be redefined for a subsequent to-be-written areaiRedefining the length d of the subsequent data to be writteniThen new head address ciIs the head address c of the previous TLP packeti-1Plus the length of the previous TLP packet, the new length d of data to be writteniThe length d of data to be written corresponding to the previous TLP data packeti-1The length of the previous TLP packet is subtracted. The length of the remaining data length to be written and the first address of the area to be written are calculated and updated in real time every time the TLP data packet is encapsulated, so that the length of the current TLP data packet can be calculated and updated in real time according to the length of the current data length to be written and the first address of the area to be written.
It can be understood that, on the basis that the TLP request packet and the TLP data packet do not cross the 4KB boundary, the data load of each packet is Payload as much as possible, so that the maximum utilization of resources of each TLP request packet and each TLP data packet is realized, and the data transmission efficiency is further improved.
According to an embodiment of the present invention, the number of the 4KB boundaries may be m, each 4KB boundary represents a physical address of the host, and the length of the physical address of the nth 4KB boundary is n × 4096, and n is less than or equal to m.
According to the embodiment of the present invention, the PCIE device further includes a data processing module, where the data processing module is configured to receive and process the data read from the host by the DMA module, and after the processing is completed, the DMA module writes the processed data into the host.
Specifically, the PCIE device may be a PCIE board, and the data processing module may be an encryption and decryption processing module, and is configured to perform encryption and decryption processing on data. Preferably, the encryption and decryption processing module may adopt any one of a DES algorithm, a 3DES algorithm, an AES algorithm, and a cryptographic SM4 algorithm to implement encryption and decryption processing on data. But is not limited thereto.
To further illustrate the technical solution of the present invention, an encapsulation rule of a TLP request packet is specifically described below according to an embodiment.
As shown in fig. 2, the Payload length in this embodiment is predetermined to be 128 (byte, which is omitted for convenience of description, and the first address a of the data to be read13912, the length of data to be read is b1Is 480.
According to the encapsulation rule of the TLP request packet, the first address a of the first TLP request packet13912, the length of data to be read is b1Is 480, the first address a is satisfied at this time1The length (184) to the 4KB boundary is greater than or equal to the Payload (128), and the length of the first TLP request packet is the Payload (128) and the length b of the data to be read1(480) The smallest one of which is 128; first address a of second TLP request packet2Update change is 3912+128=4040, length b of data to be read2The update change is 480-2The length to 4KB boundary (56) is less than the Payload (128), then the length of the second TLP request packet takes the first address a2Length to 4KB boundary (56) and length of data to be read b2(352) 56, is the smallest one of the above; first address a of third TLP request packet3The update changes to 4KB boundary (4096), the length of data to be readb3The update change is 352-56=296, when the first address a is satisfied3(4096) The length (8192-3(296) The smallest one of which is 128; similarly, the length of the fourth TLP request packet can be determined to be 128 according to the calculation manner of the third TLP request packet; head address a of fifth TLP request packet5Update change to 4352, data length b to be read5Update change is 40, when the first address a is satisfied5The length (8192-5(40) The smallest one of which is 40.
It is understood that, in the above embodiment, if no TLP request packet encapsulation rule is formulated, the data to be read (420) is encapsulated into four TLP request packets, the lengths of the first to third TLP request packets are Payload (128), and the length of the fourth TLP request packet is the remaining length of the data to be read after being encapsulated by the first three TLP request packets, that is, 96; wherein the second TLP request packet is discarded as crossing a 4KB boundary; in view of this, the present invention can effectively avoid the phenomenon of packet loss during the reading process by formulating the encapsulation rule of the TLP request packet, and ensure the integrity of the read data.
It should be noted that the principle of the encapsulation rule of the TLP packet is similar to that of the TLP request packet, and for saving space, the encapsulation rule of the TLP packet is not described in detail herein.
Fig. 3 shows a flowchart of a PCIE-based DMA data reading method according to the present invention.
As shown in fig. 3, a second aspect of the present invention further provides a PCIE-based DMA data transmission method, which is applied to the PCIE-based DMA data transmission system, where the method includes:
s301, the host feeds back the initial address and the data size of the data to be read to the DMA module;
s302, the DMA module formulates an encapsulation rule of the TLP request packet according to the first address and the data size of the data to be read and in combination with a predetermined Payload, so that each TLP request packet after encapsulation does not cross a 4KB boundary;
s303, the DMA module encapsulates the TLP request packet according to the encapsulation rule of the TLP request packet, and sends the TLP request packet after encapsulation to the host;
s304, the host returns a TLP completion packet carrying data to complete the process of the DMA module reading data from the host.
Fig. 4 shows a flowchart of a PCIE-based DMA data reading method according to the present invention.
As shown in fig. 4, the method further comprises:
s401, the host feeds back the first address of the area to be written to the DMA module;
s402, the DMA module formulates an encapsulation rule of the TLP data packet according to the head address of the area to be written and the size of the data volume to be written, and in combination with a predetermined Payload, so that each encapsulated TLP data packet does not cross a 4KB boundary;
s403, the DMA module encapsulates the data to be written into a TLP data packet according to the encapsulation rule of the TLP data packet, and transmits the TLP data packet after encapsulation to the host, so as to complete the process of writing the data into the host by the DMA module.
Further, the Payload is a maximum length of an allowed encapsulation of a TLP request packet or a TLP data packet, which is negotiated and established by the PCIE device and the host.
Further, the TLP request packet encapsulation rule is specifically:
presetting the head address of data to be read as a1The length of data to be read is b1When the first address a1When the boundary length of 4KB is greater than or equal to the Payload, the Payload and the data length b to be read are taken from the encapsulation length of the current TLP request packet1The smallest of the above; when the first address a1To 4KB boundary length less than theWhen Payload is requested, the encapsulation length of the current TLP request packet takes the first address a1Length to 4KB boundary and data length to be read b1The smallest one of them.
Further, after the previous TLP request packet is encapsulated, a new first address a needs to be redefined for subsequent data to be readiAnd a new length b of data to be readiThen the new head address aiFirst address a of a previous TLP request packeti-1Plus the length of the previous TLP request packet, the new data length b to be readiLength b of data to be read corresponding to previous TLP request packeti-1Minus the length of the previous TLP request packet.
Further, the TLP packet encapsulation rule is specifically:
presetting the head address of the area to be written as c1Length of data to be written is d1When the first address c1When the boundary length of 4KB is greater than or equal to the Payload, the encapsulation length of the current TLP data packet is the Payload and the data length d to be written1The smallest of the above; when the first address c1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP packet takes the head address c1Length to 4KB boundary and length of data to be written d1The smallest one of them.
Further, after the previous TLP packet is encapsulated, a new head address c needs to be redefined for a subsequent to-be-written areaiAnd a new length d of data to be writteniThen new head address ciIs the head address c of the previous TLP packeti-1Plus the length of the previous TLP packet, the new length d of data to be writteniThe length d of data to be written corresponding to the previous TLP data packeti-1The length of the previous TLP packet is subtracted.
Further, the number of the 4KB boundaries is m, each 4KB boundary represents a physical address of the host, and the length of the physical address of the nth 4KB boundary is n × 4096, and n is less than or equal to m.
The PCIE-based DMA data processing system and method provided by the invention solve the problem that a TLP packet is discarded when crossing a 4KB boundary in a hardware mode, and compared with the traditional software solution mode, the hardware mode provided by the invention does not need a CPU (central processing unit) to configure a DMA controller for many times, thereby reducing the burden of the CPU, improving the data transmission efficiency and further saving the data processing cost.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and those skilled in the art should make modifications to the specific embodiments of the present invention or make equivalent substitutions for part of technical features without departing from the spirit of the technical solutions of the present invention, and all of them should be covered in the technical solutions claimed in the present invention.

Claims (10)

1. A PCIE-based DMA data transfer system, the system comprising: the system comprises PCIE equipment and a host, wherein the PCIE equipment carries out data interaction with the host through a PCIE bus;
the PCIE device: the device comprises a DMA module, a data processing module and a data processing module, wherein the DMA module is used for reading data in the host and/or writing data in the PCIE equipment into the host;
when the DMA module reads data in the host, the DMA module receives a first address and a data size of data to be read, which are fed back by the host, and formulates an encapsulation rule of a TLP request packet by combining a predetermined Payload, so that each encapsulated TLP request packet does not cross a 4KB boundary;
when the DMA module writes data into the host, the DMA module receives the first address of the to-be-written area fed back by the host, and formulates an encapsulation rule of the TLP data packet by combining the data size of the to-be-written data and a predetermined Payload, so that each TLP data packet after encapsulation does not cross a 4KB boundary.
2. The PCIE-based DMA data transmission system according to claim 1, wherein the Payload is a maximum length of a TLP request packet or a TLP packet allowed to be encapsulated, which is negotiated between the PCIE device and the host.
3. The PCIE-based DMA data transmission system of claim 1, wherein a preset head address of data to be read is a1The length of data to be read is b1When the first address a1When the boundary length of 4KB is greater than or equal to the Payload, the Payload and the data length b to be read are taken from the encapsulation length of the current TLP request packet1The smallest of the above; when the first address a1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP request packet takes the first address a1Length to 4KB boundary and data length to be read b1The smallest one of them.
4. The PCIE-based DMA data transmission system according to claim 3, wherein after a previous TLP request packet is encapsulated, a new first address a needs to be redefined for subsequent data to be readiAnd a new length b of data to be readiThen the new head address aiFirst address a of a previous TLP request packeti-1Plus the length of the previous TLP request packet, the new data length b to be readiLength b of data to be read corresponding to previous TLP request packeti-1Minus the length of the previous TLP request packet.
5. The PCIE-based DMA data transmission system of claim 1, wherein a preset head address of a to-be-written area is c1Length of data to be written is d1When the first address c1When the boundary length of 4KB is greater than or equal to the Payload, the encapsulation length of the current TLP data packet is the Payload and the data length d to be written1The smallest of the above; when the first address c1When the boundary length to 4KB is smaller than the Payload, the encapsulation length of the current TLP packet takes the head address c1Length to 4KB boundary and length of data to be written d1The smallest one of them.
6. The PCIE-based DMA data transfer of claim 5The transmission system is characterized in that after a current TLP data packet is encapsulated, a new first address c needs to be redefined for a subsequent area to be writteniRedefining the length d of the subsequent data to be writteniThen new head address ciIs the head address c of the previous TLP packeti-1Plus the length of the previous TLP packet, the new length d of data to be writteniThe length d of data to be written corresponding to the previous TLP data packeti-1The length of the previous TLP packet is subtracted.
7. A PCIE-based DMA data transfer system as recited in claim 1, wherein the 4KB boundaries are m, each 4KB boundary represents a physical address of the host, the nth 4KB boundary has a physical address length of n x 4096, and n is less than or equal to m.
8. The PCIE-based DMA data transmission system according to claim 1, wherein the PCIE device further includes a data processing module, the data processing module is used for receiving and processing the data read from the host by the DMA module, and after the processing is completed, the DMA module writes the processed data into the host.
9. A PCIE-based DMA data transmission method applied to the PCIE-based DMA data transmission system according to any one of claims 1 to 8, where the method includes:
the host feeds back the initial address and the data size of the data to be read to the DMA module;
the DMA module formulates an encapsulation rule of the TLP request packet according to the first address and the data size of the data to be read and in combination with a predetermined Payload, so that each TLP request packet after encapsulation does not cross a 4KB boundary;
the DMA module encapsulates the TLP request packet according to the encapsulation rule of the TLP request packet, and sends the TLP request packet after encapsulation to the host;
and the host returns a TLP completion packet carrying data to complete the process of reading the data from the host by the DMA module.
10. The PCIE-based DMA data transfer method of claim 9, wherein the method further comprises:
the host feeds back the first address of the area to be written to the DMA module;
the DMA module establishes a TLP data packet encapsulation rule according to the head address of the area to be written and the size of the data volume to be written and in combination with a predetermined Payload, so that each TLP data packet after encapsulation does not cross a 4KB boundary;
and the DMA module encapsulates the data to be written into a TLP data packet according to the encapsulation rule of the TLP data packet, and transmits the encapsulated TLP data packet to the host so as to complete the process of writing the data into the host by the DMA module.
CN201910933066.9A 2019-09-29 2019-09-29 PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method Pending CN110688333A (en)

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CN112328520A (en) * 2020-09-30 2021-02-05 郑州信大捷安信息技术股份有限公司 PCIE equipment, and data transmission method and system based on PCIE equipment
CN112328519A (en) * 2020-09-30 2021-02-05 郑州信大捷安信息技术股份有限公司 PCIE equipment, and SR-IOV-based data packet ordered transmission method and system
CN113204515A (en) * 2021-06-02 2021-08-03 郑州信大捷安信息技术股份有限公司 Flow control system and method in PCIE application layer data receiving process
CN113485951A (en) * 2021-07-31 2021-10-08 郑州信大捷安信息技术股份有限公司 DMA read operation implementation method based on FPGA, FPGA equipment and communication system
CN113821475A (en) * 2021-11-22 2021-12-21 湖北芯擎科技有限公司 Data transmission method and device, electronic equipment and storage medium
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CN112328520A (en) * 2020-09-30 2021-02-05 郑州信大捷安信息技术股份有限公司 PCIE equipment, and data transmission method and system based on PCIE equipment
CN112328519A (en) * 2020-09-30 2021-02-05 郑州信大捷安信息技术股份有限公司 PCIE equipment, and SR-IOV-based data packet ordered transmission method and system
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CN112328519B (en) * 2020-09-30 2022-02-18 郑州信大捷安信息技术股份有限公司 PCIE equipment, and SR-IOV-based data packet ordered transmission method and system
CN113204515A (en) * 2021-06-02 2021-08-03 郑州信大捷安信息技术股份有限公司 Flow control system and method in PCIE application layer data receiving process
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CN113485951A (en) * 2021-07-31 2021-10-08 郑州信大捷安信息技术股份有限公司 DMA read operation implementation method based on FPGA, FPGA equipment and communication system
CN113485951B (en) * 2021-07-31 2022-02-11 郑州信大捷安信息技术股份有限公司 DMA read operation implementation method based on FPGA, FPGA equipment and communication system
CN113821475A (en) * 2021-11-22 2021-12-21 湖北芯擎科技有限公司 Data transmission method and device, electronic equipment and storage medium
CN115828332A (en) * 2023-02-24 2023-03-21 三未信安科技股份有限公司 Method and system for strengthening PCI password card to resist timing attack
CN115828332B (en) * 2023-02-24 2024-04-19 三未信安科技股份有限公司 Method and system for enhancing PCI cipher card to resist timing attack

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