CN117555836A - Data processing device, system and electronic equipment - Google Patents
Data processing device, system and electronic equipment Download PDFInfo
- Publication number
- CN117555836A CN117555836A CN202311576289.7A CN202311576289A CN117555836A CN 117555836 A CN117555836 A CN 117555836A CN 202311576289 A CN202311576289 A CN 202311576289A CN 117555836 A CN117555836 A CN 117555836A
- Authority
- CN
- China
- Prior art keywords
- data
- memory
- module
- request
- task request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012545 processing Methods 0.000 title claims abstract description 98
- 230000005540 biological transmission Effects 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 52
- 230000008569 process Effects 0.000 claims description 49
- 230000002776 aggregation Effects 0.000 claims description 21
- 238000004220 aggregation Methods 0.000 claims description 21
- 238000013507 mapping Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000012546 transfer Methods 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 101150071434 BAR1 gene Proteins 0.000 description 1
- 101100378536 Ovis aries ADRB1 gene Proteins 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002939 poly(N,N-dimethylacrylamides) Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses a data processing device, a system and an electronic device, which relate to the field of data processing and aim at solving the problem that a host cannot directly and efficiently read and write a large-capacity memory of network card equipment; the first memory access module is used for supporting a high-speed link protocol and directly executing operation corresponding to the task request on the storage module; and the second memory access module is used for requesting a corresponding data frame from the memory of the host according to the task request and executing corresponding operation on the storage module based on the received data frame. The invention can enable the host to directly access the transmission layer of the storage module in the electronic equipment without mapping to the memory space of the host, and reduces the occupation of the memory and the bandwidth of the host and the bandwidth of the bus link.
Description
Technical Field
The present invention relates to the field of data processing, and in particular, to a data processing apparatus, a system, and an electronic device.
Background
At present, when the network card device works, the host memory needs to be applied first, after the host processing is completed, the network card DMA (Direct Memory Access ) controller is informed to read data from the host memory into the network card device, and then the data is sent out through the optical port. In the process, the network card device occupies the memory resources of the host and has higher bandwidth, and the host in the prior proposal can not directly and efficiently read and write the large-capacity memory of the network card device, and can copy the data of the host memory into the memory of the network card device only in a DMA mode, thereby not only wasting the memory resources and the memory bandwidth of the host, but also occupying the link bandwidth of PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard).
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention provides a data processing device, a system and electronic equipment, which can enable a host to directly access a transmission layer of a storage module in the electronic equipment without mapping to a host memory space, and reduce occupation of host memory and bandwidth of a bus link.
In order to solve the above technical problems, the present invention provides a data processing apparatus, which is applied to an electronic device, the electronic device includes a storage module, and the data processing apparatus includes:
the system comprises a computing high-speed link hard core module compatible with a high-speed serial computer expansion bus standard, a target memory access module, a first memory access module and a second memory access module, wherein the computing high-speed link hard core module is used for acquiring a task request sent by a host, determining the target memory access module corresponding to the task request, and issuing the task request to the target memory access module, and the target memory access module is the first memory access module or the second memory access module;
the first memory access module supporting a computing high-speed link protocol is used for directly executing the operation corresponding to the task request on the storage module;
the second memory access module is configured to request a corresponding data frame from the memory of the host according to the task request, and execute a corresponding operation on the storage module based on the received data frame.
In an exemplary embodiment, the process of determining the target memory access module corresponding to the task request includes:
acquiring frame header information of a data frame corresponding to the task request;
and determining a target memory access module based on the target identification in the frame header information.
In an exemplary embodiment, the process of requesting the corresponding data frame from the memory of the host according to the task request includes:
acquiring at least one descriptor information from the memory of the host according to the task request;
judging whether all the descriptor information meets aggregation conditions;
if yes, acquiring all data frames corresponding to the descriptor information from the memory of the host.
In an exemplary embodiment, the process of determining whether all the descriptor information satisfies an aggregation condition includes:
when the number of the descriptor information is multiple, determining a source address and a destination address of data corresponding to each piece of descriptor information;
judging whether the source addresses corresponding to all the descriptor information are discontinuous and the destination addresses corresponding to all the descriptor information are continuous;
if yes, judging that all the descriptor information meets the aggregation condition;
if not, judging that all the descriptor information does not meet the aggregation condition.
In an exemplary embodiment, the second memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and the process of performing corresponding operations on the storage module based on the received data frame includes:
Determining frame header information of the received data frame;
determining a target output interface among a plurality of the output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
In an exemplary embodiment, the storage module includes a register, the data processing apparatus further includes a data frame processing module, and a plurality of the output interfaces of the second memory access module include a first output interface for connecting to the data frame processing module;
and the data frame processing module is used for processing the register based on the target task request when the target task request is received.
In an exemplary embodiment, the storage module further includes a memory, and a second output interface for connecting to the memory is further included in the plurality of output interfaces;
the process of determining a target output interface among the plurality of output interfaces based on the frame header information includes:
judging whether the data frame corresponds to a base address register space request or not based on the frame header information;
When the data frame corresponds to a base address register space request, determining that the target output interface is the first output interface;
when the data frame does not correspond to the base address register space request, judging whether the data frame corresponds to a memory direct access request or not based on the frame header information;
when the data frame corresponds to a memory direct access request, determining that the target output interface is the second output interface;
and discarding the data frame when the data frame does not correspond to the memory direct access request.
In an exemplary embodiment, the interface protocol type corresponding to the first output interface is a lightweight advanced extended register interface protocol, and the interface protocol type corresponding to the second output interface is an advanced extensible interface protocol.
In an exemplary embodiment, the first memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and the process of directly executing the operation corresponding to the task request on the storage module includes:
determining frame header information of a data frame corresponding to the received task request;
determining a target output interface among a plurality of the output interfaces based on the frame header information;
Obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
In an exemplary embodiment, the storage module includes a memory, where a storage space of the memory is uniformly divided into a plurality of memory blocks, at least one of the memory blocks is used as a receiving memory interval, and at least one of the memory blocks is used as a transmitting memory interval;
the host is further configured to update descriptor information of the transmission memory interval after completing a write operation on one of the transmission memory intervals;
the first memory access module is further configured to read a data frame of the transmission memory interval corresponding to the descriptor information after the descriptor information updated by the host is monitored.
In an exemplary embodiment, the first memory access module is further configured to update descriptor information of the receiving memory interval after writing data in a received data frame sent by the host into the receiving memory interval corresponding to the data frame, so as to inform the host to read data from the receiving memory interval.
In an exemplary embodiment, the descriptor information corresponding to each memory block includes a start address, a length, an occupancy, a read-write status, a data processing completion status, and reserved bit information.
In an exemplary embodiment, updating the descriptor information of the receiving memory space to inform the host of the process of reading data from the receiving memory space includes:
updating the descriptor information of the receiving memory interval, and sending an interrupt instruction to the host so as to inform the host to read data from the receiving memory interval.
In an exemplary embodiment, the first memory access module includes:
and the block storage unit is used for storing the descriptor information.
In an exemplary embodiment, the block storage unit is mounted on a register space of the first memory access module.
In an exemplary embodiment, the data processing apparatus further includes:
the arbitration module comprises a block storage unit, and is used for judging whether data corresponding to a read task request is stored in the block storage unit or not when the read task request sent by a request end is received by the arbitration module;
if yes, acquiring data corresponding to the read task request from the block storage unit, and returning the data to the request end;
if not, acquiring the data corresponding to the read task request from the storage module, and returning the data to the request end.
In an exemplary embodiment, the process of determining whether the data corresponding to the read task request is stored in the block storage unit includes:
acquiring a starting address and a length of data corresponding to the read task request;
and judging whether the data corresponding to the read task request is stored in the block storage unit or not based on the starting address and the length.
In an exemplary embodiment, the process of determining whether the data corresponding to the read task request is stored in the block storage unit based on the start address and the length includes:
judging whether all data corresponding to the read task request are stored in the block storage unit or not based on the starting address and the length;
the process of acquiring the data corresponding to the read task request from the block storage unit and returning the data to the request end comprises the following steps:
if all the data corresponding to the read task request are stored in the block storage unit, returning all the data to the request end;
if the partial data corresponding to the read task request is stored in the block storage unit, returning the partial data to the request end;
The arbitration module is further configured to request data with a preset length from the storage module while returning the part of data to the request end, and write the data with the preset length returned by the storage module into the block storage unit, where the data with the preset length includes data corresponding to the read task request.
In an exemplary embodiment, the arbitration module is further configured to request a preset length of data from the storage module while returning all the data to the request end, and write the preset length of data returned by the storage module into the block storage unit.
In an exemplary embodiment, the process of acquiring the data corresponding to the read task request from the storage module and returning the data to the request end includes:
and requesting the data corresponding to the starting address and the length from the storage module, and sending the data returned by the storage module to the request end.
In an exemplary embodiment, the arbitration module is further configured to request, while sending the data returned by the storage module to the request end, data with a preset length from the storage module, and write the data with the preset length returned by the storage module into the block storage unit.
In order to solve the technical problem, the invention also provides electronic equipment, which comprises the storage module and the data processing device.
In order to solve the technical problem, the invention also provides a data processing system which comprises a host, a high-speed serial computer expansion bus standard bus and the electronic equipment, wherein the host and the electronic equipment are connected through the high-speed serial computer expansion bus standard bus.
The invention provides a data processing device, which is arranged in an electronic device, wherein the data processing device comprises a computing high-speed link hard core module compatible with a high-speed serial computer expansion bus standard and is used for receiving a task request sent by a host and sending the task request to a corresponding memory access module. The invention also provides an electronic device and a data processing system, which have the same beneficial effects as the data processing method.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a schematic diagram of a data processing apparatus according to the present invention;
FIG. 2 is a schematic diagram of another data processing apparatus according to the present invention;
FIG. 3 is a schematic diagram illustrating a data frame moving process according to the present invention;
FIG. 4 is a flow chart of memory access according to the present invention;
FIG. 5 is a state diagram of memory block assignment provided by the present invention;
FIG. 6 is a flowchart of a buffering process according to the present invention.
Detailed Description
The core of the invention is to provide a data processing device, a system and an electronic device, which can enable a host to directly access a transmission layer of a storage module in the electronic device without mapping to a host memory space, and reduce occupation of host memory and bandwidth of a bus link.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a data processing apparatus according to the present invention, where the data processing apparatus includes:
the computing high-speed link hard core module 1 compatible with the high-speed serial computer expansion bus standard is used for acquiring a task request sent by a host, determining a target memory access module corresponding to the task request, and issuing the task request to the target memory access module, wherein the target memory access module is a first memory access module 2 or a second memory access module 3;
the first memory access module 2 supporting the high-speed link protocol is used for directly executing the operation corresponding to the task request on the storage module;
and the second memory access module 3 is used for requesting a corresponding data frame from the memory of the host according to the task request and executing a corresponding operation on the storage module based on the received data frame.
It can be appreciated that the data processing apparatus of this embodiment is provided in an electronic device, and the host may interact with the storage module in the electronic device through the data processing apparatus. Considering that a conventional DMA-based data transmission scheme, a host cannot directly and efficiently access a storage module in an electronic device, and the high-speed computing link technology CXL (Compute Express Link) is a dynamic multi-protocol technology, aiming to support an accelerator and a memory device, CXL provides a rich set of protocols including PCIe-like I/O semantics (i.e., cxl.io), cache protocol semantics (i.e., cxl.cache), direct connection and distributed memory access semantics (i.e., cxl.mem), based on which the data processing apparatus in the present embodiment includes the first memory access module 2 based on the Type3 mem (Type 3 storage) protocol in the CXL3.0 standard, the host can directly access the extended memory on the device through the first memory access module 2 without mapping to the memory space of the host, thereby reducing the occupation of the host memory address.
In this embodiment, in order to enable the data processing apparatus to operate in PCIe DMA mode to be compatible with the conventional network card, a computing high-speed link hard core module 1 compatible with the high-speed serial computer expansion bus standard and a second memory access module 3 for implementing the conventional DMA transfer function are correspondingly provided. The computing high-speed link hard core module 1 is connected with the host side through a PCIe link, in this embodiment, the PCIe link is a physical link above the PCIe Gen5 standard, so as to be compatible with a conventional PCIe DMA scheme below the Gen5 standard and a CXL-based data processing scheme.
After receiving the task request sent by the host, the computing high-speed link hard core module 1 judges whether the task request needs to be processed by the first memory access module 2 or processed by the second memory access module 3, and sends the task request to the corresponding target memory access module, and if the first memory access module 2 receives the task request sent by the computing high-speed link hard core module 1, the task request is directly responded to, and the writing operation or the reading operation on the storage module is completed. The second memory access module 3 receives the task request sent by the computation high-speed link hard core module 1, requests the descriptor from the host firstly, requests data corresponding to the descriptor information from the host according to the descriptor information requested by the host, and completes writing operation or reading operation on the storage module based on the data frame after receiving the data frame returned by the host.
It can be seen that, in this embodiment, a data processing apparatus is provided in an electronic device, where the data processing apparatus includes a computing high-speed link hard core module 1 compatible with a high-speed serial computer expansion bus standard, and is configured to receive a task request sent by a host, and send the task request to a corresponding memory access module, and the data processing apparatus is provided with a first memory access module 2 supporting a computing high-speed link protocol, and defines, based on the high-speed link protocol, a transport layer of a storage module in the electronic device that can be directly accessed by the host, without mapping to a host memory space, thereby reducing occupation of host memory and bandwidth of a PCIe link.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another data processing apparatus according to the present invention, where the data processing apparatus is based on the above embodiment:
in an exemplary embodiment, the process of determining the target memory access module corresponding to the task request includes:
acquiring frame header information of a data frame corresponding to the task request;
and determining a target memory access module based on the target identification in the frame header information.
It may be understood that the correspondence between the target identifier and the memory access module is preset, for example, the target identifier is a, where the target identifier corresponds to the first memory access module 2, for example, the target identifier is b, and the target identifier corresponds to the second memory access module 3. After the computing high-speed link hard core module 1 receives a task request transmitted from a PCIe link, analyzing frame header information of a data frame corresponding to the task request, acquiring a target identification in the frame header information, determining that the target memory access module is the first memory access module 2 if the target identification is a, and determining that the target memory access module is the second memory access module 3 if the target identification is b.
Of course, the above target identifiers are only used as examples, and a plurality of target identifiers may be set corresponding to the first memory access module 2, a plurality of target identifiers may be set corresponding to the second memory access module 3, and the present embodiment is not limited specifically herein.
In an exemplary embodiment, the process of requesting a corresponding data frame from the memory of the host according to the task request includes:
acquiring at least one descriptor information from a memory of a host according to a task request;
judging whether all descriptor information meets aggregation conditions;
if so, acquiring data frames corresponding to all descriptor information from the memory of the host.
When the target memory access module is the second memory access module 3, the data needs to be moved from the memory of the host by using a traditional DMA scheme, and when the physical memory is in a regular discontinuous state, the second memory access module 3 can aggregate descriptors corresponding to a plurality of fragment data movement tasks into one DMA descriptor according to the size of the interval address, so that the second memory access module 3 moves data frames according to the DMA descriptor information. Referring to fig. 3, 0 to 0×17f_ffff in fig. 3 is an address corresponding to each segment. When moving data from a source address to a destination address, in the conventional scheme, two DMA transmissions are required to complete the data frame transfer, i.e., the first DMA transmission transfers the data frames of the segment 1 and the segment 2, and the second DMA transmission transfers the data frames of the segment 3 and the segment 4. In this embodiment, in order to improve DMA performance, after at least one descriptor information is returned from the host according to a task request to the host, if the descriptor information returned from the host is multiple, it is determined whether the multiple descriptor information satisfies an aggregation condition, and when the aggregation condition is satisfied, a data frame corresponding to the multiple descriptor information is obtained from the memory of the host at one time, that is, a data frame of segment 1, segment 2, segment 3, and segment 4 is moved in one DMA transmission.
The source address is the address of the data frame in the memory of the host, and the destination address is the address of the data frame in the memory module of the electronic device.
In an exemplary embodiment, the process of determining whether all descriptor information satisfies an aggregation condition includes:
when the number of the descriptor information is multiple, determining a source address and a destination address of data corresponding to each descriptor information;
judging whether source addresses corresponding to all descriptor information are discontinuous and destination addresses corresponding to all descriptor information are continuous;
if yes, judging that all descriptor information meets the aggregation condition;
if not, judging that all descriptor information does not meet the aggregation condition.
In this embodiment, the aggregation condition is defined, where the aggregation condition includes, but is not limited to, that source addresses corresponding to all descriptor information are discontinuous, but destination addresses corresponding to all descriptor information are continuous, and similarly, when the destination addresses are discontinuous, the second memory access module 3 may write the data frames into the memory segments of the interval addresses respectively.
It can be understood that the second memory access module 3 has a scatter gather function, and supports data movement of discontinuous and fixed-interval addresses (including discontinuous source addresses and discontinuous destination addresses), so that DMA performance can be increased when the addresses are discontinuous, and requirements on continuity of a system memory can be reduced.
In an exemplary embodiment, the second memory access module 3 includes a plurality of output interfaces, and the interface protocol types of the plurality of output interfaces are different, and the process of performing the corresponding operation on the storage module based on the received data frame includes:
determining frame header information of a received data frame;
determining a target output interface among the plurality of output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface. In an exemplary embodiment, the storage module includes a register, the data processing apparatus further includes a data frame processing module 4, and a first output interface for connecting to the data frame processing module 4 is included in the plurality of output interfaces of the second memory access module 3;
and the data frame processing module 4 is used for processing the register based on the target task request when the target task request is received.
In an exemplary embodiment, the memory module further includes a memory 5, and the plurality of output interfaces further includes a second output interface for connecting to the memory 5;
the process of determining a target output interface among the plurality of output interfaces based on the frame header information includes:
Judging whether the data frame corresponds to a base address register space request or not based on the frame header information;
when the data frame corresponds to the space request of the base address register, determining that the target output interface is a first output interface;
when the data frame does not correspond to the space request of the base address register, judging whether the data frame corresponds to the direct memory access request or not based on the frame header information;
when the data frame corresponds to the memory direct access request, determining that the target output interface is a second output interface;
and when the data frame does not correspond to the memory direct access request, discarding the data frame.
In an exemplary embodiment, the interface protocol type corresponding to the first output interface is a lightweight advanced extended register interface protocol, and the interface protocol type corresponding to the second output interface is an advanced extensible interface protocol.
In this embodiment, the second memory access module 3 includes a plurality of output interfaces, the interface protocol types of the different output interfaces are different, further, the storage module includes a register and a memory 5, the memory 5 may be a high bandwidth memory 5, when the host accesses the register space, the data frame processing module 4 needs to be passed through, the second memory access module 3 is connected with the data frame processing module 4 and the memory 5 through different buses, for example, the second memory access module 3 is connected with the memory 5 through an AXI4-MM bus, the second memory access module 3 is connected with the data frame processing module 4 through an AXI4-Lite bus, and accordingly, the plurality of output interfaces includes a first output interface for connecting with the data frame processing module 4, and a second output interface for connecting with the memory 5, where the interface protocol type corresponding to the first output interface is a lightweight advanced extended register interface protocol, and the interface protocol type corresponding to the second output interface is an advanced extended interface protocol.
It will be appreciated that, referring to fig. 4, the memory access flow chart of the second memory access module 3 refers to the memory access flow chart of fig. 4, detects and calculates whether the TLP data frame of the memory request is output by the high-speed link kernel module, after receiving the TLP (Transaction Layer Packet ) data frame, analyzes and extracts the frame header information of the TLP data frame, determines whether the frame header information corresponds to an AXI4-Lite (lightweight advanced extensible) 32-bit base address register space request, if so, converts the frame header information into an AXI4-Lite bus read-write request, that is, a target task request, if not, determines whether the frame header information corresponds to a 64-bit BAR (base address register) 4 memory direct access request, if not, filters and discards, if so, converts the frame header information into an AXI4-MM (advanced extensible) bus read-write request, that is, a target task request, and sends the target task request to the corresponding output interface of the second memory access module.
In an exemplary embodiment, the first memory access module 2 includes a plurality of output interfaces, and interface protocol types of the plurality of output interfaces are different, and a process of directly executing an operation corresponding to a task request on the storage module includes:
determining frame header information of a data frame corresponding to the received task request;
Determining a target output interface among the plurality of output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
It can be understood that the first memory access module 2 also includes a plurality of output interfaces, and the manner of determining the target output interface for outputting the target task request is referred to the second memory access module 3, which is not described herein again.
In an exemplary embodiment, the storage module includes a memory 5, where a storage space of the memory 5 is uniformly divided into a plurality of memory blocks, at least one memory block is used as a receiving memory interval, and at least one memory block is used as a transmitting memory interval;
the host is also used for updating the descriptor information of a transmission memory interval after finishing the writing operation of the transmission memory interval;
the first memory access module 2 is further configured to read a data frame of a transmission memory interval corresponding to the descriptor information after the descriptor information updated by the host is monitored.
In an exemplary embodiment, the first memory access module 2 is further configured to update the descriptor information of the receiving memory interval after writing the data in the received data frame sent by the host into the receiving memory interval corresponding to the data frame, so as to inform the host to read the data from the receiving memory interval.
In an exemplary embodiment, the descriptor information corresponding to each memory block includes a start address, a length, an occupancy, a read-write status, a data processing completion status, and reserved bit information.
In an exemplary embodiment, updating descriptor information of a received memory interval to inform a host of reading data from the received memory interval includes:
updating the descriptor information of the receiving memory interval, and sending an interrupt instruction to the host so as to inform the host to read data from the receiving memory interval.
In an exemplary embodiment, the first memory access module 2 includes:
and a block storage unit for storing the descriptor information.
In an exemplary embodiment, the block memory locations are mounted on the register space of the first memory access module 2.
In this embodiment, the memory space of the memory 5 in the electronic device is divided into multiple parts for implementing transmission/reception of the memory interval, and a BRAM is adopted in the FPGA to implement a descriptor queue having a description of the buffer states, where the state information includes a start address, a length, an occupation right (host/device), a read-write state, a data processing completion state, and reserved bit information of each memory block, so as to implement cyclic utilization of the memory blocks. It can be understood that the first memory access module 2 implements the transmission layer defined in the cxl.mem protocol, where the host directly accesses the device memory without mapping to the host memory space, and the host application may directly apply for using the memory space of the electronic device pair as a transmission/reception buffer interval for buffering the data frame, and after buffering is completed, notify the data frame processing module 4 to process the regional data frame and send out the regional data frame.
For example, assuming that the memory space of the device is 6GB, the initial state is equally divided into 6 equal parts of memory blocks, the initial state sending and receiving memory intervals are respectively implemented by 3 memory blocks, and the two memory intervals can be implemented by dynamically adjusting the memory blocks according to specific tasks: when the transmission task is more than the reception task, the descriptor information of the memory block can be changed to be 4 transmission memory intervals and 2 reception memory intervals, otherwise, referring to fig. 5, the left side of fig. 5 is the initial state, the right side is the dynamically adjusted state, 0-0x3fff_ffff in fig. 5 is the address of the first memory block, 0x4000_0000-0x_7fff_ff is the address of the second memory block, 0x8000_0000-0xbfff_ff is the address of the third memory block, 0x000_0000-0xffff_ff is the address of the fourth memory block, 0x1_0000-0x1_3fff_ff is the address of the fifth memory block, and 0x1_4000_0000-0x1_7fff_ff is the address of the sixth memory block.
When the host computer completes the writing task of a memory interval, the descriptor information is updated, the electronic equipment is informed to start sending data frames in the memory interval, the occupation weight is given to the electronic equipment, the electronic equipment starts reading the data frames in the memory block in the memory interval, and the data frames are processed and sent by the data frame processing module 4; otherwise, after the device completes the receiving process of the data frame and writes the data frame into the memory block occupied by the device, the descriptor information of the memory block is updated, the occupation right is given to the host, and an interrupt notification host is sent to read the memory section.
The descriptor information format of the memory block is shown in table 1, and includes a start address, a length, an occupancy right (host/device), a read-write state, a data processing completion state, and reserved bit information. These descriptor information are implemented in the FPGA using BRAM mounted on a dedicated register space BAR1 inside the CMA module, which is accessible and updatable by the first memory access module 2 itself and HOST via CXL channels.
Table 1 device memory block descriptor information table
| bit position | [127:98] | [97:90] | [89:89] | [88:88] | [87:80] | [79:64] | [63:0] |
| Description of the invention | Reserved bits | Error code | Completion status | Read-write status | Occupancy right | Length of | Start address |
In an exemplary embodiment, the data processing apparatus further includes:
the arbitration module 6, the arbitration module 6 includes a block storage unit, and the arbitration module 6 is used for judging whether the data corresponding to the read task request is stored in the block storage unit when the read task request sent by the request end is received;
if yes, acquiring data corresponding to the read task request from the block storage unit, and returning the data to the request end;
if not, acquiring the data corresponding to the read task request from the storage module, and returning the data to the request end.
In an exemplary embodiment, the process of determining whether data corresponding to a read task request is stored in a block storage unit includes:
Acquiring a starting address and a length of data corresponding to a read task request;
and judging whether the data corresponding to the read task request is stored in the block storage unit or not based on the starting address and the length.
In an exemplary embodiment, the process of determining whether data corresponding to the read task request is stored in the block storage unit based on the start address and the length includes:
judging whether all data corresponding to the read task request are stored in the block storage unit or not based on the initial address and the length;
the process of acquiring the data corresponding to the read task request from the block storage unit and returning the data to the request end comprises the following steps:
if all the data corresponding to the read task request are stored in the block storage unit, returning all the data to the request end;
if the partial data corresponding to the read task request is stored in the block storage unit, returning the partial data to the request end;
the arbitration module 6 is further configured to request data with a preset length from the storage module while returning part of the data to the request end, and write the data with the preset length returned by the storage module into the block storage unit, where the data with the preset length includes data corresponding to the read task request.
In an exemplary embodiment, the arbitration module 6 is further configured to request the storage module for data with a preset length while returning all data to the request end, and write the data with the preset length returned by the storage module into the block storage unit.
In an exemplary embodiment, the process of acquiring data corresponding to a read task request from a storage module and returning the data to a request end includes:
and requesting the data corresponding to the initial address and the length from the storage module, and sending the data returned by the storage module to the request end.
In an exemplary embodiment, the arbitration module 6 is further configured to request the data with a preset length from the storage module while sending the data returned by the storage module to the request end, and write the data with the preset length returned by the storage module into the block storage unit.
The arbitration module 6 in this embodiment mainly accelerates the process of requesting the memory data of the device high bandwidth memory 5 by PCIe or cxl.mem, and the internal processing flow of the module is shown in fig. 6, and determines whether an HBM (High Bandwidth Memory ) read memory request is received, and when the HBM read memory request is received, analyzes the starting address and length of the read memory request, determines whether all the data are cached, that is, determines whether the data required by the HBM read memory request are cached in the BRAM (Block RAM, block storage unit) of the arbitration module 6, if yes, reads the Block storage unit, returns the hit data, and requests the high bandwidth memory for caching data with a preset length, where the preset length refers to the data with the next 4K length; if not, judging whether the part of the data is hit in the cache, namely judging that the part of the data required by the HBM read memory request is cached in the BRAM of the arbitration module 6, if so, returning part of the data which is hit in the BRAM firstly, and simultaneously requesting the next 4K data (including the missed 2K data); if all the data do not hit, a read request is initiated to the AXI4-MM bus according to the request address and the length, the data are directly sent to a request end after being returned, and meanwhile, the data with the preset length are requested to be cached from a high-bandwidth memory.
Further, the embodiment further includes a 100G media access controller 7 for interacting with the device memory through the data frame processing module 4.
It can be understood that the second memory access module 3 designs a device memory access through function, the memory of the electronic device can be mapped onto the high-capacity BAR4 fixed by PCIe IP through the interface, the host can directly initiate a PCIe standard memory read-write TLP request, access the device memory through the interface, and solve the problem that the traditional scheme cannot directly access the device memory; meanwhile, under the PCIe domain of the same NUMA node, the device memory can be directly accessed by other PCIe devices from point to point by using the interfaces, so that the memory data moving path between devices in the traditional scheme can be reduced, the step of caching to the host memory is omitted, and the occupancy rate to the host memory and bandwidth is reduced.
In summary, the invention is compatible with the traditional PCIe DMA data transmission mode, and provides a high-efficiency dispersion and aggregation DMA transmission mode, wherein the PDMA is designed with a BAR space for mounting a large memory of the equipment, thereby realizing direct memory access of a host and other PCIe equipment with the same node, reducing the memory access delay between the equipment, reducing the occupation of the memory bandwidth of a system and improving the DMA transmission efficiency between the equipment; the invention designs a CMA module based on CXL.mem protocol, which realizes the dynamic management of the equipment memory by matching with the driving software, and switches the ownership to realize the access of the host and the equipment to the same equipment memory area; the invention designs a descriptor queue implemented at a device end to record various states of a memory block of the device and storage information of an application data frame; according to the invention, an arbitration module is designed on a channel of the host accessing the memory of the device through PCIe/CXL, so that the data is cached, and the purposes of reducing the read memory delay and improving the memory read request efficiency are achieved.
In a second aspect, the present invention further provides an electronic device, including a storage module, and further including a data processing apparatus as any one of the above. The data processing apparatus includes:
the computing high-speed link hard core module compatible with the high-speed serial computer expansion bus standard is used for acquiring a task request sent by a host, determining a target memory access module corresponding to the task request, and issuing the task request to the target memory access module, wherein the target memory access module is a first memory access module or a second memory access module;
the first memory access module is used for supporting a high-speed link protocol and directly executing operation corresponding to the task request on the storage module;
and the second memory access module is used for requesting a corresponding data frame from the memory of the host according to the task request and executing corresponding operation on the storage module based on the received data frame.
In an exemplary embodiment, the process of determining the target memory access module corresponding to the task request includes:
acquiring frame header information of a data frame corresponding to the task request;
and determining a target memory access module based on the target identification in the frame header information.
In an exemplary embodiment, the process of requesting a corresponding data frame from the memory of the host according to the task request includes:
Acquiring at least one descriptor information from a memory of a host according to a task request;
judging whether all descriptor information meets aggregation conditions;
if so, acquiring data frames corresponding to all descriptor information from the memory of the host.
In an exemplary embodiment, the process of determining whether all descriptor information satisfies an aggregation condition includes:
when the number of the descriptor information is multiple, determining a source address and a destination address of data corresponding to each descriptor information;
judging whether source addresses corresponding to all descriptor information are discontinuous and destination addresses corresponding to all descriptor information are continuous;
if yes, judging that all descriptor information meets the aggregation condition;
if not, judging that all descriptor information does not meet the aggregation condition.
In an exemplary embodiment, the second memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and a process of performing a corresponding operation on the storage module based on the received data frame includes:
determining frame header information of a received data frame;
determining a target output interface among the plurality of output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
And outputting the target task request through the target output interface.
In an exemplary embodiment, the storage module includes a register, the data processing apparatus further includes a data frame processing module, and the plurality of output interfaces of the second memory access module includes a first output interface for connecting to the data frame processing module;
and the data frame processing module is used for processing the register based on the target task request when the target task request is received.
In an exemplary embodiment, the memory module further includes a memory, and the plurality of output interfaces further includes a second output interface for connecting to the memory;
the process of determining a target output interface among the plurality of output interfaces based on the frame header information includes:
judging whether the data frame corresponds to a base address register space request or not based on the frame header information;
when the data frame corresponds to the space request of the base address register, determining that the target output interface is a first output interface;
when the data frame does not correspond to the space request of the base address register, judging whether the data frame corresponds to the direct memory access request or not based on the frame header information;
when the data frame corresponds to the memory direct access request, determining that the target output interface is a second output interface;
and when the data frame does not correspond to the memory direct access request, discarding the data frame.
In an exemplary embodiment, the interface protocol type corresponding to the first output interface is a lightweight advanced extended register interface protocol, and the interface protocol type corresponding to the second output interface is an advanced extensible interface protocol.
In an exemplary embodiment, the first memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and a process of directly executing an operation corresponding to the task request on the storage module includes:
determining frame header information of a data frame corresponding to the received task request;
determining a target output interface among the plurality of output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
In an exemplary embodiment, the storage module includes a memory, where a storage space of the memory is uniformly divided into a plurality of memory blocks, at least one memory block is used as a receiving memory interval, and at least one memory block is used as a transmitting memory interval;
the host is also used for updating the descriptor information of a transmission memory interval after finishing the writing operation of the transmission memory interval;
the first memory access module is further configured to read a data frame of a transmission memory interval corresponding to the descriptor information after the descriptor information updated by the host is monitored.
In an exemplary embodiment, the first memory access module is further configured to update descriptor information of a receiving memory interval after writing data in a received data frame sent by the host into the receiving memory interval corresponding to the data frame, so as to inform the host to read the data from the receiving memory interval.
In an exemplary embodiment, the descriptor information corresponding to each memory block includes a start address, a length, an occupancy, a read-write status, a data processing completion status, and reserved bit information.
In an exemplary embodiment, updating descriptor information of a received memory interval to inform a host of reading data from the received memory interval includes:
updating the descriptor information of the receiving memory interval, and sending an interrupt instruction to the host so as to inform the host to read data from the receiving memory interval.
In an exemplary embodiment, the first memory access module includes:
and a block storage unit for storing the descriptor information.
In an exemplary embodiment, the block memory locations are mounted on a register space of the first memory access module.
In an exemplary embodiment, the data processing apparatus further includes:
the arbitration module comprises a block storage unit and is used for judging whether data corresponding to the read task request is stored in the block storage unit or not when the read task request sent by the request end is received;
If yes, acquiring data corresponding to the read task request from the block storage unit, and returning the data to the request end;
if not, acquiring the data corresponding to the read task request from the storage module, and returning the data to the request end.
In an exemplary embodiment, the process of determining whether data corresponding to a read task request is stored in a block storage unit includes:
acquiring a starting address and a length of data corresponding to a read task request;
and judging whether the data corresponding to the read task request is stored in the block storage unit or not based on the starting address and the length.
In an exemplary embodiment, the process of determining whether data corresponding to the read task request is stored in the block storage unit based on the start address and the length includes:
judging whether all data corresponding to the read task request are stored in the block storage unit or not based on the initial address and the length;
the process of acquiring the data corresponding to the read task request from the block storage unit and returning the data to the request end comprises the following steps:
if all the data corresponding to the read task request are stored in the block storage unit, returning all the data to the request end;
if the partial data corresponding to the read task request is stored in the block storage unit, returning the partial data to the request end;
The arbitration module is also used for requesting the data with the preset length from the storage module while returning part of the data to the request end, and writing the data with the preset length returned by the storage module into the block storage unit, wherein the data with the preset length comprises the data corresponding to the read task request.
In an exemplary embodiment, the arbitration module is further configured to request the storage module for data of a preset length while returning all the data to the request end, and write the data of the preset length returned by the storage module into the block storage unit.
In an exemplary embodiment, the process of acquiring data corresponding to a read task request from a storage module and returning the data to a request end includes:
and requesting the data corresponding to the initial address and the length from the storage module, and sending the data returned by the storage module to the request end.
In an exemplary embodiment, the arbitration module is further configured to request the data with the preset length from the storage module while sending the data returned by the storage module to the request end, and write the data with the preset length returned by the storage module into the block storage unit.
In a third aspect, the present invention also provides a data processing system, where the data processing system includes a host, a high-speed serial computer expansion bus standard bus, and the electronic device, and the host and the electronic device are connected by the high-speed serial computer expansion bus standard bus.
For an introduction to a data processing system provided by the present invention, reference should be made to the above embodiments, and the description of the present invention is omitted here.
The data processing system provided by the invention has the same beneficial effects as the data processing device.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (23)
1. A data processing apparatus, characterized by being applied to an electronic device including a storage module, comprising:
the system comprises a computing high-speed link hard core module compatible with a high-speed serial computer expansion bus standard, a target memory access module, a first memory access module and a second memory access module, wherein the computing high-speed link hard core module is used for acquiring a task request sent by a host, determining the target memory access module corresponding to the task request, and issuing the task request to the target memory access module, and the target memory access module is the first memory access module or the second memory access module;
the first memory access module supporting a computing high-speed link protocol is used for directly executing the operation corresponding to the task request on the storage module;
The second memory access module is configured to request a corresponding data frame from the memory of the host according to the task request, and execute a corresponding operation on the storage module based on the received data frame.
2. The data processing apparatus according to claim 1, wherein the process of determining the target memory access module corresponding to the task request comprises:
acquiring frame header information of a data frame corresponding to the task request;
and determining a target memory access module based on the target identification in the frame header information.
3. The data processing apparatus of claim 1, wherein requesting a corresponding data frame from the memory of the host according to the task request comprises:
acquiring at least one descriptor information from the memory of the host according to the task request;
judging whether all the descriptor information meets aggregation conditions;
if yes, acquiring all data frames corresponding to the descriptor information from the memory of the host.
4. A data processing apparatus according to claim 3, wherein the process of determining whether all of the descriptor information satisfies an aggregation condition comprises:
when the number of the descriptor information is multiple, determining a source address and a destination address of data corresponding to each piece of descriptor information;
Judging whether the source addresses corresponding to all the descriptor information are discontinuous and the destination addresses corresponding to all the descriptor information are continuous;
if yes, judging that all the descriptor information meets the aggregation condition;
if not, judging that all the descriptor information does not meet the aggregation condition.
5. The data processing apparatus according to claim 1, wherein the second memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and the process of performing the corresponding operation on the storage module based on the received data frame includes:
determining frame header information of the received data frame;
determining a target output interface among a plurality of the output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
6. The data processing apparatus of claim 5, wherein the storage module comprises a register, the data processing apparatus further comprising a data frame processing module, a plurality of the output interfaces of the second memory access module comprising a first output interface for connecting the data frame processing module;
And the data frame processing module is used for processing the register based on the target task request when the target task request is received.
7. The data processing apparatus of claim 6, wherein the memory module further comprises a memory, and wherein the plurality of output interfaces further comprises a second output interface for connecting to the memory;
the process of determining a target output interface among the plurality of output interfaces based on the frame header information includes:
judging whether the data frame corresponds to a base address register space request or not based on the frame header information;
when the data frame corresponds to a base address register space request, determining that the target output interface is the first output interface;
when the data frame does not correspond to the base address register space request, judging whether the data frame corresponds to a memory direct access request or not based on the frame header information;
when the data frame corresponds to a memory direct access request, determining that the target output interface is the second output interface;
and discarding the data frame when the data frame does not correspond to the memory direct access request.
8. The data processing apparatus of claim 7, wherein the interface protocol type corresponding to the first output interface is a lightweight advanced extended register interface protocol, and the interface protocol type corresponding to the second output interface is an advanced extensible interface protocol.
9. The data processing apparatus according to claim 1, wherein the first memory access module includes a plurality of output interfaces, interface protocol types of the plurality of output interfaces are different, and the process of directly performing the operation corresponding to the task request on the storage module includes:
determining frame header information of a data frame corresponding to the received task request;
determining a target output interface among a plurality of the output interfaces based on the frame header information;
obtaining a target task request corresponding to the interface protocol type of the target output interface according to the frame header information;
and outputting the target task request through the target output interface.
10. The data processing apparatus according to claim 9, wherein the memory module includes a memory, a memory space of the memory is uniformly divided into a plurality of memory blocks, at least one of the memory blocks is a receiving memory section, and at least one of the memory blocks is a transmitting memory section;
the host is further configured to update descriptor information of the transmission memory interval after completing a write operation on one of the transmission memory intervals;
the first memory access module is further configured to read a data frame of the transmission memory interval corresponding to the descriptor information after the descriptor information updated by the host is monitored.
11. The data processing apparatus according to claim 10, wherein the first memory access module is further configured to update descriptor information of the receiving memory space after writing data in the received data frame sent by the host into the receiving memory space corresponding to the data frame, so as to inform the host to read data from the receiving memory space.
12. The data processing apparatus of claim 11, wherein the descriptor information corresponding to each of the memory blocks includes a start address, a length, an occupancy, a read-write status, a data processing completion status, and reserved bit information.
13. The data processing apparatus of claim 11, wherein updating the descriptor information of the receive memory interval to inform the host to read data from the receive memory interval comprises:
updating the descriptor information of the receiving memory interval, and sending an interrupt instruction to the host so as to inform the host to read data from the receiving memory interval.
14. The data processing apparatus of claim 10, wherein the first memory access module comprises:
And the block storage unit is used for storing the descriptor information.
15. The data processing apparatus of claim 14, wherein the block storage unit is mounted on a register space of the first memory access module.
16. The data processing apparatus according to any one of claims 1 to 15, wherein the data processing apparatus further comprises:
the arbitration module comprises a block storage unit, and is used for judging whether data corresponding to a read task request is stored in the block storage unit or not when the read task request sent by a request end is received by the arbitration module;
if yes, acquiring data corresponding to the read task request from the block storage unit, and returning the data to the request end;
if not, acquiring the data corresponding to the read task request from the storage module, and returning the data to the request end.
17. The data processing apparatus of claim 16, wherein the process of determining whether the data corresponding to the read task request is stored in the block storage unit comprises:
acquiring a starting address and a length of data corresponding to the read task request;
And judging whether the data corresponding to the read task request is stored in the block storage unit or not based on the starting address and the length.
18. The data processing apparatus according to claim 17, wherein the process of determining whether the data corresponding to the read task request is stored in the block storage unit based on the start address and the length comprises:
judging whether all data corresponding to the read task request are stored in the block storage unit or not based on the starting address and the length;
the process of acquiring the data corresponding to the read task request from the block storage unit and returning the data to the request end comprises the following steps:
if all the data corresponding to the read task request are stored in the block storage unit, returning all the data to the request end;
if the partial data corresponding to the read task request is stored in the block storage unit, returning the partial data to the request end;
the arbitration module is further configured to request data with a preset length from the storage module while returning the part of data to the request end, and write the data with the preset length returned by the storage module into the block storage unit, where the data with the preset length includes data corresponding to the read task request.
19. The data processing apparatus of claim 18, wherein the arbitration module is further configured to request a predetermined length of data from the storage module and write the predetermined length of data returned by the storage module to the block storage unit while returning all of the data to the request terminal.
20. The data processing apparatus according to claim 17, wherein the process of acquiring the data corresponding to the read task request from the storage module and returning the data to the requesting end comprises:
and requesting the data corresponding to the starting address and the length from the storage module, and sending the data returned by the storage module to the request end.
21. The data processing apparatus according to claim 20, wherein the arbitration module is further configured to request a preset length of data from the storage module and write the preset length of data returned by the storage module into the block storage unit while transmitting the data returned by the storage module to the request terminal.
22. An electronic device comprising a memory module and further comprising a data processing apparatus as claimed in any one of claims 1 to 21.
23. A data processing system comprising a host computer, a high-speed serial computer expansion bus standard bus, and an electronic device according to claim 22, wherein the host computer and the electronic device are connected by the high-speed serial computer expansion bus standard bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311576289.7A CN117555836A (en) | 2023-11-23 | 2023-11-23 | Data processing device, system and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311576289.7A CN117555836A (en) | 2023-11-23 | 2023-11-23 | Data processing device, system and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117555836A true CN117555836A (en) | 2024-02-13 |
Family
ID=89816420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311576289.7A Pending CN117555836A (en) | 2023-11-23 | 2023-11-23 | Data processing device, system and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117555836A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117785755A (en) * | 2024-02-23 | 2024-03-29 | 北京超弦存储器研究院 | CXL memory module, resource allocation method, control chip, medium and system |
-
2023
- 2023-11-23 CN CN202311576289.7A patent/CN117555836A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117785755A (en) * | 2024-02-23 | 2024-03-29 | 北京超弦存储器研究院 | CXL memory module, resource allocation method, control chip, medium and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107992436B (en) | NVMe data read-write method and NVMe equipment | |
| US9678918B2 (en) | Data processing system and data processing method | |
| US6421746B1 (en) | Method of data and interrupt posting for computer devices | |
| EP3214550A1 (en) | Control of persistent memory via a computer bus | |
| CN117555836A (en) | Data processing device, system and electronic equipment | |
| US20120102245A1 (en) | Unified i/o adapter | |
| US6128674A (en) | Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue | |
| CN111309656B (en) | FPGA general DMA IP core | |
| CN113742269B (en) | Data transmission method, processing device and medium for EPA device | |
| WO2015027806A1 (en) | Read and write processing method and device for memory data | |
| WO2022007470A1 (en) | Data transmission method, chip, and device | |
| WO2021072721A1 (en) | Address translation method and apparatus | |
| CN110688333A (en) | PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method | |
| WO2023040464A1 (en) | Bus communication method and related device | |
| CN109101439B (en) | Message processing method and device | |
| CN110083548B (en) | Data processing method and related network element, equipment and system | |
| US7743179B2 (en) | Data transmission methods | |
| US10789001B1 (en) | Posted operation data control | |
| US20170147517A1 (en) | Direct memory access system using available descriptor mechanism and/or pre-fetch mechanism and associated direct memory access method | |
| US20080005399A1 (en) | Method and Apparatus for Determining the Status of Bus Requests and Responses | |
| CN111190840A (en) | Multi-party central processing unit communication architecture based on field programmable gate array control | |
| CN111694777B (en) | DMA transmission method based on PCIe interface | |
| KR20210152962A (en) | SYSTEM AND METHOD FOR PERFORMING TRANSACTION AGGREGATION IN A NETWORK-ON-CHIP (NoC) | |
| CN116601616A (en) | Data processing device, method and related equipment | |
| CN112559434A (en) | Multi-core processor and inter-core data forwarding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |