CN106919522A - A kind of dma controller based on PXI e interface - Google Patents
A kind of dma controller based on PXI e interface Download PDFInfo
- Publication number
- CN106919522A CN106919522A CN201511000955.8A CN201511000955A CN106919522A CN 106919522 A CN106919522 A CN 106919522A CN 201511000955 A CN201511000955 A CN 201511000955A CN 106919522 A CN106919522 A CN 106919522A
- Authority
- CN
- China
- Prior art keywords
- data
- volume
- transmitted
- address
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a kind of dma controller based on PXI e interface.The dma controller includes configuration register, for configuring according to volume of transmitted data and data transfer destination address；, for being more than 128Byte when volume of transmitted data, be then transmitted for data sectional according to volume of transmitted data and data transfer purpose first address by DMA control units：The data transfer purpose first address and volume of transmitted data of the data segment before calculating 4K borders less than 4K, calculating meets the data transfer purpose first address and volume of transmitted data of the data segment of 4K, and calculates the data transfer purpose first address and volume of transmitted data of the data segment behind 4K borders；Data transfer purpose first address and volume of transmitted data according to each data segment transmit all data.The present invention is solved the problems, such as in the data transmission not across 4KB borders, and does not need many configuration DMA parameters of CPU, saves the CPU time, improves running efficiency of system.
Description
Technical field
The present invention relates to observation and control technology field, more particularly to a kind of dma controller based on PXI e interface.
Background technology
With continuing to develop for technology, equipment has requirement higher to transmission speed and bandwidth.In actual observing and controlling
In system, the transmission of mass data can take the CPU more times so that when carrying out data transmission,
Main frame cannot carry out other operations.DMA controls are usually introduced in order to improve CPU efficiency, in TT＆C system
Device so that the transmission of data is not take up the time of CPU, improves the operational efficiency of system.
With the development of modern processors technology, in interconnection field, height differential bus replace parallel bus
It is trend of the times.Compared with single-ended parallel signal, high-speed differential signal can use clock frequency higher,
So as to use less holding wire, the bus for needing many single-ended parallel signal datas can be only achieved before completion
Bandwidth.Compared with pci bus, PXIe buses can support dual transfer mode with each passage unshared bandwidth
With data subchannel transmission mode.Meanwhile, PXIe buses are based on point-to-point interconnection, can effectively mention system
Robustness.
Based on the advantage of PXIe buses, the data transfer that can be used between dma controller and host computer.
But when DMA controls are communicated by PXIe buses with other PXIe equipment, the data transmitted
Message is packaged into TLP by transaction layer first, could be sent out by each chromatography of PXIe buses afterwards
Go.But PXIe buses specify that the data area transmitted can not cross-domain 4KB borders.Traditional solution party
Method is solved by software mode, but the shortcoming of the method is to need the CPU to be carried out to dma controller for many times
Configuration is, it is necessary to take the time of CPU.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of dma controller based on PXI e interface,
It is used to solve CPU in the prior art to configure dma controller many times, it is necessary to be taken the time of CPU
Problem.
According to an aspect of of the present present invention, there is provided a kind of dma controller based on PXI e interface, including：
Configuration register, for configuration data transmission quantity and data transfer purpose first address；
DMA control units, for judging whether volume of transmitted data meets 128Byte；
When the volume of transmitted data is more than 128Byte, then according to the volume of transmitted data and the data transfer mesh
First address data sectional is transmitted：
The data transfer purpose first address and volume of transmitted data of the data segment before calculating 4K borders less than 4K,
And judge remaining data transmission quantity whether more than 4K；
When the remaining data transmission quantity is more than 4K, then the data transfer mesh of the data segment for meeting 4K is calculated
First address and volume of transmitted data, and calculate the data segment behind 4K borders data transfer purpose first address and
Volume of transmitted data；
When the remaining data volume of transmitted data is less than or equal to 4K, then 4K post-boundary datas section is calculated
Data transfer purpose first address and volume of transmitted data；
Data transfer purpose first address and volume of transmitted data according to each data segment transmit all data.
Preferably, the DMA control units are used for before data transfer, according in the configuration register
Reseting register is resetted.
Preferably, the DMA control units are used for before data transfer, according to opening for the configuration register
Dynamic register file is started.
Preferably, the data transfer direction that the DMA control units are used in the configuration register is posted
Storage control sends data to host computer or receives the data that host computer sends.
Preferably, the bus control signal that the DMA control units are used in the configuration register is posted
The opening of storage controlling bus coffret or closing.
Preferably, the dma controller is integrated in FPGA.
The present invention has following technique effect：
Dma controller based on PXI e interface provided by the present invention, is set by carrying out logic to FPGA
Meter, solves the problems, such as in the data transmission not across 4K borders, and does not need many configurations of CPU
DMA parameters, reduce holding time of the data transfer to CPU, improve the whole efficiency of system, and
And can extensive use in the requirement in big broadband.
Described above is only the general introduction of technical solution of the present invention, in order to better understand technology of the invention
Means, and being practiced according to the content of specification, and in order to allow above and other objects of the present invention,
Feature and advantage can become apparent, below especially exemplified by specific embodiment of the invention.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to implementing
Example or the accompanying drawing to be used needed for description of the prior art are briefly described, it should be apparent that, retouch below
Accompanying drawing in stating only some embodiments of the present invention, for those of ordinary skill in the art, not
On the premise of paying creative labor, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the dma controller based on PXI e interface in the embodiment of the present invention；
Fig. 2 is the schematic diagram of dma controller division data segment in the embodiment of the present invention；
Fig. 3 is the flow chart of dma controller configuration register in the embodiment of the present invention；
Fig. 4 is the flow chart of dma controller controlling transmission data in the embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is only a part of embodiment of the invention, rather than
Whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creation
Property work under the premise of the every other embodiment that is obtained, belong to the scope of protection of the invention.
Referring to Fig. 1, the structural representation of the dma controller based on PXI e interface provided by the present invention,
Dma controller using FPGA realize, when dma controller carries out write operation, complete TLP data from
FPGA is to the transmission between host computer；When dma controller carries out read operation, TLP data are completed from upper
Transmission of the machine to FPGA.The maximum load number of a TLP is 128Byte in the present invention, if necessary to pass
Defeated more data need transmission multiple TLP.
Because the internal memory of PC is a point page management, a page-size is 4KB, to PC internal memory
When writing data, it is desirable to which the transmission of data is also required that not across 4KB borders in PXIe agreements
4KB (abbreviation 4K) border can be crossed over.
The dma controller based on PXI e interface in the present invention, as shown in figure 1, including configuration register
With DMA control units, specifically,
Configuration register, for configuring according to volume of transmitted data and data transfer destination address；
DMA control units, for judging whether volume of transmitted data meets 128Byte：
When volume of transmitted data is less than or equal to 128Byte, directly enter line number with host computer by PXIe mouthfuls
According to transmission；
When volume of transmitted data is more than 128Byte, then according to volume of transmitted data and data transfer purpose first address by number
It is transmitted according to segmentation.
Specifically, calculate first data segment before 4K borders less than 4K data transfer purpose first address and
Volume of transmitted data, and judge to remove before the 4K borders for calculating remaining data biography after volume of transmitted data less than 4K
Whether throughput rate is more than 4K：
As shown in Fig. 2 when remaining data transmission quantity is more than 4K, then calculating the number of the data segment for meeting 4K
According to transmission purpose first address and volume of transmitted data, and the data transfer purpose for calculating the data segment behind 4K borders
First address and volume of transmitted data.In the case, the data that will be transmitted are divided into three sections, then according to three
The data transfer purpose first address and volume of transmitted data of data segment, will be all after a configuration register is configured
Data transfer.
And when remaining data volume of transmitted data is less than or equal to 4K, then calculate 4K post-boundary datas section
Data transfer purpose first address and volume of transmitted data.In the case, the data that will be transmitted are divided into two sections,
Data transfer purpose first address and volume of transmitted data according to two data segments transmit all data.
By the above method, the present invention is efficiently solved the problems, such as across 4KB borders.According to transmission data
The size of destination address and transmitted data amount judges whether across 4KB borders.For more than 4KB borders
Data need to carry out segment transmissions to it.Specifically, dma controller by the transmission of data block stage by stage,
One stage completed first address to first data of 4KB boundary addresses；Then when remaining data transmission quantity is more than
During 4K, remaining data amount is being divided into two sections；When remaining data transmission quantity be less than or equal to 4K when,
Using remaining data transmission quantity as a single data segment.So can be after a register be configured, by institute
End of transmission of some data, without many configuration DMA parameters of CPU, reduces data biography
The defeated holding time to CPU.
Dma controller controls the information of the configuration register for data transfer, specifically includes arrangement reset and posts
It is storage, data destination address register, data transfer size register, data transfer direction register, total
Line control signal register and startup register.When carrying out data transmission, dma controller configuration deposit
The process of device, referring to Fig. 3, comprises the following steps：
DMA handles are initialized first；
Secondly arrangement reset register, resets to dma controller；
Then configuration data destination address, data transfer size, data transfer direction and bus control signal
Register；
Then configuration DMA starts register, and control dma controller starts, and waits data transfer.
Referring to Fig. 4, DMA control units configure DMA parameters according to the configuration information of configuration register.Tool
Body ground, resets according to reseting register in configuration register to DMA control units；Then, reception is matched somebody with somebody
Put register transmission volume of transmitted data size, data transfer direction, data transfer purpose first address and
Bus control signal.Wherein host computer is sent data to according to the control of data transfer direction signal still to receive
The data and bus control signal controlling bus coffret that host computer sends are opened.Then posted according to configuration
The startup register pair DMA control units of storage are started；Then according to volume of transmitted data size and data
Data are carried out segment transmissions by transmission purpose first address.When data completion is transmitted, according to configuration register
Bus control signal controlling bus coffret is closed, and bus is discharged.
In sum, dma controller can effectively solve asking for 4KB borders in data transfer in the present invention
Topic.The present invention realizes the leap that logical design based on FPGA solves 4KB borders, only need CPU to
Dma controller configures primary parameter, it is possible to complete the transmission of data.By the logic of FPGA, solve
In the data transmission not across the problem on 4KB borders, and many configuration DMA ginsengs of CPU are not needed
Number, saves the CPU time, improves running efficiency of system.
One of ordinary skill in the art will appreciate that all or part of flow in realizing above-described embodiment method,
Computer program be can be by instruct the hardware of correlation to complete, program can be stored in embodied on computer readable
In storage medium, the program is upon execution, it may include such as the flow of the embodiment of above-mentioned each method.
Although describing the application by embodiment, it will be apparent to one skilled in the art that the application has many changes
Shape and change are without departing from the spirit and scope of the present invention.So, if these modifications of the invention and modification
Belong within the scope of the claims in the present invention and its equivalent technologies, then the present invention is also intended to be changed comprising these
Including modification.
Claims (6)
1. a kind of dma controller based on PXI e interface, it is characterised in that including：
Configuration register, for configuration data transmission quantity and data transfer purpose first address；
DMA control units, for judging whether the volume of transmitted data meets 128Byte；
When the volume of transmitted data is less than or equal to 128Byte, directly entered with host computer by PXIe mouthfuls
Row data transfer；
When the volume of transmitted data is more than 128Byte, then according to the volume of transmitted data and the data transfer mesh
First address data sectional is transmitted：
The data transfer purpose first address and volume of transmitted data of the data segment before calculating 4K borders less than 4K,
And judge remaining data transmission quantity whether more than 4K；
When the remaining data transmission quantity is more than 4K, then the data transfer mesh of the data segment for meeting 4K is calculated
First address and volume of transmitted data, and calculate the data segment behind 4K borders data transfer purpose first address and
Volume of transmitted data；
When the remaining data volume of transmitted data is less than or equal to 4K, then 4K post-boundary datas section is calculated
Data transfer purpose first address and volume of transmitted data；
Data transfer purpose first address and volume of transmitted data according to each data segment transmit all data.
2. dma controller as claimed in claim 1, it is characterised in that the DMA control units
For before data transfer, the reseting register in the configuration register to be resetted.
3. dma controller as claimed in claim 1, it is characterised in that the DMA control units
For before data transfer, the startup register according to the configuration register to be started.
4. the method for claim 1, it is characterised in that the DMA control units are used for basis
On data transfer direction register control in the configuration register sends data to host computer or receives
The data that position machine sends.
5. dma controller as claimed in claim 1, it is characterised in that the DMA control units
For when data transfer is completed, the bus control signal register control in the configuration register to be total
Line coffret is opened or closed.
6. dma controller as claimed in claim 1, it is characterised in that the dma controller collection
Into in FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000955.8A CN106919522A (en) | 2015-12-28 | 2015-12-28 | A kind of dma controller based on PXI e interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000955.8A CN106919522A (en) | 2015-12-28 | 2015-12-28 | A kind of dma controller based on PXI e interface |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106919522A true CN106919522A (en) | 2017-07-04 |
Family
ID=59455842
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511000955.8A Pending CN106919522A (en) | 2015-12-28 | 2015-12-28 | A kind of dma controller based on PXI e interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106919522A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110688333A (en) * | 2019-09-29 | 2020-01-14 | 郑州信大捷安信息技术股份有限公司 | PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method |
| CN110781120A (en) * | 2019-10-23 | 2020-02-11 | 山东华芯半导体有限公司 | Method for realizing cross-4 KB transmission of AXI bus host equipment |
| WO2020177252A1 (en) * | 2019-03-06 | 2020-09-10 | 上海熠知电子科技有限公司 | Pcie protocol-based dma controller, and dma data transmission method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002366507A (en) * | 2001-06-12 | 2002-12-20 | Fujitsu Ltd | Multichannel dma(direct memory access) controller, and processor system |
| JP2006018642A (en) * | 2004-07-02 | 2006-01-19 | Victor Co Of Japan Ltd | Dma transfer controller |
| CN101290604A (en) * | 2007-04-20 | 2008-10-22 | 索尼株式会社 | Information processing apparatus and method, and program |
| CN102567944A (en) * | 2012-03-09 | 2012-07-11 | 中国人民解放军信息工程大学 | Computed tomography (CT) image reconstruction hardware accelerating method based on field programmable gate array (FPGA) |
| CN102609383A (en) * | 2010-12-22 | 2012-07-25 | 索尼公司 | Information processing device, information processing system, information processing method, and program |
-
2015
- 2015-12-28 CN CN201511000955.8A patent/CN106919522A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002366507A (en) * | 2001-06-12 | 2002-12-20 | Fujitsu Ltd | Multichannel dma(direct memory access) controller, and processor system |
| JP2006018642A (en) * | 2004-07-02 | 2006-01-19 | Victor Co Of Japan Ltd | Dma transfer controller |
| CN101290604A (en) * | 2007-04-20 | 2008-10-22 | 索尼株式会社 | Information processing apparatus and method, and program |
| CN102609383A (en) * | 2010-12-22 | 2012-07-25 | 索尼公司 | Information processing device, information processing system, information processing method, and program |
| CN102567944A (en) * | 2012-03-09 | 2012-07-11 | 中国人民解放军信息工程大学 | Computed tomography (CT) image reconstruction hardware accelerating method based on field programmable gate array (FPGA) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020177252A1 (en) * | 2019-03-06 | 2020-09-10 | 上海熠知电子科技有限公司 | Pcie protocol-based dma controller, and dma data transmission method |
| CN110688333A (en) * | 2019-09-29 | 2020-01-14 | 郑州信大捷安信息技术股份有限公司 | PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method |
| CN110781120A (en) * | 2019-10-23 | 2020-02-11 | 山东华芯半导体有限公司 | Method for realizing cross-4 KB transmission of AXI bus host equipment |
| CN110781120B (en) * | 2019-10-23 | 2023-02-28 | 山东华芯半导体有限公司 | Method for realizing cross-4 KB transmission of AXI bus host equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2763045B1 (en) | Method and apparatus for allocating memory space with write-combine attribute | |
| US7660922B2 (en) | Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports | |
| CN103559152A (en) | Device and method for CPU (central processing unit) to access local bus on basis of PCIE (peripheral component interface express) protocol | |
| DE102019108376A1 (en) | Sequence for negotiation and activation of Flexbus protocols | |
| CN105335309B (en) | A kind of data transmission method and computer | |
| CN110781117A (en) | SPI expansion bus interface and system on chip based on FPGA | |
| CN106919522A (en) | A kind of dma controller based on PXI e interface | |
| US9400760B2 (en) | Information processor with tightly coupled smart memory unit | |
| DE112016002909T5 (en) | Flexible interconnect architecture | |
| CN104461400B (en) | The method and apparatus for handling access request conflict | |
| US20130173834A1 (en) | Methods and apparatus for injecting pci express traffic into host cache memory using a bit mask in the transaction layer steering tag | |
| CN108388527A (en) | Direct memory access (DMA) engine and its method | |
| CN104679681B (en) | Ahb bus accesses the high speed Biodge device and its method of work of SRAM on piece | |
| CN109324991A (en) | A kind of hot plug device of PCIE device, method, medium and system | |
| CN110968352B (en) | Reset system and server system of PCIE equipment | |
| DE112020006858T5 (en) | DYNAMIC INTERRUPT DEPLOYMENT | |
| CN112783818A (en) | Online upgrading method and system for multi-core embedded system | |
| CN107526534A (en) | The method and apparatus for managing the input and output (I/O) of storage device | |
| CN105765545A (en) | Sharing method and device for PCIe I/O device and interconnection system | |
| DE102021121490A1 (en) | APPROXIMATE DATA BUS INVERSION TECHNOLOGY FOR LATENT-SENSITIVE APPLICATIONS | |
| CN104123173A (en) | Method and device for achieving communication between virtual machines | |
| CN104063345A (en) | SATA (serial advanced technology attachment) bridge device | |
| US9032252B2 (en) | Debug barrier transactions | |
| DE112012005663B4 (en) | Apparatus, method and system for assigning processes or threads to agents | |
| CN105117353B (en) | FPGA with conventional data interactive module and the information processing system using the FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170704 |
|
| RJ01 | Rejection of invention patent application after publication |