JP2006018642A - Dma transfer controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DMA transfer controller for normally and efficiently performing burst transfer without being affected by a page boundary even for data transfer exceeding the page boundary. <P>SOLUTION: The DMA transfer controller 200 comprises: transfer parameter setting means (201, 202, 203) for setting a transfer destination, a transfer origin and a transfer size; a buffer (208); a buffer size comparison and decision part (204) for comparing the transfer size of data with the size of the buffer and deciding a processing transfer size which can be transferred by one read processing; a page boundary decision part (205) for deciding whether or not the transfer size exceeds the page boundary and setting a division transfer size by dividing the processing transfer size before the page boundary in the case of deciding that it exceeds the page boundary; and a non-processed transfer decision part (206) for deciding the presence of non-transmitted data after the page boundary and setting the division transfer size for the transfer of the next time in the case that the non-transmitted data are present, and the like. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a DMA transfer control device that can perform burst transfer normally and efficiently when a transfer source or a transfer destination is a DRAM memory.

DMA (direct memory access) is one method for controlling data transfer from a data transfer source to a data transfer destination. In the DMA transfer, the data transfer source address, the data transfer destination address, and the data transfer size are set in a register or the like, and then the DMA transfer control device starts the transfer operation when the CPU or the like controls the transfer start. Since there is no need for transfer control by the CPU at the time of transfer, the data transfer speed can be improved and the burden on the CPU can be reduced. When the transfer of the data size set in the register or the like is completed, the DMA transfer control device asserts a DMA transfer end interrupt. When the DMA transfer end interrupt is asserted, the CPU reads the data size result of the actual transfer completion, the register for reporting the status such as DMA transfer stop or transfer, and the like, and monitors the DMA transfer operation. In the case of DMA transfer, burst transfer is often used in which a plurality of byte data is transferred continuously in a single address designation (see Patent Document 1).
JP 2000-132497 A

  However, in the above-described DMA transfer control device, when the transfer source or transfer destination is a DRAM memory burst transfer, if a large transfer size is handled, the transfer always exceeds the page boundary, and even after the transfer across the page boundary, the transfer is already performed. The same access is executed for the address where the access has been completed. For this reason, it is impossible to perform normal data transfer, which hinders the original purpose of burst transfer that enables high-speed data transfer at high speed.

  In order to avoid this problem, it is necessary for the CPU or the like to manage the transfer source address, the transfer destination address, and the transfer size so as not to perform burst transfer across the page boundary. Therefore, the original purpose of the DMA transfer, which can reduce the load on the CPU by transferring the data, is hindered.

  In the present invention, burst transfer is performed without being affected by the page boundary even when the transfer source or the transfer destination is a DRAM memory, and even when the transfer size is large, such as exceeding the page boundary. An object of the present invention is to provide a DMA transfer control apparatus that can perform normal and efficient.

In view of the above problems, the present invention is characterized in that a DMA having a configuration for DMA-transferring continuous data stored in a transfer source to a transfer destination based on control of an external control unit for each [a] page. In the transfer control device,
Transfer parameter setting means for setting the transfer source start address of the continuous data stored in the transfer source, the transfer destination start address of the transfer destination, and the data size of the continuous data from the external control means and setting the parameters for transfer 201, 202, 203), [b] a buffer (208) for temporarily storing continuous data, [c] transfer parameter setting means, and the size of the buffer determine the processing transfer size that can be transferred in one reading process A buffer size comparison / determination unit (204) that determines whether or not the data size to be read from the transfer source to the buffer exceeds the page boundary of the transfer source, and is determined to exceed the page boundary of the transfer source Includes a page boundary determination unit (205) that sets a division transfer transfer size in units of transfer source page boundaries. [E] DMA transfer control including an unprocessed transfer determination unit (206) that determines whether there is untransmitted data after the page boundary of the transfer source and if there is untransmitted data, sets a divided transfer size for the next transfer The gist is that it is a device.

  According to the DMA transfer control device of the present invention, divided transfer control can be performed even for a transfer with a large transfer size exceeding a page boundary during burst transfer when the transfer source or transfer destination is a DRAM memory. As a result, burst transfer can be performed normally and efficiently without being affected by the page boundary.

  Further, the DMA transfer control device of the present invention determines whether or not the page boundary is exceeded and controls whether or not to divide burst transfer according to the determination result. Therefore, the CPU controls the transfer source address, transfer destination address and transfer size. It is not necessary to control to prevent burst transfer across page boundaries. Therefore, even in the case of burst transfer across page boundaries, the burden on the CPU does not increase, and the CPU can instruct burst transfer without considering page boundaries.

  The DMA transfer control device according to the embodiment of the present invention will be described below. In addition, the apparatus, method, etc. which are used in embodiment of this invention are examples, and of course, this invention is not limited to these.

(Embodiment)
(DMA transfer controller)
As shown in FIG. 1, a DMA transfer control apparatus 200 according to an embodiment of the present invention includes a transfer source address register 201, a transfer destination address register 202, a transfer size register 203, which are transfer parameter setting means, and a buffer size comparison determination. Unit 204, page boundary determination unit 205, unprocessed transfer determination unit 206, buffer 208, bus cycle generator 209, DMA transfer controller 210, and the like.

  The transfer source address register 201 holds a transfer source address. The transfer destination address register 202 holds a transfer destination address. The transfer size register 203 holds the transfer size.

  The buffer size comparison / determination unit 204 compares the “transfer size”, which is the total data transfer amount obtained from the transfer size register 203, with the “buffer size”, which is the total data storage amount of the buffer 208, so that the basic unit of transfer ( (Hereinafter referred to as “1 cool”) is set to “process transfer size” which is the amount of data transferred in the process of reading. The amount of data that can be transferred in one cool reading process depends on the buffer size. That is, the maximum processing transfer size is the buffer size.

  The page boundary determination unit 205 determines whether the read transfer exceeds the page boundary based on the transfer source address obtained from the transfer source address register 201, the processing transfer size obtained from the buffer size comparison judgment unit 204, and the page boundary size obtained from the transfer source memory 211. Determine whether or not. If the page boundary is exceeded, a “division transfer size” is determined by dividing the process transfer size by the page boundary. Whether the write transfer exceeds the page boundary is determined from the transfer destination address obtained from the transfer destination address register 202, the data size written to the buffer 208 at the time of read transfer, and the page boundary size of the transfer destination memory 212. When the page boundary is exceeded, the divided transfer size is determined by dividing the processing transfer size by the page boundary.

  The unprocessed transfer determination unit 206 determines whether there is still untransmitted divided transfer data in the case of divided transfer across page boundaries, and if there is still untransmitted divided transfer data, Determine the split transfer size.

  The buffer 208 is a storage device for temporarily storing data in order to compensate for a difference in processing speed or transfer speed when data is exchanged between the transfer source memory 211 and the transfer destination memory 212.

  The bus cycle generator 209 converts the transfer size of the transfer size register 203 from the transfer source memory 211 specified by the transfer source address register 201 to the transfer destination memory 212 specified by the transfer destination address register 202 by the bus width (processing). Transfer is performed according to the amount of data that can be transferred in one data transfer within one course of transfer size transfer.

  The DMA transfer controller 210 instructs the DMA transfer control device 200 to execute DMA transfer in response to the input of a transfer request signal based on the transfer request.

  The DMA transfer control device 200 is connected to the CPU 100, the transfer source memory 211, and the transfer destination memory 212 via an external bus. The register 110, the transfer source memory 211, the transfer destination memory 212, and the buffer 208 are each connected by a data bus having a plurality of bytes.

  The CPU 100 is an external control means, and sets predetermined values in the transfer source address register 201, the transfer destination address register 202, and the transfer size register 203, and instructs the start of the DMA transfer process when receiving a DMA transfer request. Once the DMA transfer is started, the CPU 100 does not issue a direct command for the DMA transfer.

(Operation of DMA transfer control device)
Hereinafter, a data transfer operation in which the DMA transfer control apparatus 200 according to the embodiment of the present invention reads data from the transfer source memory 211 of FIG. 1 and writes it to the transfer destination memory 212 will be described with reference to the flowchart of FIG.

  The data transfer operation described below is for burst transfer with a data bus width of 16 bytes, and the transfer source address, transfer destination address, and transfer byte size are set as shown in FIG. It is assumed that the original address register 201, the transfer destination address register 202, and the transfer size register 203 are already set.

(a) First, in step S101, the DMA transfer controller 210 determines whether a DMA transfer request is received via an external interface such as a SCSI interface. If no determination request has been received, the DMA transfer controller 210 continues this determination.

(B) If there is a request for DMA transfer, in step S102, the CPU 100 instructs the DMA transfer control device 200 to start DMA transfer, and the DMA transfer control device 200 sets the transfer source address in the transfer source address register 201 and The transfer size in the transfer size register 203 is read.

(C) In step S103, the buffer size comparison / determination unit 204 determines the transfer size by comparing the transfer source address and transfer size, the size of the buffer 208, and the page boundary size of the transfer source memory 211. If the transfer size is larger than the buffer size in step S104, “process transfer size = buffer size” is set. If the transfer size is equal to or smaller than the buffer size in step S105, “process transfer size = transfer size” is set. The maximum transfer size is the size of the buffer 208 and has the following relationship.

1) When transfer size <buffer size Transfer size = transfer size (1 transfer)
2) When transfer size = buffer size Transfer size = buffer size (1 transfer)
3) When transfer size> buffer size Transfer 1st: transfer size = buffer size Transfer 2nd: transfer size = (transfer size-buffer size) Thereafter, transfer is performed until the remaining size of transfer size data becomes 0 The processing transfer size is determined each time.

  Specifically, when the bus width is 16 bytes and the buffer size is 256 bytes, for example, when the transfer size is 40 bytes, the processing transfer size is 40 bytes, and 40 = 16 + 16 + 8, and one transfer is performed three times. Processing is required. If the transfer byte size is 260 bytes, the process transfer byte size of the first cool is 256 bytes of the buffer size, and 256 = 16 × 16, one transfer process is performed 16 times, and the second transfer process transfer byte size is 260−256 = 4 bytes, and transfer processing is required once every 2 cools with 4 × 1.

(D) In step S106, the page boundary determination unit 205 compares the transfer source address, the set processing transfer size, and the page boundary size of the transfer source memory 211 to determine whether the transfer size exceeds the page boundary. judge.

  If the page boundary is exceeded, the read transfer is divided in step S107, and therefore, the divided transfer size of one read in one course shown in FIG. Determine the size up to the boundary).

  If the page boundary is not exceeded, it is determined in step S108 that “divided transfer size = process transfer size”, that is, division of the process transfer size is unnecessary, and the process transfer size becomes the divided transfer size as it is. In the following, for the sake of convenience, even if the divided transfer size and the processing transfer size are the same amount, they are referred to as a divided transfer size.

(E) In step S109, since the divided transfer size is determined, data is read from the transfer source address in the transfer source address register 201. In step S110, the bus cycle generator 209 performs the data transfer for the processing transfer size from the transfer source memory 211 to the buffer 208 in one cool. The transfer destination memory 212 stores this process transfer data. In step S111, it is determined whether or not the divided transfer size is 0, that is, whether all the divided transfer data has been transferred. If it is 0, the process proceeds to step S112. If not, the process returns to step S109 and data is read again. Process.

(F) Next, in step S112, the unprocessed transfer determination unit 206 compares the process transfer size determined in step S104 or S105 with the split transfer size determined in step S107. The presence or absence of is determined.

  As shown in FIG. 3A, when “process transfer size> divided transfer size”, the transfer exceeds the page boundary of the transfer source memory 211. Therefore, unprocessed divided transfer data after the page boundary (second time) is stored. Exists. Accordingly, in step S113, the transfer source address and the transfer size to be read are updated, the process returns to step S109, and the remaining read transfer is performed in the same manner.

  On the other hand, if it is determined that “process transfer size = divided transfer size” and there is no unprocessed divided read transfer, the process proceeds to the write transfer operation from step S114.

(G) In step S114, the transfer destination address is read from the transfer destination address register 202. In step S115, the page boundary determination unit 205 determines whether or not the page boundary is exceeded by comparing the transfer destination address with the data size already stored in the buffer by read transfer and the page boundary size of the transfer destination memory 212. Determine.

  If the page boundary is exceeded, the write transfer is divided and performed in step S116. First, as shown in FIG. 4, the first divided transfer size (size from the transfer destination address to the page boundary of the transfer destination memory 212) is set. If the page boundary is not exceeded, the processing transfer size is set without dividing the data in step S117.

(H) In step S118, the bus cycle generator 209 acquires data from the buffer 208, and transfers it to the transfer destination memory 212 in step S119. The transfer destination memory 212 stores this. This operation is performed until the transfer of all the divided transfer size data is completed (step S120).

(I) In step S121, the unprocessed transfer determination unit 206 determines whether the next divided transfer is necessary or unnecessary by comparing the data size remaining in the buffer 208 with the divided transfer size determined in step S116 or S117. judge. When “process transfer size> first divided transfer size”, the transfer exceeds the page boundary of the transfer destination memory 212, and therefore there is an unprocessed write transfer after the page boundary. Accordingly, in step S122, the transfer destination address and the write transfer size are updated, and the process returns to steps S118 to S121 to similarly perform the remaining write transfer. On the other hand, when it is determined that “process transfer size = first divided transfer size” and there is no more divided transfer size data, the process proceeds to step S123.

(J) In step S123, when the first write transfer is completed, in step S120, the entire transfer size is compared with the process transfer size for which write transfer has already been completed. If “transfer size> process transfer size”, since there is untransferred data in the transfer source memory 211, the transfer source address, transfer destination address, and transfer size are updated in step S124, and the process returns to step S102. Read and write processes are repeated until the transfer size becomes zero.

  When the transfer size becomes 0, DMA burst transfer by the DMA transfer control device 200 is terminated.

(Example: Read transfer operation)
Hereinafter, an embodiment of the read transfer operation will be specifically described with reference to FIG. In the following, it is assumed that the transfer source address is 0x0140, the transfer byte size is 0x1C0, the page boundary position is 0x200, and the buffer size is 0x100.

<Process 1> Read the transfer source address (0x0140) and the transfer size (0x1C0).

<Process 2> When the transfer size (0x1C0) and the buffer size (0x100) are compared, since the transfer size is larger, two read transfers are required. The division transfer size of the first cool is 0x100, and the division transfer size of the second cool is 0xC0.

<Process 3> As a result of determining whether or not the page boundary is exceeded by comparing the transfer source address (0x0140) with the process transfer size (0x100) and page boundary (0x200) of the first cool, it is determined that the page boundary is exceeded. . Then, the read transfer is divided into two, and the size (0xC0) from the transfer source address to the page boundary is set as the first divided transfer size.

<Process 4> As shown in FIG. 3B, the first divided transfer size data (0xC0) is written to the buffer 208 from the transfer source address (0x0140).

<Process 5> It is determined whether or not there is read transfer unprocessed, and “process transfer size> first divided transfer size”, and there is unprocessed divided transfer size data. to go into.

<Process 6> To perform the second transfer, the transfer source address is updated to 0x0200 at the page boundary and the read transfer size is updated to 0x40 as shown in FIG.

<Process 7> Data (0x40) of the second divided transfer size from the transfer source address (0x0200) is written to the buffer 208 as shown in FIG.

  When the first-cool read transfer operation is completed, a first-cool write transfer operation described later is performed. When the write transfer operation of the first cool is completed, a read transfer operation of the second cool transfer processing size (0xC0) is performed as shown in FIG. 3A, and the buffer 208 is read as shown in FIG. Next, the data is written following the first course of data.

  As described above, even in the read transfer when the page boundary is exceeded, the DMA transfer control device 200 manages whether or not the page boundary of the transfer source memory 211 is exceeded, so that any transfer size data can be normally obtained from the transfer source address. It can be read and stored in the buffer 208.

(Example: Write transfer operation)
Next, the write transfer operation will be specifically described. As shown in FIG. 4, a case will be described in which the data of the data size (0x100) stored in the buffer 208 is written and transferred to the transfer destination address 0x0580 by the data transfer of the first processing transfer size described above. The page boundary position is 0x600.

<Process 1> Read the transfer destination address (0x0580) from the transfer destination address register 202.

<Process 2> It is determined whether or not the page boundary is exceeded by comparing the data size (0x100) and the page boundary (0x600) already stored in the buffer 208 by the read transfer. In FIG. 4, since the page boundary is exceeded, the write transfer is divided into two. The first divided transfer size data is the size up to the page boundary (0x80).

<Process 4> The data (0x80) for the first divided transfer size is written from the buffer 208 to the transfer destination address (0x0580).

<Process 5> The determination as to whether or not there is an unprocessed divided transfer by the unprocessed transfer determination unit 206 is "Process transfer size remaining in buffer 208> First divided transfer size" in the case of FIG. Since there is an unprocessed divided write transfer, the second divided transfer is entered.

<Process 6> The transfer destination address of the second divided transfer size is updated to 0x0600, and the transfer size is updated to 0x80.

<Process 7> Write the second divided transfer size data (0x80) from the buffer 208 to the transfer destination address (0x0600). As a result, all the data stored in the buffer 208 is written and transferred to the transfer destination address, and the first write transfer is completed.

  Next, the second cool read transfer operation described above is performed. When the second cool read transfer operation is completed, a write transfer operation of the second transfer processing transfer size (0xC0) is performed as shown in FIG. 4, and writing of all transfer size data is completed.

  As described above, even in the write transfer when the page boundary is exceeded, the DMA transfer control device 200 manages whether or not the page boundary of the transfer destination memory 212 is exceeded, so that the transfer destination address can be normally written.

It is a block diagram of an internal configuration of a DMA transfer control device according to an embodiment of the present invention. It is a flowchart which shows operation | movement of DMA transfer control. It is explanatory drawing of the data structure at the time of the read transfer of this invention. It is explanatory drawing of the data structure at the time of the write transfer of this invention.

Explanation of symbols

100 ... CPU
DESCRIPTION OF SYMBOLS 110 ... Register 200 ... DMA transfer control device 201 ... Transfer source address register 202 ... Transfer destination address register 203 ... Transfer size register 204 ... Buffer size comparison determination unit 205 ... Page boundary determination unit 206 ... Unprocessed transfer determination unit 208 ... Buffer 209 ... bus cycle generator 210 ... DMA transfer controller 211 ... transfer source memory 212 ... transfer destination memory

Claims (1)

For each page, in a DMA transfer control device having a configuration for DMA-transferring continuous data stored in a transfer source to a transfer destination based on control of an external control unit,
Transfer that sets transfer parameters by acquiring the transfer source start address and the transfer destination start address of the transfer destination stored in the transfer source, and the data size of the continuous data from the external control unit, respectively. Parameter setting means;
A buffer for temporarily storing the continuous data;
A buffer size comparison / determination unit for determining a processing transfer size that can be transferred in one reading process from the transfer parameter setting means and the size of the buffer;
It is determined whether or not the data size read from the transfer source to the buffer exceeds the page boundary of the transfer source, and if it is determined that the data size exceeds the page boundary of the transfer source, the processing transfer size is set to the A page boundary determination unit that sets a divisional divided transfer size in units of page boundaries of the transfer source;
A DMA comprising: an unprocessed transfer determination unit that determines whether or not there is untransmitted data after a page boundary of the transfer source, and sets the divided transfer size for the next transfer when the untransmitted data exists. Transfer control device.

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