CN114547663A - Method for realizing data encryption, decryption and reading by high-speed chip based on USB interface - Google Patents

Method for realizing data encryption, decryption and reading by high-speed chip based on USB interface Download PDF

Info

Publication number
CN114547663A
CN114547663A CN202210455007.7A CN202210455007A CN114547663A CN 114547663 A CN114547663 A CN 114547663A CN 202210455007 A CN202210455007 A CN 202210455007A CN 114547663 A CN114547663 A CN 114547663A
Authority
CN
China
Prior art keywords
data
usb
dma
algorithm
decryption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210455007.7A
Other languages
Chinese (zh)
Other versions
CN114547663B (en
Inventor
何军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Wise Security Technology Co Ltd
Original Assignee
Guangzhou Wise Security Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Wise Security Technology Co Ltd filed Critical Guangzhou Wise Security Technology Co Ltd
Priority to CN202210455007.7A priority Critical patent/CN114547663B/en
Publication of CN114547663A publication Critical patent/CN114547663A/en
Application granted granted Critical
Publication of CN114547663B publication Critical patent/CN114547663B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/606—Protecting data by securing the transmission between two devices or processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4286—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a handshaking protocol, e.g. RS232C link
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/602—Providing cryptographic facilities or services
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/3013—Organisation of register space, e.g. banked or distributed register file according to data content, e.g. floating-point registers, address registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Computer Security & Cryptography (AREA)
  • Information Transfer Systems (AREA)

Abstract

The invention provides a method for realizing data encryption, decryption and reading of a high-speed chip based on a USB interface.A chip operating system configures the USB interface into a large-capacity Storage device, adopts a USB Mass Storage protocol for transmission, and uses Bulk-Only transmission and a SCSI command set to communicate with a host CPU. The COS is designed by adopting a USB drive-free design, the USB drive-free COS has high USB read-write performance, the enumeration process can be quickly completed, and the APDU instruction supported by the COS accords with the GM/T0017 specification. The chip has the capability of encrypting and decrypting data at high speed, and can be applied to the fields of video stream encryption and decryption systems, embedded information security and the like.

Description

Method for realizing data encryption, decryption and reading by high-speed chip based on USB interface
Technical Field
The invention relates to the technical field of encryption chips, in particular to a method for realizing data encryption, decryption and reading by a high-speed chip based on a USB interface.
Background
The encryption performance of the USB as an important interface for data transmission between devices should be high, and there are various methods for encrypting USB data in the prior art: some secure chips use software to encrypt or plug-in hardware to encrypt and decrypt, the former has flexible encryption algorithm but consumes more time and has higher firmware complexity, and the latter increases hardware cost. The traditional USB encryption card symmetric algorithm code processing flow is to finish receiving all data to be operated and then start symmetric algorithm operation, so the processing performance is low. Some firmware used by the USB encryption chip dynamically switches the strategy of USB transceiving FIFO, the firmware realizes pipelined processing as much as possible, and the encryption and decryption performance is not high in practice. In order to improve the data transmission rate of the USB encryption card, some chip designs adopt a direct memory access module (USB-DMA) special for the USB on hardware, and the special USB-DMA can improve the data transmission rate of a USB interface and directly complete the data transmission between the Endpoint FIFO and the memory; some USB encryption chips use multilayer AHB bus and AHB-Lite bus to meet the requirements of high bandwidth and low time delay of the multiprocessor system; these designs have high complexity of hardware design, large chip area, high chip cost, simple design of peripheral circuits, and small obstacles to application and popularization.
Disclosure of Invention
The invention aims to provide a method for realizing data encryption, decryption and reading based on a high-speed chip of a USB interface, thereby solving the problems in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a high-speed data encryption and decryption chip based on a USB interface comprises a 32-bit RISC security CPU core, an AHB bus, a direct access module DMA and a memory management unit EMMU which are connected to the AHB bus, a cryptographic algorithm module and a USB communication module, wherein the USB communication module is internally provided with a USB high-speed PHY through an UTMI + Level2 interface to realize a high-speed communication mode; the 32-bit RISC security CPU core integrates a COS operation system, and accesses a control register through an AHB bus interface, so that each IP is scheduled to complete specific work; providing interrupt and DMA (direct memory access) services, realizing quick response of an IP (Internet protocol) request and quick data handling, reading data received by a USB interface from a USB communication module, and simultaneously taking charge of analysis work of an application protocol data unit command; the memory management unit EMMU is used for protecting and managing the ROM, the RAM and the Flash memory; the direct access module DMA can accelerate the data handling process of different address intervals in the SOC, and specifically comprises the following steps: the DMA controller transmits the first data in the data buffer area received by the USB communication module to the cryptographic algorithm module, and the 20K byte encryption and decryption data buffer area is transmitted to the SRAM controller in the EMMU chip after being decrypted or encrypted by the cryptographic algorithm module and is temporarily stored; because the USB controller uses a plurality of RxFIFOs, the USB communication module can receive the second data at the moment, and meanwhile, the DMA controller directly transmits the second data to the cryptographic algorithm module, and the second data is encrypted or decrypted by the data encryption and decryption module and then transmitted to a 20KB data buffer area of the SRAM controller in the interface chip for temporary storage.
Preferably, the chip further comprises a timer, a clock management module and a power management module.
Preferably, the cryptographic algorithm module implements at least one of the SM1/SM4/SM7/DES/AES/PKU/HASH algorithms.
Preferably, the USB communication module includes a USB serial interface controller and a USB data transceiver, the USB serial interface controller is provided with an 8k FIFO RAM, the USB serial interface controller and the AHB bus interface complete a high-speed parallel transmission process of data, and the USB data transceiver receives and sends a data packet to be encrypted and decrypted and instruction data by using a Bulk-Only transmission protocol.
The invention also aims to provide a high-speed data encryption and decryption method based on the high-speed data encryption and decryption chip based on the USB interface, which comprises the following steps:
s1, after the chip is powered on, the operating system COS configures the USB serial interface controller to use the USB Mass Storage protocol to perform a drive symbol enumeration process;
s2, the USB communication module issues APDU instruction, the APDU instruction enters the chip system through the USB data transceiver, the USB serial interface controller completes USB communication handshake and moves the APDU instruction to the USB RxFIFO memory;
s3, the chip operating system COS obtains APDU command from the USB RxFIFO memory, if the command is the encryption/decryption data command, the number of USB transmission data blocks is directly obtained, and the step enters S4; if the command is not the data encryption and decryption command, the USB flash disk is in a normal USB flash disk state;
s4, the operating system COS configures an OUT endpoint receiving register of the USB serial interface controller, so that the USB data transceiver starts to receive the data packet to be encrypted and decrypted, when the data of the first packet 512B is received, the data packet is analyzed and configured with a register of the algorithm coprocessor and a DMA module register according to the selected target algorithm in the received APDU command, and DMA algorithm shifting operation is started on the data to be encrypted and decrypted sent by the USB; at the moment, the interrupt of the USB communication module is shielded, and an AHB bus is managed by a DMA controller;
s5, taking over the control right of the cryptographic algorithm module from the CPU by the DMA controller, controlling the cryptographic algorithm module to complete the processing of all the data to be encrypted and decrypted in the USB RxFIFO memory, and when the last packet of data to be encrypted and decrypted is processed by the DMA controller, generating and entering a DMA completion interrupt service program by the DMA controller, wherein the specific steps include;
the DMA-Codec reads a first group of data to be encrypted and decrypted from a DMA source address register, writes the data into a data register corresponding to a target algorithm, starts algorithm operation and waits for the data operation to be completed; after the operation is finished, the DMA-Codec reads the calculation result data from the data register corresponding to the target algorithm and writes the calculation result data into the target address register of the DMA, and the DMA data length register reduces the length of a group of data so as to finish the algorithm operation of the group of data; at the moment, the USB serial interface controller simultaneously receives the next packet of plaintext data and writes the next packet of plaintext data into the USB RxFIFO, and the USB stops receiving the data packet to be encrypted and decrypted until no space exists in the USB RxFIFO; when the DMA algorithm function finishes 512B data encryption, the USB RxFIFO space of 512B is released, and the chip USB automatically receives the data of the next packet from the USB host and writes the data into the USB RxFIFO.
S6, when the DMA controller finishes the operation of the interrupt service program, the CSW of 13 bytes is filled into the USB TxFIFO of the chip, the USB serial interface controller returns the CSW to the USB host, and the APDU instruction overall process of the current encryption and decryption data is completed.
Preferably, the USB RxFIFO memory in step S2 is 8 kbytes, and the operating system COS configures an OUT endpoint receiving register of the USB serial interface controller in step S4, which specifically includes: the USB data transceiver receives the number of data packets to be issued and then enables the receiving function of an Out endpoint;
the register of the configuration algorithm coprocessor specifically comprises: initializing an encryption and decryption algorithm, and configuring a relevant register of a target algorithm;
configuring the DMA module register specifically includes: the DMA source address register is configured to be RxFIFO, the target address register is the starting address of the encryption and decryption SRAM buffer area, and the DMA operation data length register is the number of transmission data packets in CBW multiplied by 512B.
The invention finally aims to provide a method for reading a high-speed data encryption and decryption result, which is based on the high-speed data encryption and decryption chip based on the USB interface and comprises the following steps:
a1, COS obtains the data packet length SendSize from CBW 31B, writes the SendSize information into the target end point IN control register of USB serial interface controller and enables the sending function;
a2, configuring a USB target endpoint IN control register and a DMA controller target address, a source address and a transfer length, wherein the target address is TxFIFO, the source address is the starting address of an encryption/decryption 20K Codec RAM buffer area, the transfer length is the available space TxFIFOCurSize of the current TxFIFO, and starting the DMA controller;
a3, obtaining current available space TxFIFOCurSize1 of USB TxFIFO, if SendSize > TxFIFOCurSize, and the length of the sent data packet is equal to the current available space of TxFIFO, then the USB controller will generate TxFIFO half-empty interrupt, entering step A4, if SendSize < TxFIFOCurSize, the length of the sent data packet is equal to the length of the data packet to be read, and directly entering step A5;
a4, newly acquiring the available space TxFIFOCurSize2 of the current TxFIFO to be X K, reconfiguring the DMA transfer length to be X K again, starting the DMA, and modifying the current data to be read to be SendSize = SendSize-X; repeating the step until the SendSize value is 0, and entering the step A5;
a5, in the interrupt service procedure completed by the last DMA operation, filling 13 bytes of CSW into the USB TxFIFO of the chip, and at this time, completing the current Bulk protocol transmission, i.e. reading APDU of the encryption and decryption result.
Preferably, the size of the USB TxFIFO configuration is 4KB space, 8 USB data packets of 512B are written by DMA according to 512B packets of data, and when DMA writes one packet of 512B, the USB IP automatically generates a "port number transaction" message to the Tx In request queue;
when the number of data packets requested to be read by the USB host is more than 8, the USB TxFIFO half-empty interrupt is enabled, and when the USB IP TxFIFO sends 4 512B data packets, the TxFIFO half-empty USB interrupt is generated to inform the CPU; in the USB half-empty interrupt service program, the DMA is configured to continuously move the data packet to be sent to the USB TxFIFO.
Preferably, the DMA comprises a common DMA, a peripheral DMA and an algorithm DMA, and the common DMA is carried between a memory and a common IP; the peripheral DMA is carried between the USB and the memory; the algorithm DMA is carried between a memory and an algorithm memory;
the operation principle flow of the algorithm DMA is as follows:
the first step is as follows: initializing an algorithm, and configuring Key, IV and other related registers of a target algorithm;
the second step is that: initializing DMA, and configuring a DMA data source address RxFIFO, a DMA data target address and a DMA operation data length register;
the third step: configuring a DMA transmission control register according to the algorithm type, and starting the algorithm DMA to perform algorithm operation;
the fourth step: the algorithm DMA reads a group of data from the data source address of the DMA, writes the data into a data register corresponding to the algorithm, starts algorithm operation and waits for the completion of the data operation; and then the algorithm DMA reads the calculation result data from the data register corresponding to the algorithm, writes the calculation result data into the data target address of the DMA and increases the address, and the DMA data length register reduces the length of a group of data, thereby completing the algorithm encryption and decryption and reading operation of the group of data.
The invention has the beneficial effects that:
the invention provides a method for realizing data encryption, decryption and reading of a high-speed chip based on a USB interface.A chip operating system configures the USB interface into a large-capacity Storage device, adopts a USB Mass Storage protocol for transmission, and uses Bulk-Only transmission and a SCSI command set to communicate with a host CPU. The COS is designed by adopting a USB drive-free design, the USB drive-free COS has high USB read-write performance, the enumeration process can be quickly completed, and the APDU instruction supported by the COS accords with the GM/T0017 specification. The chip has the capability of encrypting and decrypting data at high speed, and can be applied to the fields of video stream encryption and decryption systems, embedded information security and the like.
The design chip uses a single-layer AHB bus structure and supports a plurality of encryption algorithms, including SM1/SM4/SM 7/DES/AES/PKU/HASH. For quickly encrypting and decrypting data packets, a code Remap mechanism key firmware code is used for executing in a memory, and is driven by interrupt transactions, an algorithm hardware circuit is used for realizing, a DMA (direct memory access) and algorithm coprocessor parallel pipeline design, a flexible USB FIFO (universal serial bus) mechanism design and other acceleration strategies are used for improving the encryption and decryption data performance of a USB interface.
The encryption and decryption method realized based on the chip reads data waiting for encryption and decryption from a USB controller Rx FIFO by using an AHB bus through a DMA module, writes the data into an algorithm hardware coprocessor register, and then stores the algorithm calculation encryption and decryption result data into a system memory. When the USB host computer needs to read the encryption and decryption result data, the DMA module is flexibly designed by matching with the TxFIFO of the USB controller, and the result data is transmitted to the USB host computer through parallel processing. Compared with the similar USB safety chip in the market, the chip has the characteristics of low cost and high performance, has higher USB interface encryption and decryption performance under the same CPU frequency, has the leading position of the USB encryption and decryption performance, and has wide market prospect.
Drawings
Fig. 1 is a schematic structural diagram of a high-speed data encryption and decryption chip based on a USB interface provided in embodiment 1;
fig. 2 is a schematic diagram of a high-speed data encryption and decryption chip based on a USB interface provided in embodiment 1;
FIG. 3 is a flow chart showing a high-speed data encryption/decryption method provided in embodiment 2;
FIG. 4 is a schematic diagram of a high-speed data encryption/decryption method provided in embodiment 2;
fig. 5 is a flowchart illustrating an encrypted/decrypted data reading method provided in embodiment 3;
FIG. 6 is a schematic flow chart of an ISR when a half-empty interrupt occurs in the USB according to embodiment 3;
FIG. 7 is a flow chart of ISR in the case of an interrupt in DMA in embodiment 3;
fig. 8 is a schematic diagram of the FIFO design in the USB communication module used in embodiment 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.
Example 1
The present embodiment provides a high-speed data encryption and decryption chip based on USB interface, the chip structure is shown in fig. 1, and the chip structure includes a 32-bit RISC secure CPU core, an AHB bus, and a direct access module DMA, a memory management unit EMMU, a cryptographic algorithm module and a USB communication module connected to the AHB bus, where the USB communication module is built in with a USB high-speed PHY through an UTMI + Level2 interface, so as to implement a high-speed communication mode; the USB communication module comprises a USB serial interface controller and a USB data transceiver, the USB serial interface controller is provided with an 8k FIFO RAM, the USB serial interface controller and an AHB bus interface complete the high-speed parallel transmission process of data, and the USB data transceiver receives and sends data packets to be encrypted and decrypted and instruction data by adopting a Bulk-Only transmission protocol.
The 32-bit RISC security CPU core integrates a COS operation system, and accesses a control register through an AHB bus interface, so that each IP is scheduled to complete specific work; providing interrupt and DMA (direct memory access) services, realizing quick response of an IP (Internet protocol) request and quick data handling, reading data received by a USB interface from a USB communication module, and simultaneously taking charge of analysis work of an application protocol data unit command; the memory management unit EMMU is used for protecting and managing the ROM, the RAM and the Flash memory; the direct access module DMA can accelerate the data handling process of different address intervals in the SOC, and specifically comprises the following steps: the DMA controller transmits the first data in the data buffer area received by the USB communication module to the cryptographic algorithm module, and the 20K byte encryption and decryption data buffer area is transmitted to the SRAM controller in the EMMU chip after being decrypted or encrypted by the cryptographic algorithm module and is temporarily stored; because the USB controller uses a plurality of RxFIFOs, the USB communication module can receive the second data, and the DMA controller can directly transmit the second data to the cryptographic algorithm module, and the second data is encrypted or decrypted by the data encryption and decryption module and then transmitted to a 20KB data buffer of the SRAM controller in the chip for temporary storage.
The chip also comprises a timer, a clock management module and a power management module.
The cryptographic algorithm module implements at least one of SM1/SM4/SM7/DES/AES/PKU/HASH algorithms.
Example 2
The embodiment provides a high-speed data encryption and decryption method, which adopts the high-speed data encryption and decryption chip based on the USB interface described in embodiment 1, and as shown in fig. 3, includes the following steps:
s1, after the chip is powered on, the USB operating system COS configures the USB serial interface controller to use the USB Mass Storage protocol to perform a drive symbol enumeration process;
s2, the USB communication module issues an APDU command, the APDU command enters the chip system through the USB data transceiver, the USB serial interface controller completes USB communication handshake and moves the APDU command to the USB RxFIFO memory;
s3, the chip operating system COS obtains APDU command from the USB RxFIFO memory, if the command is the encryption/decryption data command, the number of USB transmission data blocks is directly obtained, and the step enters S4; if the command is not the data encryption and decryption command, the USB flash disk is in a normal USB flash disk state;
s4, the operating system COS configures an OUT endpoint receiving register of the USB serial interface controller, so that the USB data transceiver starts to receive the data packet to be encrypted and decrypted, when the data of the first packet 512B is received, the data packet is analyzed and a register of an algorithm coprocessor (any one encryption algorithm processor in a cryptographic algorithm module) and a DMA module register are configured according to the selected target algorithm in the received APDU command, and DMA algorithm moving operation is started on the data to be encrypted and decrypted sent by the USB; at the moment, the interruption of the USB communication module is shielded, and the AHB bus is managed by the DMA controller and is only responsible for the transmission and encryption process of USB data;
s5, taking over the control right of the cryptographic algorithm module from the CPU by the DMA controller, controlling the cryptographic algorithm module to complete the processing of all the data to be encrypted and decrypted in the USB RxFIFO memory, when the last packet of data to be encrypted and decrypted is processed by the DMA controller, generating and entering a DMA completion interrupt service program by the DMA controller, wherein the process specifically comprises the following steps;
the DMA-Codec reads a group of data to be encrypted and decrypted from a DMA source address register, writes the data into a data register corresponding to a target algorithm, starts algorithm operation and waits for the completion of the data operation; after the operation is finished, the DMA-Codec reads the calculation result data from the data register corresponding to the target algorithm and writes the calculation result data into the target address register of the DMA, and at the moment, the DMA data length register reduces the length of a group of data, thereby finishing the algorithm operation of the group of data; at the moment, the USB serial interface controller simultaneously receives the next packet of plaintext data and writes the next packet of plaintext data into the USB RxFIFO, and the USB stops receiving the data packet to be encrypted and decrypted until no space exists in the USB RxFIFO; when the DMA algorithm function finishes 512B data encryption, the USB RxFIFO space of 512B can be released, and the chip USB automatically receives the data of the next packet from the USB host and writes the data into the USB RxFIFO.
S6, when the length of the DMA data length register is 0, generating DMA interrupt, when the DMA controller completes the interrupt service program, filling 13 bytes of CSW into the USB TxFIFO of the chip, the USB serial interface controller returns the CSW to the USB host, and the APDU instruction whole process of the current encryption and decryption data is completed.
In this embodiment, the USB RxFIFO memory in step S2 is 8 kbytes, and the operating system COS configures an OUT endpoint receiving register of the USB serial interface controller in step S4, which specifically includes: the USB data transceiver receives the number of data packets to be issued and then enables the receiving function of an Out endpoint;
the register of the configuration algorithm coprocessor specifically comprises: initializing an encryption and decryption algorithm, and configuring a relevant register of a target algorithm;
configuring the DMA module register specifically includes: the DMA source address register is configured to be RxFIFO, the target address register is the starting address of the encryption and decryption SRAM buffer area, and the DMA operation data length register is the number of transmission data packets in CBW multiplied by 512B.
Specific examples are:
in this embodiment, the RAM is divided into RAM0, RAM1, RAM2, and RAM3, which are taken as an example to illustrate the operation flow of the USB 8KB RxFIFO RAM working simultaneously:
in the process of data encryption or decryption, USB, DMA and algorithm coprocessor hardware IP are supported to work simultaneously, and the specific flow is as follows:
1) the USB receives Out packets from host and writes them to RAM0, RAM0 is USB controlled, and the other RAMs are idle at this time
/RAM3 RAM2 RAM1 RAM0
00 00 00 USB
After completion, the hardware flag RAM0_ s is 01 (indicating that the USB operation on the RAM0 is complete)
2) In the first encryption/decryption packet reception completion interrupt service routine, the DMA-Codec performs an encryption/decryption operation on the data in the RAM0, and the RAM0 is controlled by the DMA-Codec.
The USB continues to receive data from host and write to RAM1, RAM1 is USB controlled, and the other 2 RAMs are now free.
RAM3 RAM2 RAM1 RAM0
00 00 USB DMA-Codec
The encryption speed is slower than the data receiving speed, so that after the RAM1 receives the data, the data packet in the RAM0 is not encrypted or decrypted, so that the hardware set flag RAM1_ s is 01 under the control of the DMA-Codec after the USB operation is completed. RAM2 is idle at this time, USB continues to receive data from host and writes to RAM2, and RAM2 is USB controlled.
RAM3 RAM2 RAM1 RAM0
00 USB 01 DMA-Codec
3) At this time, after the DMA-Codec encryption and decryption are completed, the hardware flag setting RAM0_ s is 00, since the RAM1_ s is 01, which indicates that there is data to be encrypted and decrypted, the DMA-Codec encrypts the data in the RAM1, and the RAM1 is controlled by the DMA-Codec. At this time, after the USB operation is completed, the hardware flag RAM2_ s is set to 01. RAM3 is idle at this time, USB continues to receive data from host and writes to RAM3, and RAM3 is USB controlled. The RAM0 is in an idle state at this time since encryption has been completed, and therefore can start receiving data again.
RAM3 RAM2 RAM1 RAM0
USB 01 DMA-Codec 00
As can be seen from the above, the USB and DMA-Codec controllers operate in parallel, and loop until all the packets to be encrypted and decrypted in the APDU header are processed. In the process, the data is automatically processed by hardware IP, no interrupt exists in the middle, when the last packet of a data packet to be processed is completed, a DMA completion interrupt is generated to fill 13 bytes of CSW into the USB TxFIFO of the chip, and the USB serial interface controller returns the CSW to the USB host to complete the whole process of the APDU command of the current encryption and decryption data.
Example 3
The present embodiment provides a method for reading a high-speed data encryption and decryption result, based on the high-speed data encryption and decryption chip based on the USB interface described in embodiment 1, as shown in fig. 5, the method includes the following steps:
a1, COS obtains the data packet length SendSize from CBW 31B, writes the SendSize information into the target end point IN control register of USB serial interface controller and enables the sending function;
a2, configuring a USB target endpoint IN control register IN sending endpoint register and DMA controller target address, source address and move length, wherein the target address is TxFIFO, the source address is the starting address of the encryption and decryption 20K Codec RAM buffer area, the move length is the available space TxFIFOCurSize of the current TxFIFO, and starting the DMA controller;
a3, obtaining the current available space TxFIFOCurSize1 of USB TxFIFO, if SendSize > TxFIFOCurSize, and the length of the sent data packet is equal to the current available space TxFIFO, then the USB controller will generate TxFIFO half-empty interrupt at this moment, enter step A4;
if SendSize < TxFIFOCurSize, the length of the sent data packet is equal to the length of the data packet to be read, and the step A5 is directly entered, and the length of the sent data packet is equal to the length of the data packet to be read, the DMA is opened to finish the interruption;
a4, reacquiring the available space of the current TxFIFO to be X K, reconfiguring the DMA transfer length to be X K again, starting the DMA, and modifying the current data to be read to be SendSize = SendSize-X; repeating the step until the SendSize value is 0, and entering the step A5;
a5, in the interrupt service procedure completed by the last DMA operation, filling 13 bytes of CSW into the USB TxFIFO of the chip, and at this time, completing the current Bulk protocol transmission, i.e. reading APDU of the encryption and decryption result.
The specific implementation process comprises the following steps:
in this implementation process, the total size of the TxFIFO configuration is 4 kbytes, and according to the Bulk protocol, the TxFIFO configuration is 8 512B data packets, and when the USB host wants to read 8K encryption/decryption data packets, the transmission length of the issued CBW instruction will be 16, that is, the USB host is required to upload 16 512B data packets, then the processing flow is as follows:
the first step is as follows: configuring the USB In sending endpoint register as follows: transmitting (16 + 1) data packets, transmitting (16 × 512 + 13) bytes, then enabling the transmitting function of In endpoints, and setting the number of packets to be transmitted SendPkt =16, where SendPkt has the same meaning as SendSize, except for the number of data packets.
The second step is that: configuring that the DMA target address is TxFIFO, the source address is the starting address of the encryption and decryption 20K Codec RAM buffer area, the DMA transfer length is 4K bytes of the available space of the current TxFIFO, namely 8 packets of data, and starting DMA at the moment.
And modifying the current transmission packet number SendPkt = 16-8 = 8, and when the USB host transmits an In packet, the chip transfers the DMA to a 512B data packet In the USB TxFIFO and transmits the data packet to the USB host.
The third step: the DMA finishes the movement of 4K byte data packets, simultaneously the USB sends 512B length data packets to the USB host, when the USB controller sends 4 data packets which are 2K bytes, the USB controller can generate TxFIFO half-empty interrupt, and simultaneously the USB continues to send 512B length data packets to the USB host. If the data to be read is less than 4k, the data can be directly sent without generating a half-space interrupt process.
The fourth step: in the USB half-empty interrupt service routine, the available space of the current TxFIFO is retrieved, assuming XK bytes, since the TxFIFO is already occupied at this time, X should be less than 4, such as 2K bytes. At this time, the DMA transfer length needs to be configured again to be 2 Kbytes, the DMA is started again, and the number of currently transmitted packets SendPkt = SendPkt-4 is modified. This process is repeated until the SendPkt current value is 0, indicating that the data required by the USB host has been sent out, at the last time DMA completion interrupts are enabled.
The fifth step: and in the process that the last DMA operation finishes the interrupt service program, filling 13 bytes of CSW into the USB TxFIFO of the chip, and finishing the current Bulk protocol transmission at the moment, namely reading APDU of the encryption and decryption result.
From the above flow, it can be seen that because the USB TxFIFO half-empty interrupt transaction is added, the In transaction operation of the USB host can substantially reach the line speed, and the firmware processing time of the chip can be ignored.
The USB TxFIFO configuration In this embodiment has a size of 4KB space, and according to 512B packets of data, 8 USB packets of 512B can be written by DMA, and when DMA writes one packet of 512B, the USB IP automatically generates a "port number transaction" message to the Tx In request queue, as shown In fig. 8.
It should be noted that the DMA provided in the present invention includes a normal DMA, a peripheral DMA, and an algorithm DMA, and the normal DMA is carried between a memory and a normal IP; the peripheral DMA is carried between the USB and the memory; the algorithm DMA is carried between a memory and an algorithm memory;
the operation principle flow of the algorithm DMA is as follows:
the first step is as follows: initializing an algorithm, and configuring Key, IV and other related registers of a target algorithm;
the second step is that: initializing DMA, and configuring a DMA data source address RxFIFO, a DMA data target address and a DMA operation data length register;
the third step: configuring a DMA transmission control register according to the algorithm type, and starting the algorithm DMA to carry out algorithm operation;
the fourth step: the algorithm DMA reads a group of data from the data source address of the DMA, writes the data into a data register corresponding to the algorithm, starts algorithm operation and waits for the completion of the data operation; and then the algorithm DMA reads the calculation result data from the data register corresponding to the algorithm, writes the calculation result data into the data target address of the DMA and increases the address, and the DMA data length register reduces the length of a group of data, thereby completing the algorithm encryption and decryption and reading operation of the group of data.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.

Claims (9)

1. A high-speed data encryption and decryption chip based on a USB interface is characterized by comprising a 32-bit RISC security CPU core, an AHB bus, a direct access module DMA, a memory management unit EMMU, a cryptographic algorithm module and a USB communication module, wherein the direct access module DMA, the memory management unit EMMU, the cryptographic algorithm module and the USB communication module are connected to the AHB bus, and the USB communication module is internally provided with a USB high-speed PHY through a UTMI + Level2 interface to realize a high-speed communication mode; the 32-bit RISC security CPU core integrates a COS operation system, and accesses a control register through an AHB bus interface, so that each IP is scheduled to complete specific work; providing interrupt and DMA (direct memory access) services, realizing quick response of an IP (Internet protocol) request and quick data handling, reading data received by a USB interface from a USB communication module, and simultaneously taking charge of analysis work of an application protocol data unit command; the memory management unit EMMU is used for protecting and managing the ROM, the RAM and the Flash memory; the direct access module DMA can accelerate the data handling process of different address intervals in the SOC, and specifically comprises the following steps: the DMA controller transmits the first data in the data buffer area received by the USB communication module to the cryptographic algorithm module, and the 20K byte encryption and decryption data buffer area is transmitted to the SRAM controller in the EMMU chip after being decrypted or encrypted by the cryptographic algorithm module and is temporarily stored; because the USB controller uses a plurality of RxFIFOs, the USB communication module receives the second data, and the DMA controller directly transmits the second data to the cryptographic algorithm module, and the second data is encrypted or decrypted by the data encryption and decryption module and then transmitted to a 20KB data buffer of the SRAM controller in the interface chip for temporary storage.
2. The USB interface-based high-speed data encryption and decryption chip according to claim 1, wherein the chip further comprises a timer, a clock management module and a power management module.
3. The USB interface-based high-speed data encryption and decryption chip according to claim 1, wherein the cryptographic algorithm module implements at least one of SM1/SM4/SM7/DES/AES/PKU/HASH algorithms.
4. The high-speed data encryption and decryption chip based on the USB interface according to claim 1, wherein the USB communication module comprises a USB serial interface controller and a USB data transceiver, the USB serial interface controller is provided with an 8k FIFO RAM, the USB serial interface controller and the AHB bus interface complete the high-speed parallel transmission process of data, and the USB data transceiver adopts a Bulk-Only transmission protocol to receive and send data packets to be encrypted and decrypted and instruction data.
5. A high-speed data encryption and decryption method based on the USB interface-based high-speed data encryption and decryption chip of any one of claims 1 to 4, comprising the steps of:
s1, after the chip is powered on, the operating system COS configures the USB serial interface controller to use the USB Mass Storage protocol to perform a drive symbol enumeration process;
s2, the USB communication module issues APDU instruction, the APDU instruction enters the chip system through the USB data transceiver, the USB serial interface controller completes USB communication handshake and moves the APDU instruction to the USB RxFIFO memory;
s3, the chip operating system COS obtains APDU command from the USB RxFIFO memory, if the command is the encryption/decryption data command, the number of USB transmission data blocks is directly obtained, and the step enters S4; if the command is not the data encryption and decryption command, the USB flash disk is in a normal USB flash disk state;
s4, the operating system COS configures an OUT endpoint receiving register of the USB serial interface controller, so that the USB data transceiver starts to receive the data packet to be encrypted and decrypted, when the data of the first packet 512B is received, the data packet is analyzed and configured with a register of the algorithm coprocessor and a DMA module register according to the selected target algorithm in the received APDU command, and DMA algorithm shifting operation is started on the data to be encrypted and decrypted sent by the USB; at the moment, the interrupt of the USB communication module is shielded, and an AHB bus is managed by a DMA controller;
s5, taking over the control right of the cryptographic algorithm module from the CPU by the DMA controller, controlling the cryptographic algorithm module to complete the processing of all the data to be encrypted and decrypted in the USB RxFIFO memory, and when the last packet of data to be encrypted and decrypted is processed by the DMA controller, generating and entering a DMA completion interrupt service program by the DMA controller, wherein the specific steps include;
the DMA-Codec reads a first group of data to be encrypted and decrypted from a DMA source address register, writes the data into a data register corresponding to a target algorithm, starts algorithm operation and waits for the data operation to be completed; after the operation is finished, the DMA-Codec reads the calculation result data from the data register corresponding to the target algorithm and writes the calculation result data into the target address register of the DMA, and the DMA data length register reduces the length of a group of data so as to finish the algorithm operation of the group of data; at the moment, the USB serial interface controller simultaneously receives the next packet of plaintext data and writes the next packet of plaintext data into the USB RxFIFO, and the USB RxFIFO stops receiving the data packet to be encrypted and decrypted until no space exists; when the DMA algorithm function finishes 512B data encryption, the USB RxFIFO space of 512B is released, and the chip USB automatically receives the data of the next packet from the USB host and writes the data into the USB RxFIFO;
s6, when the DMA controller finishes the operation of the interrupt service program, the CSW of 13 bytes is filled into the USB TxFIFO of the chip, the USB serial interface controller returns the CSW to the USB host, and the APDU instruction overall process of the current encryption and decryption data is completed.
6. The high-speed data encryption and decryption method as claimed in claim 5, wherein the USB RxFIFO memory in step S2 is 8K bytes, and the operating system COS configures the OUT endpoint receiving register of the USB serial interface controller in step S4, specifically comprising: the USB data transceiver receives the number of data packets to be issued and then enables the receiving function of an Out endpoint;
the register of the configuration algorithm coprocessor specifically comprises the following steps: initializing an encryption and decryption algorithm, and configuring a relevant register of a target algorithm;
configuring the DMA module register specifically includes: the DMA source address register is configured to be RxFIFO, the target address register is the starting address of the encryption and decryption SRAM buffer area, and the DMA operation data length register is the number of transmission data packets in CBW multiplied by 512B.
7. A method for reading the encryption and decryption result of high-speed data, which is based on the high-speed data encryption and decryption chip based on the USB interface of any one of claims 1 to 4, and comprises the following steps:
a1, COS obtains the data packet length SendSize from CBW 31B, writes the SendSize information into the target end point IN control register of USB serial interface controller and enables the sending function;
a2, configuring a USB target endpoint IN control register and a DMA controller target address, a source address and a transfer length, wherein the target address is TxFIFO, the source address is the starting address of an encryption/decryption 20K Codec RAM buffer area, the transfer length is the available space TxFIFOCurSize of the current TxFIFO, and starting the DMA controller;
a3, obtaining the current available space TxFIFOCurSize1 of USB TxFIFO, if SendSize > TxFIFOCurSize1 and the length of the sent data packet is equal to half of the current available space of TxFIFO, then the USB controller will generate TxFIFO half-empty interrupt at this moment, enter step A4, if SendSize < TxFIFOCurSize1, the length of the sent data packet is equal to the length of the data packet to be read, and directly enter step A5;
a4, newly acquiring the available space TxFIFOCurSize2 of the current TxFIFO to be X K, reconfiguring the DMA transfer length to be X K again, starting the DMA, and modifying the current data to be read to be SendSize = SendSize-X; repeating the step until the SendSize value is 0, and entering the step A5;
a5, in the last time of finishing the interrupt service program by DMA operation, filling 13 bytes of CSW into the USB TxFIFO of the chip, and at this time, finishing the current Bulk protocol transmission, namely reading APDU instruction of the encryption and decryption result.
8. The method for reading the encryption/decryption result of high-speed data according to claim 7, wherein the size of the USB TxFIFO configuration is 4KB space, 8 USB packets of 512B are written by DMA according to 512B packets, and when DMA writes one packet of 512B, the USB IP automatically generates a "port number transaction" message to the Tx In request queue;
when the number of data packets requested to be read by the USB host is more than 8, the USB TxFIFO half-empty interrupt is enabled, and when the USB IP TxFIFO sends 4 512B data packets, the TxFIFO half-empty USB interrupt is generated to inform the CPU; in the USB half-empty interrupt service program, the DMA is configured to continuously move the data packet to be sent to the USB TxFIFO.
9. The method for reading the encryption and decryption results of the high-speed data according to claim 7, wherein the DMA comprises a normal DMA, a peripheral DMA and an algorithm DMA, and the normal DMA is carried between a memory and a normal IP; the peripheral DMA is carried between the USB and the memory; the algorithm DMA is carried between a memory and an algorithm memory;
the operation principle flow of the algorithm DMA is as follows:
the first step is as follows: initializing an algorithm, and configuring Key and IV related registers of a target algorithm;
the second step is that: initializing DMA, and configuring a DMA data source address RxFIFO, a DMA data target address and a DMA operation data length register;
the third step: configuring a DMA transmission control register according to the algorithm type, and starting the algorithm DMA to perform algorithm operation;
the fourth step: the algorithm DMA reads a group of data from the data source address of the DMA, writes the data into a data register corresponding to the algorithm, starts algorithm operation and waits for the completion of the data operation; and then the algorithm DMA reads the calculation result data from the corresponding data register, writes the calculation result data into the data target address of the DMA and increases the address, and the DMA data length register reduces the length of a group of data so as to finish the algorithm encryption and decryption and reading operation of the group of data.
CN202210455007.7A 2022-04-28 2022-04-28 Method for realizing data encryption, decryption and reading of high-speed chip based on USB interface Active CN114547663B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210455007.7A CN114547663B (en) 2022-04-28 2022-04-28 Method for realizing data encryption, decryption and reading of high-speed chip based on USB interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210455007.7A CN114547663B (en) 2022-04-28 2022-04-28 Method for realizing data encryption, decryption and reading of high-speed chip based on USB interface

Publications (2)

Publication Number Publication Date
CN114547663A true CN114547663A (en) 2022-05-27
CN114547663B CN114547663B (en) 2022-07-22

Family

ID=81667732

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210455007.7A Active CN114547663B (en) 2022-04-28 2022-04-28 Method for realizing data encryption, decryption and reading of high-speed chip based on USB interface

Country Status (1)

Country Link
CN (1) CN114547663B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115292236A (en) * 2022-09-30 2022-11-04 山东华翼微电子技术股份有限公司 Multi-core acceleration method and device based on high-speed interface

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825878A (en) * 1996-09-20 1998-10-20 Vlsi Technology, Inc. Secure memory management unit for microprocessor
US20060288235A1 (en) * 2005-06-17 2006-12-21 Fujitsu Limited Secure processor and system
CN101551784A (en) * 2008-04-02 2009-10-07 西北工业大学 Method and device for encrypting data in ATA memory device with USB interface
CN103777918A (en) * 2012-10-18 2014-05-07 苏州简约纳电子有限公司 Hardware accelerator
CN112329038A (en) * 2020-11-15 2021-02-05 珠海市一微半导体有限公司 Data encryption control system and chip based on USB interface

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5825878A (en) * 1996-09-20 1998-10-20 Vlsi Technology, Inc. Secure memory management unit for microprocessor
US20060288235A1 (en) * 2005-06-17 2006-12-21 Fujitsu Limited Secure processor and system
CN101551784A (en) * 2008-04-02 2009-10-07 西北工业大学 Method and device for encrypting data in ATA memory device with USB interface
CN103777918A (en) * 2012-10-18 2014-05-07 苏州简约纳电子有限公司 Hardware accelerator
CN112329038A (en) * 2020-11-15 2021-02-05 珠海市一微半导体有限公司 Data encryption control system and chip based on USB interface

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
张彤等: "即时加速非对齐数据传输的dma设计方法", 《电子测量技术》 *
张锋等: "一种高速免驱USB加密卡的设计与实现", 《计算机工程》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115292236A (en) * 2022-09-30 2022-11-04 山东华翼微电子技术股份有限公司 Multi-core acceleration method and device based on high-speed interface

Also Published As

Publication number Publication date
CN114547663B (en) 2022-07-22

Similar Documents

Publication Publication Date Title
EP1943595B1 (en) Unified dma
US8266338B2 (en) Data flow control within and between DMA channels
EP2803012B1 (en) Using storage controller bus interfaces to secure data transfer between storage devices and hosts
US6823403B2 (en) DMA mechanism for high-speed packet bus
US20110307759A1 (en) Functional DMA
US7707321B2 (en) Chained DMA for low-power extended USB flash device without polling
KR20150143708A (en) Storage device assisted inline encryption and decryption
CN114662136B (en) PCIE (peripheral component interface express) channel-based high-speed encryption and decryption system and method for multi-algorithm IP (Internet protocol) core
US6889266B1 (en) Method for delivering packet boundary or other metadata to and from a device using direct memory controller
US9317462B2 (en) Microcontroller peripheral data transfer redirection for resource sharing
CN109992543A (en) A kind of PCI-E data efficient transmission method based on ZYZQ-7000
CN110688333A (en) PCIE (peripheral component interface express) -based DMA (direct memory Access) data transmission system and method
CN114547663B (en) Method for realizing data encryption, decryption and reading of high-speed chip based on USB interface
CN114817965A (en) High-speed encryption and decryption system and method for realizing MSI interrupt processing based on multi-algorithm IP (Internet protocol) core
KR100799305B1 (en) High-Performance Cryptographic Device using Multiple Ciphercores and its Operation Method
CN101655894B (en) Method for improving throughput of grouping algorithm on general serial bus encryption lock
CN105468983B (en) Data transmission method and device based on SATA interface
US6032204A (en) Microcontroller with a synchronous serial interface and a two-channel DMA unit configured together for providing DMA requests to the first and second DMA channel
JP2008502977A (en) Interrupt method for bus controller
CN210836072U (en) Bridge chip for converting stream encryption USB interface into FIFO interface
CN114943087A (en) Multi-algorithm-core high-performance SR-IOV encryption and decryption system and method
US20220416997A1 (en) Handling unaligned transactions for inline encryption
KR20090059602A (en) Encrypting device having session memory bus
CN112470136A (en) Direct memory access controller
CN115292236B (en) Multi-core acceleration method and device based on high-speed interface

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant