CN110677017A - Driving circuit of low-EMI normally-on SiJFET - Google Patents
Driving circuit of low-EMI normally-on SiJFET Download PDFInfo
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- CN110677017A CN110677017A CN201910978703.4A CN201910978703A CN110677017A CN 110677017 A CN110677017 A CN 110677017A CN 201910978703 A CN201910978703 A CN 201910978703A CN 110677017 A CN110677017 A CN 110677017A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
- H02M1/0054—Transistor switching losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention provides a driving circuit of a low EMI normally-on SiJFET (silicon-based junction field effect transistor), which comprises a driving current regulating circuit, a driving voltage clamping module, a driving power tube Q2, a driving voltage turn-off power tube Q3 and an inverter INV1, wherein the driving current regulating circuit comprises a driving current regulating circuit, a driving voltage clamping module, a driving power tube Q2, a driving voltage turn-off; the drain electrode of the driving power tube Q2 is connected with the source electrode of the normally-on SiJFET power tube Q1, and the source electrode of the driving power tube Q2 is connected with the grid electrode of the SiJFET power tube Q1 and grounded; the grid electrode of the driving power tube Q2 is connected with the driving voltage vDrv; the driving current regulating circuit 110 is connected with a switching signal In, and the current output end of the driving current regulating circuit 110 is connected with the grid electrode of the driving power tube Q2; the driving voltage clamping module 140 is connected with the gate of the driving power tube Q2; the input end of the inverter INV1 is connected with the switching signal In, the output end is connected with the grid electrode of the driving voltage turn-off power tube Q3, the source electrode of Q3 is grounded, and the drain electrode is connected with the grid electrode of the driving power tube Q2; the invention realizes a normal SiC JFET drive circuit with low loss and low EMI.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a driving circuit of a low-EMI normally-on SiJFET.
Background
The SiCMOS tube has the performance advantages of high thermal conductivity, low on-state resistance, high switching speed and the like, and is very suitable for high-temperature, high-efficiency and high-frequency occasions. SiC power devices are of two types, normally-on and normally-off. Compared with a normally-on SiC JFET, the normally-off SiC JFET power device is large in on-state resistance. Therefore, the normal SiC JFET has very wide application.
The normally-on SiC JFET is usually cascaded with the low-voltage MOS to form a Cascode structure, and the on and off of the normally-on SiC JFET are controlled by a switch of the low-voltage MOS. The source electrode driving mode of the Cascode is high in speed and can meet the requirements of high-frequency occasions, but the Cascode structure has high requirements on the driving mode of low-voltage MOS, the driving speed is too high, the EMI is poor, and the loss is increased when the driving speed is too low.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a normally-on SiC JFET drive circuit capable of realizing low loss and low EMI. The technical scheme adopted by the invention is as follows:
a drive circuit of a low EMI normally-on SiJFET comprises a drive current regulating circuit, a drive voltage clamping module, a drive power tube Q2, a drive voltage turn-off power tube Q3 and an inverter INV 1;
the drain electrode of the driving power tube Q2 is connected with the source electrode of the normally-on SiJFET power tube Q1, and the source electrode of the driving power tube Q2 is connected with the grid electrode of the SiJFET power tube Q1 and grounded; the grid electrode of the driving power tube Q2 is connected with the driving voltage vDrv;
the driving current regulating circuit 110 is connected with a switching signal In, and the current output end of the driving current regulating circuit 110 is connected with the grid electrode of the driving power tube Q2; the driving voltage clamping module 140 is connected with the gate of the driving power tube Q2; the input end of the inverter INV1 is connected with the switching signal In, the output end is connected with the grid electrode of the driving voltage turn-off power tube Q3, the source electrode of Q3 is grounded, and the drain electrode is connected with the grid electrode of the driving power tube Q2;
the driving voltage vDrv is generated through a driving current regulating circuit, a driving voltage clamping module, a driving voltage turn-off power tube Q3 and an inverter INV 1;
the driving current adjusting circuit detects the driving voltage vDrv in real time and adjusts the magnitude of the driving current iDrv in real time according to the magnitude of the driving voltage vDrv.
Further, Q2 and Q3 are NMOS transistors.
Further, a drive current adjusting circuit including PMOS type bias current sources PB1, PB2, PB3, NMOS type current mirrors Ncm1, Ncm2, Ncm3, Ncm4, PMOS type current mirrors Pcm1, Pcm2, NMOS type switches Nsw1, Nsw2, Nsw3, Nsw4, resistors R1, R2, R3, R4, a pull-up resistor Rup, an inverter INV3, NMOS type current adjusting switches N1, N2, and a level converting circuit;
the gates of the bias current sources PB1, PB2 and PB3 are connected, and the sources of the bias voltages VBIAS1, PB1, PB2 and PB3 are connected; the drain of bias current source PB1 is connected to the drain and gate of current mirror Ncm1, the gate of Ncm2, the gate of Ncm3, and the gate of Ncm 4; the sources of the current mirrors Ncm1, Ncm2, Ncm3, Ncm4 are grounded; the drain of the current mirror Ncm2 is connected with the source of a current regulation switch N2 and the drain of a switch Nsw 1; the drain of the current mirror Ncm3 is connected with the source of the switch Nsw1 and the drain of the switch Nsw 2; the drain of the current mirror Ncm4 is connected with the source of the switch Nsw 2;
the drain of the bias current source PB2 is connected with the input end of the inverter INV3 and the drain of the switch Nsw 3; the source of the switch Nsw3 is grounded; the output end of the inverter INV3 is connected with the grid of the switch Nsw 2;
the drain of the bias current source PB3 is connected with the gate of the switch Nsw1 and the drain of the switch Nsw 4; the source of the switch Nsw4 is grounded;
the grid electrode of the current regulating switch N2 is connected with a switching signal In, the drain electrode of N2 is connected with the drain electrode of a current regulating switch N1, the drain electrode and the grid electrode of a current mirror Pcm1, the grid electrode of the current mirror Pcm2 and one end of a pull-up resistor Rup; the source of the current mirror Pcm1 is connected with the other end of the pull-up resistor Rup and the source of the current mirror Pcm 2; the drain electrode of the current mirror Pcm2 is connected with the current output end of the driving current regulating circuit;
the input end of the level conversion circuit 310 is connected with the switch signal In, and the output end is connected with the grid of the current adjusting switch N1; the source of the current regulating switch N1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with one end of a resistor R2 and the current output end of the driving current regulating circuit; the other end of the resistor R2 is connected with the gate of the switch Nsw3 and one end of the resistor R3; the other end of the resistor R3 is connected with the gate of the switch Nsw4 and one end of the resistor R4; the other end of the resistor R4 is connected to ground.
Further, the output of the level shift circuit is related to the input switch signal In, and is zero when the input switch signal In is at a low level, and is at a high level when the input switch signal In is at a high level.
Further, the output high level voltage of the level shifter circuit is clamped at tens of volts.
The invention has the advantages that: the invention detects the driving voltage in real time at the conduction stage of the SicJFET power tube, automatically adjusts the magnitude of the driving current in stages according to the magnitude of the driving voltage, forms a high-speed feedback control loop, and realizes a low-loss and low-EMI normal SiC JFET driving circuit.
Drawings
FIG. 1 is an electrical schematic of the present invention.
FIG. 2 is a signal diagram of the present invention.
FIG. 3 is a schematic diagram of a driving current regulating circuit according to the present invention.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1, the driving circuit of the low EMI normally-on SiCJFET includes a driving current adjusting circuit 110, a driving voltage clamping module 140, a driving power transistor Q2, a driving voltage turn-off power transistor Q3, and an inverter INV 1; q2 and Q3 are NMOS tubes;
the drain electrode of the driving power tube Q2 is connected with the source electrode of the normally-on SiJFET power tube Q1, and the source electrode of the driving power tube Q2 is connected with the grid electrode of the SiJFET power tube Q1 and grounded; the grid electrode of the driving power tube Q2 is connected with the driving voltage vDrv; a common SiJFET power tube Q1 and a driving tube Q2 form a Cascode structure;
the driving current regulating circuit 110 is connected with a switching signal In, and the current output end of the driving current regulating circuit 110 is connected with the grid electrode of the driving power tube Q2; the driving voltage clamping module 140 is connected with the gate of the driving power tube Q2; the input end of the inverter INV1 is connected with the switching signal In, the output end is connected with the grid electrode of the driving voltage turn-off power tube Q3, the source electrode of Q3 is grounded, and the drain electrode is connected with the grid electrode of the driving power tube Q2;
the driving voltage vDrv is generated through the driving current regulating circuit 110, the driving voltage clamping module 140, the driving voltage turn-off power transistor Q3 and the inverter INV 1;
the on and off of the normally-on SiJFET power tube Q1 are controlled by the on and off of the driving power tube Q2; when the driving voltage vDrv is at a high level, the driving power tube Q2 is switched on, the source electrode of the normally-on SiCJFET power tube Q1 is pulled to the ground level, and the normally-on SiCJFET power tube Q1 is switched on; when the driving voltage vDrv is at a low level, the driving power tube Q2 is turned off, the normally-on SiCJFET power tube Q1 pulls the source high, and at this time, V of the normally-on SiCJFET power tube Q1 is set to be VGSThe normally-on SiJFET power tube Q1 is a negative voltage and is turned off due to channel pinch-off;
when the switching signal In is at a high level, the driving current iDrv flows from the driving current regulating circuit 110 to the gate of the driving power transistor Q2, the gate voltage vDrv of the driving power transistor Q2 is gradually raised, and the driving voltage vDrv goes through three stages In the rising process, as shown In fig. 2; when the gate driving voltage vDrv of the driving power transistor Q2 reaches the clamping threshold of the voltage clamping module 140, the driving current iDrv will flow to the voltage clamping module 140, vDrv is clamped, and the driving power transistor Q2 is fully turned on.
The driving current adjusting circuit 110 detects the driving voltage vDrv in real time and adjusts the magnitude of the driving current iDrv in real time according to the magnitude of the driving voltage vDrv;
after the switching signal In changes from low to high, the driving voltage vDrv goes through three stages during the rising process, which correspond to three stages 210, 211, and 212 In fig. 2. In stage 210, the driving voltage vDrv gradually rises, and the driving current iDrv gradually falls; in the stage 211, the power tube Q2 is driven to enter the miller platform, the driving voltage vDrv is substantially constant, and the driving current iDrv is also substantially constant; at stage 212, the driving current iDrv reaches a maximum value, the driving voltage vDrv rapidly rises, and when the driving voltage vDrv reaches the clamp threshold voltage, the driving current iDrv instantly falls to a minimum value only for maintaining the driving voltage vDrv at a high level;
when the switching signal In is at a low level, the driving current iDrv is zero; the switching signal In passes through the inverter INV1 and then outputs a high level, and is connected to the gate of the power tube Q3, the power tube Q3 is turned on, the driving voltage vDrv is pulled to a low level, the power tube Q2 is turned off, and the normally-on SiCJFET power tube Q1 is turned off due to channel pinch-off.
As shown in fig. 3, the drive current adjustment circuit 110 includes PMOS type bias current sources PB1, PB2, PB3, NMOS type current mirrors Ncm1, Ncm2, Ncm3, Ncm4, PMOS type current mirrors Pcm1, Pcm2, NMOS type switches Nsw1, Nsw2, Nsw3, Nsw4, resistors R1, R2, R3, R4, pull-up resistors Rup, an inverter INV3, NMOS type current adjustment switches N1, N2, and a level conversion circuit 310;
the gates of the bias current sources PB1, PB2 and PB3 are connected, and the sources of the bias voltages VBIAS1, PB1, PB2 and PB3 are connected; the drain of bias current source PB1 is connected to the drain and gate of current mirror Ncm1, the gate of Ncm2, the gate of Ncm3, and the gate of Ncm 4; the sources of the current mirrors Ncm1, Ncm2, Ncm3, Ncm4 are grounded; the drain of the current mirror Ncm2 is connected with the source of a current regulation switch N2 and the drain of a switch Nsw 1; the drain of the current mirror Ncm3 is connected with the source of the switch Nsw1 and the drain of the switch Nsw 2; the drain of the current mirror Ncm4 is connected with the source of the switch Nsw 2;
the drain of the bias current source PB2 is connected with the input end of the inverter INV3 and the drain of the switch Nsw 3; the source of the switch Nsw3 is grounded; the output end of the inverter INV3 is connected with the grid of the switch Nsw 2;
the drain of the bias current source PB3 is connected with the gate of the switch Nsw1 and the drain of the switch Nsw 4; the source of the switch Nsw4 is grounded;
the grid electrode of the current regulating switch N2 is connected with a switching signal In, the drain electrode of N2 is connected with the drain electrode of a current regulating switch N1, the drain electrode and the grid electrode of a current mirror Pcm1, the grid electrode of the current mirror Pcm2 and one end of a pull-up resistor Rup; the source of the current mirror Pcm1 is connected with the other end of the pull-up resistor Rup and the source of the current mirror Pcm 2; the drain electrode of the current mirror Pcm2 is connected with the current output end of the driving current regulating circuit;
the input end of the level conversion circuit 310 is connected with the switch signal In, and the output end is connected with the grid of the current adjusting switch N1; the source of the current regulating switch N1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with one end of a resistor R2 and the current output end of the driving current regulating circuit; the other end of the resistor R2 is connected with the gate of the switch Nsw3 and one end of the resistor R3; the other end of the resistor R3 is connected with the gate of the switch Nsw4 and one end of the resistor R4; the other end of the resistor R4 is connected to ground.
The output of the level shifter 310 is related to the input switch signal In, when the input switch signal In is at a low level, the output of the level shifter 310 is zero, when the input switch signal In is at a high level, the output of the level shifter 310 is at a high level, and the high level voltage thereof is typically clamped at tens of volts.
When the input switching signal In is at a high level, N1 and N2 are turned on, and the current mirrors Pcm1 and Pcm2 are turned on, and when the input switching signal In is at a low level, N1 and N2 are turned off, and the current mirrors Pcm1 and Pcm2 are turned off after being pulled up by a resistor Rup on the gate.
In the initial state, vDrv is low voltage, and after the switching signal In changes from low to high, Nsw3 and Nsw4 are turned off, Nsw2 is turned off, Nsw1 is turned on, N1 and N2 are turned on, and the driving current ildrv is related to the current flowing through Ncm2, Ncm3 and N1, wherein the current passing through N1 is related to the driving voltage vDrv, the bias voltage VBIAS2 of the gate of N1 and the resistor R1, and I (N1) = (VBIAS 2-vdv)/R1.
As the driving voltage vDrv is gradually raised, the current flowing through N1 is gradually reduced, i.e., the driving current iDrv is gradually reduced.
After the driving voltage vDrv reaches the miller stage voltage of the power transistor Q2, the driving voltage vDrv is substantially constant at the miller stage, and the driving current iDrv is also substantially constant;
after the Miller stage is finished, the driving voltage vDrv is raised again, the Nsw3 is turned on, the output end of the inverter INV3 is made high, Nsw2 is turned on, and the driving current iDrv is related to the current flowing through Ncm2, Ncm3, Ncm4 and N1.
When the drive voltage vDrv is greater than the bias voltage VBIAS2 minus the on threshold voltage of N1, N1 is turned off and the current through N1 becomes zero.
When the driving voltage vDrv continues to rise, Nsw4 turns on, pulling down the gate of Nsw1 to turn Nsw1 off, and the driving current iDrv is related only to the current flowing through Ncm 2.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (5)
1. A drive circuit of a low EMI normally-on SiJFET is characterized by comprising a drive current regulating circuit (110), a drive voltage clamping module (140), a drive power tube Q2, a drive voltage turn-off power tube Q3 and an inverter INV 1;
the drain electrode of the driving power tube Q2 is connected with the source electrode of the normally-on SiJFET power tube Q1, and the source electrode of the driving power tube Q2 is connected with the grid electrode of the SiJFET power tube Q1 and grounded; the grid electrode of the driving power tube Q2 is connected with the driving voltage vDrv;
the driving current regulating circuit (110) is connected with a switching signal In, and the current output end of the driving current regulating circuit (110) is connected with the grid electrode of the driving power tube Q2; the driving voltage clamping module (140) is connected with the grid electrode of the driving power tube Q2; the input end of the inverter INV1 is connected with the switching signal In, the output end is connected with the grid electrode of the driving voltage turn-off power tube Q3, the source electrode of Q3 is grounded, and the drain electrode is connected with the grid electrode of the driving power tube Q2;
the driving voltage vDrv is generated through a driving current regulating circuit (110), a driving voltage clamping module (140), a driving voltage turn-off power tube Q3 and an inverter INV 1;
the driving current adjusting circuit (110) detects the driving voltage vDrv in real time and adjusts the magnitude of the driving current iDrv in real time according to the height of the driving voltage vDrv.
2. The low EMI normally-on SiJFET driver circuit of claim 1,
q2 and Q3 are NMOS tubes.
3. The low EMI normally-on SiJFET driver circuit of claim 1,
a drive current adjustment circuit (110) including PMOS-type bias current sources PB1, PB2, PB3, NMOS-type current mirrors Ncm1, Ncm2, Ncm3, Ncm4, PMOS-type current mirrors Pcm1, Pcm2, NMOS-type switches Nsw1, Nsw2, Nsw3, Nsw4, resistors R1, R2, R3, R4, a pull-up resistor Rup, an inverter INV3, NMOS-type current adjustment switches N1, N2, and a level conversion circuit (310);
the gates of the bias current sources PB1, PB2 and PB3 are connected, and the sources of the bias voltages VBIAS1, PB1, PB2 and PB3 are connected; the drain of bias current source PB1 is connected to the drain and gate of current mirror Ncm1, the gate of Ncm2, the gate of Ncm3, and the gate of Ncm 4; the sources of the current mirrors Ncm1, Ncm2, Ncm3, Ncm4 are grounded; the drain of the current mirror Ncm2 is connected with the source of a current regulation switch N2 and the drain of a switch Nsw 1; the drain of the current mirror Ncm3 is connected with the source of the switch Nsw1 and the drain of the switch Nsw 2; the drain of the current mirror Ncm4 is connected with the source of the switch Nsw 2;
the drain of the bias current source PB2 is connected with the input end of the inverter INV3 and the drain of the switch Nsw 3; the source of the switch Nsw3 is grounded; the output end of the inverter INV3 is connected with the grid of the switch Nsw 2;
the drain of the bias current source PB3 is connected with the gate of the switch Nsw1 and the drain of the switch Nsw 4; the source of the switch Nsw4 is grounded;
the grid electrode of the current regulating switch N2 is connected with a switching signal In, the drain electrode of N2 is connected with the drain electrode of a current regulating switch N1, the drain electrode and the grid electrode of a current mirror Pcm1, the grid electrode of the current mirror Pcm2 and one end of a pull-up resistor Rup; the source of the current mirror Pcm1 is connected with the other end of the pull-up resistor Rup and the source of the current mirror Pcm 2; the drain electrode of the current mirror Pcm2 is connected with the current output end of the driving current regulating circuit;
the input end of the level conversion circuit (310) is connected with a switch signal In, and the output end is connected with the grid of the current adjusting switch N1; the source of the current regulating switch N1 is connected with one end of a resistor R1, and the other end of the resistor R1 is connected with one end of a resistor R2 and the current output end of the driving current regulating circuit; the other end of the resistor R2 is connected with the gate of the switch Nsw3 and one end of the resistor R3; the other end of the resistor R3 is connected with the gate of the switch Nsw4 and one end of the resistor R4; the other end of the resistor R4 is connected to ground.
4. The low EMI normally-on SiJFET driver circuit of claim 3,
the output of the level shift circuit (310) is related to the input switch signal In, the output of the level shift circuit (310) is zero when the input switch signal In is at a low level, and the output of the level shift circuit (310) is at a high level when the input switch signal In is at a high level.
5. The low EMI normally-on SiJFET driver circuit of claim 4,
the output high level voltage of the level shifter circuit (310) is clamped at tens of volts.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910978703.4A CN110677017A (en) | 2019-10-15 | 2019-10-15 | Driving circuit of low-EMI normally-on SiJFET |
| PCT/CN2019/111582 WO2021072693A1 (en) | 2019-10-15 | 2019-10-17 | Low-emi normally-on sic jfet driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910978703.4A CN110677017A (en) | 2019-10-15 | 2019-10-15 | Driving circuit of low-EMI normally-on SiJFET |
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| Publication Number | Publication Date |
|---|---|
| CN110677017A true CN110677017A (en) | 2020-01-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910978703.4A Pending CN110677017A (en) | 2019-10-15 | 2019-10-15 | Driving circuit of low-EMI normally-on SiJFET |
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| CN (1) | CN110677017A (en) |
| WO (1) | WO2021072693A1 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9071245B2 (en) * | 2013-04-24 | 2015-06-30 | Hamilton Sundstrand Corporation | Solid state power controller gate control |
| US9954461B1 (en) * | 2017-06-12 | 2018-04-24 | Power Integrations, Inc. | Multiple stage gate drive for cascode current sensing |
| CN109981088B (en) * | 2018-12-28 | 2024-04-12 | 南京航空航天大学 | Driving circuit capable of adaptively adjusting switching speed of SiC MOSFET |
| CN109842279B (en) * | 2019-02-22 | 2021-07-02 | 湖南大学 | SiC MOSFET open-loop active driving circuit |
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2019
- 2019-10-15 CN CN201910978703.4A patent/CN110677017A/en active Pending
- 2019-10-17 WO PCT/CN2019/111582 patent/WO2021072693A1/en active Application Filing
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| WO2021072693A1 (en) | 2021-04-22 |
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