CN211377999U - High-reliability GaN power tube rapid gate drive circuit - Google Patents
High-reliability GaN power tube rapid gate drive circuit Download PDFInfo
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- CN211377999U CN211377999U CN202020318648.4U CN202020318648U CN211377999U CN 211377999 U CN211377999 U CN 211377999U CN 202020318648 U CN202020318648 U CN 202020318648U CN 211377999 U CN211377999 U CN 211377999U
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Abstract
The utility model provides a high reliable quick gate pole drive circuit of gaN power tube, include: the control end of the driving current regulating circuit and the input end of the inverter INV115 are connected with the input end of the gate drive circuit; the input end of the gate pole driving circuit is used for inputting a control signal On; the output end of the inverter INV115 is connected to the control end of the first MOS switch Q111 and the input end of the turn-off delay circuit; the output end of the turn-off delay circuit is connected with the control end of a second MOS switch Q113; the driving current regulating circuit outputs two current sources iCp and iDrv which are respectively connected to a node a and a node b at two ends of the charge pump capacitor C120; one switch of the first MOS switch Q111 is connected with a node a, and the other switch is connected with a reference ground; one switch of the second MOS switch Q113 is connected to the node b, and the other switch is connected to the reference ground; the node b is used as the output end of the gate pole driving circuit; the utility model discloses can promote gaN power tube operational reliability.
Description
Technical Field
The utility model belongs to the integrated circuit field especially relates to a quick gate pole drive circuit of high reliable gaN power tube.
Background
GaN High Electron Mobility Transistors (HEMTs) have high off-state breakdown strength and excellent channel conductivity in the on-state, and are a development trend for high frequency high power density switching power transistors. The breakdown strength of GaN material is 10 times higher than Si compared to Si, which means that for a given device size, 10 times more voltage can be applied to the GaN device compared to Si devices, and a more compact GaN device has as low on-resistance as possible since the specific on-resistance Ron is proportional to the length of the device drift region required to maintain a given breakdown voltage. Furthermore, the HEMT electron transfer characteristics of GaN devices are almost two orders of magnitude lower in specific on-resistance compared to Si power devices with the same voltage rating. Thus, GaN devices achieve both high breakdown voltage and high current levels, i.e., have high switching frequencies at high power levels.
GaN devices also have some drawbacks themselves. Firstly, the device has no avalanche voltage rating, so the gate drive is very critical, the absolute maximum voltage rating is typically only plus or minus 10V, and when the gate drive voltage is less than 5V, the dynamic on-resistance performance of the GaN device is deteriorated. In addition, the ultra-fast turn-on speed of GaN devices can result in poor EMI characteristics. In addition, enhancement mode (E-mode) GaN is generally a normally-off device, and its gate turn-on threshold of about 1.5V is also lower than that of about 3.5V of Si device, and the gate turn-on threshold is low and is prone to misturn-on in application. It is critical that the expected advantages of low loss, high power density, and high reliability be achieved, depending on the gate drive circuit having robust protection characteristics.
Therefore, highly reliable gate drive is critical to GaN device performance.
Disclosure of Invention
An object of the utility model is to overcome exist among the prior art not enough, provide a quick gate drive circuit of high reliable gaN power tube, can promote the EMI performance of gaN power tube during operation, promote operational reliability. The embodiment of the utility model provides a technical scheme who adopts is:
a high-reliability GaN power tube fast gate drive circuit comprises: the circuit comprises a driving current regulating circuit, a first MOS switch Q111, a turn-off delay circuit, a second MOS switch Q113, a driving voltage clamping circuit, an inverter INV115 and a charge pump capacitor C120;
the control end of the driving current regulating circuit and the input end of the inverter INV115 are connected with the input end of the gate drive circuit; the input end of the gate pole driving circuit is used for inputting a control signal On; the output end of the inverter INV115 is connected to the control end of the first MOS switch Q111 and the input end of the turn-off delay circuit; the output end of the turn-off delay circuit is connected with the control end of a second MOS switch Q113;
the driving current regulating circuit outputs two current sources iCp and iDrv which are respectively connected to a node a and a node b at two ends of the charge pump capacitor C120; one switch of the first MOS switch Q111 is connected with a node a, and the other switch is connected with a reference ground; one switch of the second MOS switch Q113 is connected to the node b, and the other switch is connected to the reference ground;
one end of the driving voltage clamping circuit is connected with a node b, and the other end of the driving voltage clamping circuit is connected with a reference ground;
and the node b is used as the output end of the gate driving circuit and used for outputting a driving voltage vDrv for driving the GaN power tube.
Further, two current sources iCp and iDrv output by the driving current adjusting circuit are controlled by a control signal On; when the control signal On is at a low level, the currents of the two output current sources iCp and iDrv are zero; when the control signal On is at a high level, the output currents of the two current sources iCp and iDrv vary with the driving voltage vDrv output by the gate driving circuit.
Furthermore, when the GaN power transistor driven by the gate driving circuit is fully turned On when the control signal On changes from low to high, the voltage vCp at the node a at one end of the charge pump capacitor C120 is higher than the voltage vDrv at the node b at the other end.
Furthermore, the input and the output of the turn-off delay circuit are in phase, and the output signal Offd of the turn-off delay circuit is delayed when the input signal off rises; the output signal Offd of the turn-off delay circuit is not delayed when its input signal off falling edge.
Furthermore, the output signal Offd of the turn-off delay circuit is delayed when the input signal off rises, and the delay time td is tens of nanoseconds.
Further, the drive current adjusting circuit includes: an inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, a controlled current source IBias1, a capacitor C1, a resistor Rup and an Rdrv;
the input end of the inverter INV1 and the grid electrode of the PMOS tube P0 are connected with the input end of the driving current regulating circuit; the output end of the inverter INV1 is connected with the grid of an NMOS tube N1, the source of N1 and one end of a capacitor C1 are connected with the ground, the drain of N1 is connected with the other end of a capacitor C1, the grid of an NMOS tube N2 and the current outflow end of a controlled current source IBias 1; the current inflow end of the controlled current source IBias1, the source electrode of the PMOS tube P1, the source electrode of P0, the source electrode of P2, the source electrode of P3 and one end of the resistor Rup are connected with a power supply voltage end; the gate of the P1 is connected with the drain of the P0, the other end of the resistor Rup, the gate of the P2, the gate of the P3 and the drain of the P1; the drain of P1 is connected with the drain of N2; the source of the N2 is connected with one end of a resistor Rdrv, and the other end of the resistor Rdrv is connected with the drain of the P2 and used for outputting a current source iDrv; the drain of P3 is used to output current source iCp.
Furthermore, the driving voltage clamping circuit is formed by connecting two back-to-back clamping diodes in series; the positive voltage threshold of the driving voltage clamping circuit is set within the safe conduction voltage range of the GaN power tube driven by the gate pole driving circuit.
Further, the second MOS switch Q113 is formed by connecting two back-to-back NMOS transistors in series, and gates of the two back-to-back NMOS transistors are connected to serve as control terminals thereof.
Further, the first MOS switch Q111 employs a single NMOS transistor.
The utility model has the advantages that: the utility model provides a high-reliability GaN power tube rapid gate drive circuit, which controls the opening speed of a GaN power tube by controlling the change rate of drive current in the conduction and opening stage of the GaN power tube, thereby improving the EMI performance; in the conduction stage of the GaN power tube, the grid driving voltage of the GaN is accurately controlled, and the working reliability of the GaN power tube is improved; in the GaN power tube turn-off stage, the charge pump generates negative grid drive voltage, so that the GaN power tube can be turned off rapidly, false triggering is avoided, and the reliability under high-speed switching is solved.
Drawings
Fig. 1 is an electrical schematic diagram of a gate driving circuit according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a driving current adjusting circuit according to an embodiment of the present invention.
Fig. 3 is a signal timing diagram according to an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following specific drawings and examples.
The embodiment of the utility model provides a high reliable quick gate drive circuit of GaN power tube (this is called the gate drive circuit for short), as shown in FIG. 1, include: the driving circuit comprises a driving current regulating circuit 110, a first MOS switch Q111, a turn-off delay circuit 112, a second MOS switch Q113, a driving voltage clamping circuit 114, an inverter INV115 and a charge pump capacitor C120;
the control end of the driving current regulating circuit 110 and the input end of the inverter INV115 are connected with the input end of the gate driving circuit; the input end of the gate pole driving circuit is used for inputting a control signal On; the output end of the inverter INV115 is connected to the control end of the first MOS switch Q111 and the input end of the turn-off delay circuit 112; the output end of the turn-off delay circuit 112 is connected with the control end of a second MOS switch Q113;
the driving current adjusting circuit 110 outputs two current sources iCp and iDrv, which are respectively connected to a node a and a node b at two ends of the charge pump capacitor C120; one switch of the first MOS switch Q111 is connected with a node a, and the other switch is connected with a reference ground; one switch of the second MOS switch Q113 is connected to the node b, and the other switch is connected to the reference ground;
one end of the driving voltage clamping circuit 114 is connected with a node b, and the other end is connected with a reference ground;
the node b is used as the output end of the gate driving circuit and is used for outputting a driving voltage vDrv for driving the GaN power tube;
in the present embodiment, the driving voltage vDrv is generated by the combined action of the driving current adjusting circuit 110, the first MOS switch Q111, the turn-off delay circuit 112, the second MOS switch Q113, the driving voltage clamping circuit 114, the inverter INV115, and the charge pump capacitor C120;
the grid electrode of the GaN power tube Q100 is connected with the driving voltage vDrv output by the gate electrode driving circuit, the drain electrode of the GaN power tube Q100 is connected with the load 101 of the GaN power tube Q100, and the source electrode of the GaN power tube Q100 is connected with the current detection circuit 102;
the first MOS switch Q111 adopts a single NMOS tube; the control end of the single NMOS tube is the grid electrode of the single NMOS tube;
the second MOS switch Q113 is preferably formed by connecting two back-to-back NMOS transistors in series, and gates of the two back-to-back NMOS transistors are connected to serve as control ends of the two back-to-back NMOS transistors; when two NMOS tubes of the MOS switch are turned off, no parasitic path exists at two ends, and two diodes shown in Q113 are parasitic diodes of the MOS; when the grid of the second MOS switch Q113 is at a low level, the two internal NMOS switches are switched off, and no matter the positive voltage or the negative voltage is applied to the two ends of the MOS switch, a current path is not formed;
the second MOS switch Q113 may also adopt a single NMOS transistor, but it is not a preferable solution, when the GaN power transistor Q100 starts to turn off, and the driving voltage vDrv becomes a negative voltage, the negative voltage is limited to about-0.6 v due to the effect of the parasitic diode in the MOS transistor;
the driving voltage clamping circuit 114 is formed by connecting two back-to-back clamping diodes in series, so that the driving voltage clamping circuit 114 can clamp both positive voltage and negative voltage, and the reliability of the GaN power tube in the switching process is fully ensured;
two current sources iCp and iDrv output by the driving current adjusting circuit 110 are controlled by a control signal On; when the control signal On is at a low level, the currents of the two output current sources iCp and iDrv are zero; when the control signal On is at a high level, the output current of the two current sources iCp and iDrv changes along with the drive voltage vDrv output by the gate pole drive circuit;
the first MOS switch Q111 is controlled by the output of an inverter INV115, and the input end of the inverter INV115 is connected with a control signal On; when On is low, the output of the inverter INV115 is high, and the first MOS switch Q111 is turned On; when On is high level, the output of the inverter INV115 is low level, and the first MOS switch Q111 is turned off;
the second MOS switch Q113 is controlled by the turn-off delay circuit 112, the input and the output of the turn-off delay circuit 112 are in phase, and the delay time td of the output signal Offd of the turn-off delay circuit 112 can be tens of nanoseconds when the input signal off rises; the output signal Offd of the turn-off delay circuit 112 is not delayed when the input signal off falls; the delay circuit is a relatively mature circuit and is not described herein again;
in an initial state, the control signal On is at a low level, at this time, the two current sources iCp and iDrv output by the driving current adjusting circuit 110 are both zero, the first MOS switch Q111 is turned On, the second MOS switch Q113 is also turned On, the driving voltage vDrv output by the gate driving circuit is zero, and the GaN power tube Q100 is turned off;
when the control signal On changes from low level to high level, the inverter INV115 outputs low level, the turn-off delay circuit 112 also outputs low level immediately, the first MOS switch Q111 is turned off immediately, the second MOS switch Q113 is also turned off immediately, the two current sources idc, iDrv output by the driving current adjusting circuit 110 charge the two ends of the charge pump capacitor C120 respectively, the voltages vcc, vDrv at the two ends of the charge pump capacitor C120 increase, and the output voltage vDrv of the gate driving circuit changes from zero to high; when the driving voltage vDrv reaches the conduction threshold of the GaN power tube Q100, the GaN power tube Q100 is conducted, the two current sources iCp and iDrv output by the driving current adjusting circuit 110 continue to charge the two ends of the charge pump capacitor C120, the voltages vCp and vDrv at the two ends of the charge pump capacitor C120 continue to be raised, and the GaN power tube Q100 is fully conducted; when the driving voltage vDrv reaches the positive voltage threshold of the driving voltage clamp circuit 114, the current source iDrv current outputted by the driving current regulating circuit 110 is absorbed by the driving voltage clamp circuit 114, the driving voltage vDrv is clamped, the driving voltage of the GaN power tube is clamped at about 6V, and the voltage vCp at the node a continues to be charged by the current source iCp outputted by the driving current regulating circuit 110; when the voltage vCp reaches the power supply voltage of the driving current adjusting circuit 110, the current of the current source iCp automatically drops to zero, at this time, the voltage vCp at the node a at one end of the charge pump capacitor C120 is the power supply voltage of the driving current adjusting circuit 110, and the voltage vDrv at the node b at the other end of the charge pump capacitor C120 is about 6V; in this embodiment, when the control signal On changes from low level to high level and the GaN power transistor Q100 is fully turned On, the voltage vCp of the node a at one end of the charge pump capacitor C120 is required to be higher than the voltage vDrv of the node b at the other end;
when the control signal On changes from high level to low level, the currents of the two current sources iCp and iDrv output by the driving current adjusting circuit 110 immediately become zero, the first MOS switch Q111 immediately turns On, and the second MOS switch Q113 continues to be turned off due to the control of the turn-off delay circuit 112; because the voltage difference across the charge pump capacitor C120 cannot be transient and the previous voltage vCp is higher than the voltage vDrv, when the voltage vCp at the node a at one end of the charge pump capacitor C120 is pulled to zero by the first MOS switch Q111, the voltage vDrv becomes a negative voltage, and the GaN power transistor 100 is turned off rapidly;
the magnitude of the negative voltage of the driving voltage vDrv depends On the voltage difference between two ends of the charge pump capacitor C120 before the control signal On changes from high to low, the capacitance value of the charge pump capacitor C120 and the magnitude of the gate junction capacitance of the GaN power tube 100; the maximum negative voltage of vDrv is the negative voltage threshold of the drive voltage clamp 114;
after the delay of tens of nanoseconds by the turn-off delay circuit 112, the second MOS switch Q113 is also turned on, the driving voltage vDrv is pulled back to zero level, and the GaN power tube 100 maintains the turn-off state;
in one embodiment, the driving current adjusting circuit 110 is shown in fig. 2 and includes: an inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, a controlled current source IBias1, a capacitor C1, a resistor Rup and an Rdrv;
the input end of the inverter INV1 and the grid electrode of the PMOS tube P0 are connected with the input end of the driving current regulating circuit; the output end of the inverter INV1 is connected with the grid of an NMOS tube N1, the source of N1 and one end of a capacitor C1 are connected with the ground, the drain of N1 is connected with the other end of a capacitor C1, the grid of an NMOS tube N2 and the current outflow end of a controlled current source IBias 1; the current inflow end of the controlled current source IBias1, the source electrode of the PMOS tube P1, the source electrode of P0, the source electrode of P2, the source electrode of P3 and one end of the resistor Rup are connected with a power supply voltage end; the gate of the P1 is connected with the drain of the P0, the other end of the resistor Rup, the gate of the P2, the gate of the P3 and the drain of the P1; the drain of P1 is connected with the drain of N2; the source of the N2 is connected with one end of a resistor Rdrv, and the other end of the resistor Rdrv is connected with the drain of the P2 and used for outputting a current source iDrv; the drain of P3 is used to output current source iCp;
wherein, P1, P2 and P3 form a current mirror; the power supply voltage end is connected with a power supply voltage VDD;
when the control signal On is at a low level, the inverter INV1 outputs a high level, at this time, the PMOS transistor P0 is turned On, the NMOS transistor N1 is turned On, the voltage vGn of the gate of the N2 is at a low level, the voltages vGp of the gates of the P1, P2 and P3 are at a high level, the driving current adjusting MOS transistor N2 is turned off, and the current mirrors P1, P2 and P3 are turned off;
when the control signal On is at a high level, the inverter INV1 outputs a low level, at this time, the PMOS transistor P0 is turned off, the NMOS transistor N1 is turned off, the controlled current source Ibias1 charges the capacitor C1, the voltage vGn rises, when the voltage vGn is greater than the threshold voltage of the driving current adjusting MOS transistor N2, the N2 is turned On, and the current flowing through the N2 generates current sources iCp and iDrv through the current mirrors P1, P2 and P3;
wherein the rate of change of current source iCp and iDrv can be controlled by adjusting the magnitude of controlled current source Ibias 1;
wherein, the resistor Rdrv can set the current magnitude of the current sources iCp and iDrv; the resistor Rdrv can also affect the voltage difference across the charge pump capacitor C120;
wherein the current mirrors P1, P2, P3 may set the current magnitude and proportion of the current sources iCp and iDrv;
the gate drive control timing of the GaN power tube, see fig. 3;
when the control signal On changes from low to high, the input signal Off and the output signal Off of the turn-Off delay circuit 112 change from high to low at the same time, and the driving voltage vDrv rises from zero and is clamped at about 6V;
when the control signal On changes from high to low, the input signal Off of the turn-Off delay circuit 112 changes from low to high immediately, so that the first MOS switch Q111 is also turned On immediately, the output signal Offd of the turn-Off delay circuit 112 changes from low to high immediately after the delay td, the driving voltage vDrv decreases from 6V to a negative voltage, and then is pulled back to zero level after a delay of tens of nanoseconds.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the examples, those skilled in the art should understand that the technical solutions of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the scope of the claims of the present invention.
Claims (10)
1. A high-reliability GaN power tube fast gate drive circuit is characterized by comprising: the circuit comprises a driving current regulating circuit (110), a first MOS switch Q111, a turn-off delay circuit (112), a second MOS switch Q113, a driving voltage clamping circuit (114), an inverter INV115 and a charge pump capacitor C120;
the control end of the driving current regulating circuit (110) and the input end of the inverter INV115 are connected with the input end of the gate driving circuit; the input end of the gate pole driving circuit is used for inputting a control signal On; the output end of the inverter INV115 is connected with the control end of the first MOS switch Q111 and the input end of the turn-off delay circuit (112); the output end of the turn-off delay circuit (112) is connected with the control end of a second MOS switch Q113;
the driving current adjusting circuit (110) outputs two current sources iCp and iDrv which are respectively connected to a node a and a node b at two ends of the charge pump capacitor C120; one switch of the first MOS switch Q111 is connected with a node a, and the other switch is connected with a reference ground; one switch of the second MOS switch Q113 is connected to the node b, and the other switch is connected to the reference ground;
one end of the driving voltage clamping circuit (114) is connected with a node b, and the other end is connected with a reference ground;
and the node b is used as the output end of the gate driving circuit and used for outputting a driving voltage vDrv for driving the GaN power tube.
2. The high-reliability GaN power tube fast gate drive circuit of claim 1,
two current sources iCp and iDrv output by the driving current regulating circuit (110) are controlled by a control signal On; when the control signal On is at a low level, the currents of the two output current sources iCp and iDrv are zero; when the control signal On is at a high level, the output currents of the two current sources iCp and iDrv vary with the driving voltage vDrv output by the gate driving circuit.
3. The high-reliability GaN power tube fast gate drive circuit of claim 2,
when the GaN power transistor driven by the gate driving circuit is fully turned On when the control signal On changes from low level to high level, the voltage vCp at the node a at one end of the charge pump capacitor C120 is higher than the voltage vDrv at the node b at the other end.
4. The high-reliability GaN power tube fast gate drive circuit of claim 1, 2 or 3,
the input and the output of the turn-off delay circuit (112) are in phase, and the output signal Offd of the turn-off delay circuit (112) is delayed when the input signal off rises; the output signal Offd of the turn-off delay circuit (112) is not delayed when the input signal off falls.
5. The high-reliability GaN power tube fast gate drive circuit of claim 4,
the output signal Offd of the turn-off delay circuit (112) is delayed at the rising edge of the off input signal, and the delay time td is tens of nanoseconds.
6. The high-reliability GaN power tube fast gate drive circuit of claim 1, 2 or 3,
the drive current adjustment circuit (110) includes: an inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, a controlled current source IBias1, a capacitor C1, a resistor Rup and an Rdrv;
the input end of the inverter INV1 and the grid electrode of the PMOS tube P0 are connected with the input end of the driving current regulating circuit; the output end of the inverter INV1 is connected with the grid of an NMOS tube N1, the source of N1 and one end of a capacitor C1 are connected with the ground, the drain of N1 is connected with the other end of a capacitor C1, the grid of an NMOS tube N2 and the current outflow end of a controlled current source IBias 1; the current inflow end of the controlled current source IBias1, the source electrode of the PMOS tube P1, the source electrode of P0, the source electrode of P2, the source electrode of P3 and one end of the resistor Rup are connected with a power supply voltage end; the gate of the P1 is connected with the drain of the P0, the other end of the resistor Rup, the gate of the P2, the gate of the P3 and the drain of the P1; the drain of P1 is connected with the drain of N2; the source of the N2 is connected with one end of a resistor Rdrv, and the other end of the resistor Rdrv is connected with the drain of the P2 and used for outputting a current source iDrv; the drain of P3 is used to output current source iCp.
7. The high-reliability GaN power tube fast gate drive circuit of claim 4,
the drive current adjustment circuit (110) includes: an inverter INV1, NMOS transistors N1, N2, PMOS transistors P0, P1, P2, P3, a controlled current source IBias1, a capacitor C1, a resistor Rup and an Rdrv;
the input end of the inverter INV1 and the grid electrode of the PMOS tube P0 are connected with the input end of the driving current regulating circuit; the output end of the inverter INV1 is connected with the grid of an NMOS tube N1, the source of N1 and one end of a capacitor C1 are connected with the ground, the drain of N1 is connected with the other end of a capacitor C1, the grid of an NMOS tube N2 and the current outflow end of a controlled current source IBias 1; the current inflow end of the controlled current source IBias1, the source electrode of the PMOS tube P1, the source electrode of P0, the source electrode of P2, the source electrode of P3 and one end of the resistor Rup are connected with a power supply voltage end; the gate of the P1 is connected with the drain of the P0, the other end of the resistor Rup, the gate of the P2, the gate of the P3 and the drain of the P1; the drain of P1 is connected with the drain of N2; the source of the N2 is connected with one end of a resistor Rdrv, and the other end of the resistor Rdrv is connected with the drain of the P2 and used for outputting a current source iDrv; the drain of P3 is used to output current source iCp.
8. The high-reliability GaN power tube fast gate drive circuit of claim 1, 2 or 3,
the driving voltage clamping circuit (114) is formed by connecting two back-to-back clamping diodes in series; the positive voltage threshold of the driving voltage clamping circuit (114) is set within the safe conduction voltage range of the GaN power tube driven by the gate electrode driving circuit.
9. The high-reliability GaN power tube fast gate drive circuit of claim 1, 2 or 3,
the second MOS switch Q113 is formed by two back-to-back NMOS transistors connected in series, and the gates of the two back-to-back NMOS transistors are connected as the control terminals.
10. The high-reliability GaN power tube fast gate drive circuit of claim 1, 2 or 3,
the first MOS switch Q111 uses a single NMOS transistor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112953485A (en) * | 2021-01-27 | 2021-06-11 | 深圳市矽塔科技有限公司 | Shutoff control circuit and electronic equipment thereof |
| WO2021179342A1 (en) * | 2020-03-13 | 2021-09-16 | 无锡硅动力微电子股份有限公司 | High-reliability gan power tube fast gate drive circuit |
| CN114430519A (en) * | 2022-02-09 | 2022-05-03 | 深圳木芯科技有限公司 | Output stage circuit and audio equipment |
| CN115173854A (en) * | 2022-09-06 | 2022-10-11 | 英彼森半导体(珠海)有限公司 | Self-adaptive MOS transistor threshold voltage reduction circuit |
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- 2020-03-13 CN CN202020318648.4U patent/CN211377999U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021179342A1 (en) * | 2020-03-13 | 2021-09-16 | 无锡硅动力微电子股份有限公司 | High-reliability gan power tube fast gate drive circuit |
| CN112953485A (en) * | 2021-01-27 | 2021-06-11 | 深圳市矽塔科技有限公司 | Shutoff control circuit and electronic equipment thereof |
| CN114430519A (en) * | 2022-02-09 | 2022-05-03 | 深圳木芯科技有限公司 | Output stage circuit and audio equipment |
| CN115173854A (en) * | 2022-09-06 | 2022-10-11 | 英彼森半导体(珠海)有限公司 | Self-adaptive MOS transistor threshold voltage reduction circuit |
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