CN109818257B - CMOS (complementary Metal oxide semiconductor) process laser driving circuit - Google Patents
CMOS (complementary Metal oxide semiconductor) process laser driving circuit Download PDFInfo
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Abstract
The invention discloses a CMOS process laser driving circuit which comprises an input Current Mode Logic (CML) circuit, an embedded low voltage difference linear voltage stabilizer circuit, a negative feedback clamping circuit and a common mode feedback circuit. The structure differential digital voltage signal is converted into a switch current signal for driving a laser diode; meanwhile, an externally arranged reference current signal is received, the level of an externally input differential digital voltage signal is adjusted by adopting a negative feedback principle, and then the magnitude of a switching current signal is adjusted to be in direct proportion to the reference current signal. The invention is used in the laser diode driver circuit of CMOS process, it features that the output current and the setting current are converted into voltage form by the resistance, the voltage is compared, and the output current of the output current tube is driven by the common mode feedback circuit to reach the set current; the working speed of the laser driver in the CMOS process is improved while the output current capability is ensured.
Description
Technical Field
The invention relates to a laser driving circuit for a CMOS (complementary metal oxide semiconductor) process, in particular to a circuit for realizing modulation current with the transmission rate of more than 1Gbps and more than 50mA in the CMOS process, belonging to the technical field of photoelectric conversion devices.
Background
With the rapid increase of communication data traffic, the demand for optical fiber data transmission chips is increasing. Laser driver circuits are important components in fiber optic transceiver modules, where the speed and signal quality of the driving output signal affects the performance of the transmission system. At present, the laser driver circuit mostly adopts an advanced Gesi process to meet the requirement of outputting and driving high-speed large current. The laser driving circuit of the traditional CMOS process is realized by adopting a switch current source, so that a tail current source needs to support the current change of 1 milliampere to dozens of milliamperes, and the current source with the large current range change is difficult to realize even if the influence of current mismatch is not considered. And a large amount of switching noise is introduced into the switching tube, so that the quality of output signals is influenced, and particularly, under the condition of low power supply voltage, the driving current with the output rate of more than Gbps and the current of dozens of milliamperes is difficult to ensure. Under the CMOS, the tail current source raises the source end voltage of the switch tube, and under the action of the substrate bias effect, the threshold voltage of the switch tube is raised, so that the switching rate is reduced.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the CMOS process laser driving circuit overcomes the defects of the prior art, integrates the driving current regulation and the switching signal driving together in a feedback control mode, realizes the transmission of the switching signal while finishing the driving current setting regulation of the current output stage, and effectively improves the working speed of the circuit.
The technical solution of the invention is as follows: a CMOS process laser driving circuit structurally comprises a common mode feedback circuit, wherein the common mode feedback circuit converts a differential digital voltage signal into a switching current signal for driving a laser diode, receives an externally arranged reference current signal, adjusts the level of the externally input differential digital voltage signal by adopting the principle of negative feedback, and further adjusts the magnitude of the switching current signal to be in direct proportion to the reference current signal.
The common-mode feedback circuit comprises a voltage regulation stage, a buffer driving stage, a current output stage and a voltage feedback stage;
the voltage regulating stage is used for receiving the differential digital voltage signal, comparing the reference voltage with the feedback voltage output by the voltage feedback stage, and regulating the level of the differential digital voltage signal according to the comparison result, namely, when the feedback voltage is greater than the reference voltage, increasing the level of the differential digital signal; otherwise, the level of the differential digital signal is reduced, and the adjusted differential digital voltage signal is sent to the buffer driving stage.
And buffering the driving stage, reducing the common-mode level of the adjusted differential digital voltage signal to obtain a driving differential voltage signal, wherein the low level of the driving differential voltage signal is less than the starting threshold voltage of the current output stage.
And the current output stage is used for respectively converting the positive and negative signals of the driving differential voltage signal into switching current signals, and the amplitude of the switching current signals is in direct proportion to the magnitude of the differential digital voltage signal.
And the voltage feedback stage converts the switch current signal into feedback voltage and feeds the feedback voltage back to the voltage regulation stage.
The voltage regulation stage comprises an operational amplifier OPA _1, a current driving tube M10, an NMOS tube M1, an NMOS tube M2, a resistor R7, a resistor R8 and a resistor R3.
The positive input end of the operational amplifier OPA _1 is connected with a reference voltage, the negative input end is connected with a feedback voltage, and the output end is connected with the grid electrode of the current driving tube M10; the source electrode of the current driving tube M10 is connected to the core voltage, and the drain electrode of the current driving tube M10 is connected in parallel with one end of the resistors R7 and R8; the gates of the NMOS transistors M1 and M2 are respectively connected with the positive terminal and the negative terminal of the differential digital voltage signal, the sources of the NMOS transistors M1 and M2 are grounded through a resistor R3, and the drains of the NMOS transistors M1 and M2 are respectively connected with the other ends of the resistors R7 and R8; the voltage signals of the drains of the NMOS transistors M1 and M2 are adjusted differential digital voltage signals.
The buffer driving stage comprises two followers which are formed by NMOS tubes and current sources.
The method specifically comprises the following steps: the device comprises NMOS transistors M3 and M4 and current sources I1 and I2; the NMOS tube M3 and the current source I1 form a first follower, the drain electrode of the NMOS tube M3 is connected with the core voltage, the grid electrode of the NMOS tube M3 is connected with the positive end of an output signal of the voltage regulating stage, the source electrode of the NMOS tube M is the positive end of a driving differential voltage signal, and the source electrode of the NMOS tube M is grounded through the current source I1; the NMOS transistor M4 and the current source I2 form a second follower, the drain electrode of the NMOS transistor M4 is connected with the kernel voltage, the grid electrode of the NMOS transistor M4 is connected with the negative end of an output signal of the voltage regulating stage, the source electrode of the NMOS transistor M is the negative end of a driving differential voltage signal, and the source electrode of the NMOS transistor M is grounded through the current source I2.
The current output stage comprises NMOS tubes M5 and M6;
the gates of the NMOS tubes M5 and M6 are respectively connected with the positive end and the negative end of the driving differential voltage signal, and the drain of the NMOS tube M5 is the positive end output of the switching current signal; the drain of the NMOS transistor M6 is the negative terminal output of the switch current signal, and the sources of the NMOS transistors M5 and M6 are connected in parallel to the voltage feedback stage.
The current output stage further comprises NMOS tubes M7 and M8, the grid electrode and the source electrode of the NMOS tube M7 are connected to the grid electrode of the NMOS tube M5 in common, and the drain electrode of the NMOS tube M7 is connected to the drain electrode of the NMOS tube M6; the gate and the source of the NMOS transistor M8 are commonly connected to the gate of the NMOS transistor M6, and the drain of the NMOS transistor M8 is connected to the drain of the NMOS transistor M5.
The voltage feedback stage comprises a resistor R4, one end of the resistor R4 is grounded, the other end of the resistor R4 is connected with the source electrodes of the NMOS tubes M5 and M6, and the switch current signals are converted into feedback voltage to be output.
The CMOS process laser driving circuit further comprises a negative feedback clamping circuit, the negative feedback clamping circuit comprises an operational amplifier OPA _2, an NMOS tube M9, resistors Rmodset, R5, a current source I4 and a mirror current source I3, a forward input port of the operational amplifier OPA _2 is connected with a reference level VB, an output port of the operational amplifier OPA _2 is connected with a grid electrode of a transistor M9, a source end of an NMOS tube M9 is connected to a negative end of the operational amplifier OPA _2 to form negative feedback and is connected to the ground through a modulation resistor Rmodset, a drain end of the NMOS tube M9 is connected to an IO power supply Vdd1 through a current source I4, one end of a mirror current source I3 and the current source I4 are connected to the IO power supply Vdd1 at the same time, the other end of the mirror current source I3 is grounded through a resistor R5 in a mirror relationship with the current source I4 to generate a mirror current, the mirror current flows through a resistor R5 to, the current I4 through the modulation resistor Rmodset is of magnitude Imodset.
The modulation resistor Rmodset is an adjustable resistor.
The common mode feedback circuit power voltage V3 is provided by the embedded low dropout regulator LDO.
Compared with the prior art, the invention has the technical effects that:
(1) the current regulation and the switch signal driving are integrated together through the common-mode feedback circuit, and the common-mode feedback circuit regulates the level of the differential switch signal, so that the high level of the high-speed switch signal can set and determine the magnitude of the output current while finishing the opening of a switch tube of a current regulation stage, and the driving current setting regulation of a current output stage is realized while finishing the transmission of the switch signal;
(2) the invention adopts the current output stage of the tailless current source, avoids the problem of the rising of the threshold value of the switching tube of the current output stage caused by the tailless current source, and improves the working speed of the laser driver under the CMOS process;
(3) the embedded low-voltage difference linear voltage regulator (LDO) supplies power for the current regulation stage, realizes stable high-speed switching signal level and ensures the quality of output current;
(4) the current regulation is realized by adopting a common-mode feedback circuit, the resistance value of the resistor R4 is very small, the voltage fluctuation introduced by the resistor R4 in the switching process of the switches of the driving tubes M5 and M6 can be ignored, and the accurate output of the current can be realized;
(5) according to the invention, a negative feedback clamping circuit is adopted to generate a reference current Imodset, the voltage on an effective clamping modulation resistor Rmodset is equal to VBG, the voltage on the modulation resistor Rmodset is kept unchanged when the current on the modulation resistor Rmodset is changed, and the interference on an internal circuit, which is usually introduced by the Rmodset outside the circuit, is isolated;
(6) an input Current Mode (CML) circuit (1) formed by cascading 5-stage amplifiers (Amp1, Amp2, Amp3, Amp4 and Amp5) is adopted between the input port and the common mode feedback circuit. When a signal with high speed and low swing amplitude is input, the output signal with high speed and large swing amplitude can be generated through the cascade structure of the 5-stage amplifier. By adopting the cascade structure of the 5-stage amplifier, the maximum speed of the circuit capable of processing the input signal and the minimum differential mode voltage of the input signal are improved, the rise time and the fall time of the signal are reduced, and the rate of transmitting the signal is increased.
Drawings
FIG. 1 is a CMOS process laser driver circuit of the present invention;
FIG. 2 is an Alternating Current (AC) simulation of the common mode feedback loop of the CMOS process laser driver circuit of the present invention;
FIG. 3 is a simulation waveform diagram of the laser driving circuit of CMOS process of the present invention with output speed of 1.25Gbps and current of 50 mA;
fig. 4 is a simulated waveform diagram of the modulation resistance Rmodset and the output current of the CMOS process laser driving circuit of the present invention.
Detailed Description
As shown in fig. 1, the structure of a laser driver circuit in CMOS process according to the present invention is shown, and the driver circuit is implemented based on a mixed design of 3.3V CMOS transistors and 1.8V CMOS transistors. Can be applied to optical fiber transmission communication systems. The CMOS process laser driving circuit comprises an input Current Mode (CML) circuit 1, a low voltage difference linear voltage stabilizer 2, a negative feedback clamping circuit 3 and a common mode feedback circuit 4.
1. Input Current Mode (CML) circuit
The input Current Mode (CML) circuit 1 is a five-stage amplification structure formed by cascade connection of a first amplifier Amp1, a second amplifier Amp2, a third amplifier Amp3, a fourth amplifier Amp4 and a fifth amplifier Amp5, the input end of the first amplifier Amp1 is the input end of the input Current Mode (CML) circuit 1 for receiving externally input differential voltage signals, the second amplifier Amp2 also receives externally input enable control signals an and ap for controlling whether to input Current Mode (CML) circuit output signals, the output end of the fifth amplifier Amp5 is the output end of a Current Mode (CML) circuit for amplifying and conditioning differential voltage signals INP and INN after burst mode control signals are received, the differential voltage signals INP and INN are connected with the gates of differential input tubes M1 and M2 in the common mode feedback circuit 3, the drain ends of the differential input tubes M1 and M2 are controlled to generate differential output voltages, and the output driving tube driving drive through a buffer driving stage M5, M6 generates a modulated current.
Since the level range of the laser driver differential input signal is usually larger than the circuit core voltage, the amplifiers Amp1, Amp2 are powered by the 3.3V IO voltage Vdd 1; the power supplies for the amplifiers Amp3, Amp4, Amp5 are powered by a 1.8V core voltage Vdd 2.
2. Low dropout regulator (LDO) circuit
The low-voltage difference linear regulator (LDO) circuit 2 is embedded in the CMOS process laser driving circuit and used for generating a common mode feedback circuit 4 power supply V3 according to the power supply voltage 3.3V.
3. Common mode feedback circuit
The common mode feedback circuit 4 converts the differential digital voltage signal output by the input Current Mode (CML) circuit 4 into a switching current signal for driving the laser diode, and meanwhile, receives an externally set reference current signal, and adjusts the level of the externally input differential digital voltage signal by adopting a negative feedback principle, thereby adjusting the magnitude of the switching current signal to be in direct proportion to the reference current signal.
As shown in fig. 1, the common mode feedback circuit 4 includes a voltage regulation stage, a buffer driving stage, a current output stage, and a voltage feedback stage.
The voltage regulating stage is used for receiving the differential digital voltage signal, comparing the reference voltage with the feedback voltage output by the voltage feedback stage, and regulating the level of the differential digital voltage signal according to the comparison result, namely, when the feedback voltage is greater than the reference voltage, increasing the level of the differential digital signal; otherwise, the level of the differential digital signal is reduced, and the adjusted differential digital voltage signal is sent to the buffer driving stage. The voltage regulation stage comprises an operational amplifier OPA _1, a current driving tube M10, an NMOS tube M1, an NMOS tube M2, a resistor R7, a resistor R8 and a resistor R3; the positive input end of the operational amplifier OPA _1 is connected with a reference voltage, the negative input end is connected with a feedback voltage, and the output end is connected with the grid electrode of the current driving tube M10; the source electrode of the current driving tube M10 is connected to the core voltage, and the drain electrode of the current driving tube M10 is connected in parallel with one end of the resistors R7 and R8; the gates of the NMOS transistors M1 and M2 are respectively connected with the positive terminal and the negative terminal of the differential digital voltage signal, the sources of the NMOS transistors M1 and M2 are grounded through a resistor R3, and the drains of the NMOS transistors M1 and M2 are respectively connected with the other ends of the resistors R7 and R8; the voltage signals of the drains of the NMOS transistors M1 and M2 are adjusted differential digital voltage signals. The NMOS transistors M1, M2, and the resistors R7, R8 constitute an input differential amplifier.
And buffering the driving stage, reducing the common-mode level of the adjusted differential digital voltage signal to obtain a driving differential voltage signal, wherein the low level of the driving differential voltage signal is less than the starting threshold voltage of the current output stage. The buffer driving stage comprises two followers which are composed of NMOS tubes and current sources. The method comprises the following steps: the buffer driving stage comprises NMOS transistors M3 and M4 and current sources I1 and I2; the NMOS tube M3 and the current source I1 form a first follower, the drain electrode of the NMOS tube M3 is connected with the core voltage, the grid electrode of the NMOS tube M3 is connected with the positive end of an output signal of the voltage regulating stage, the source electrode of the NMOS tube M is the positive end of a driving differential voltage signal, and the source electrode of the NMOS tube M is grounded through the current source I1; the NMOS transistor M4 and the current source I2 form a second follower, the drain electrode of the NMOS transistor M4 is connected with the kernel voltage, the grid electrode of the NMOS transistor M4 is connected with the negative end of an output signal of the voltage regulating stage, the source electrode of the NMOS transistor M is the negative end of a driving differential voltage signal, and the source electrode of the NMOS transistor M is grounded through the current source I2.
And the current output stage is used for respectively converting the positive and negative signals of the driving differential voltage signal into switching current signals, and the amplitude of the switching current signals is in direct proportion to the magnitude of the differential digital voltage signal. The current output stage comprises NMOS tubes M5, M6, M7 and M8. The gates of the NMOS tubes M5 and M6 are respectively connected with the positive end and the negative end of the driving differential voltage signal, and the drain of the NMOS tube M5 is the positive end output of the switching current signal; the drain electrode of the NMOS tube M6 is the negative end output of the switch current signal, and the source electrodes of the NMOS tubes M5 and M6 are connected in parallel to the voltage feedback stage; the grid electrode and the source electrode of the NMOS tube M7 are connected to the grid electrode of the NMOS tube M5 in common, and the drain electrode of the NMOS tube M7 is connected to the drain electrode of the NMOS tube M6; the gate and the source of the NMOS transistor M8 are commonly connected to the gate of the NMOS transistor M6, and the drain of the NMOS transistor M8 is connected to the drain of the NMOS transistor M5.
And the voltage feedback stage converts the switch current signal into feedback voltage and feeds the feedback voltage back to the voltage regulation stage. The voltage feedback stage comprises a resistor R4, one end of the resistor R4 is grounded, the other end of the resistor R4 is connected with the source electrodes of NMOS tubes M5 and M6 in common, and switching current signals are converted into feedback voltage to be output.
4. Negative feedback clamping circuit
The negative feedback clamp circuit 3 comprises an operational amplifier OPA _2, an NMOS tube M9, a resistor Rmodset, R5, R6, a current source I4 and a mirror current source I3, wherein a forward input port of the operational amplifier OPA _2 is connected with a reference level VB, an output port of the operational amplifier OPA _2 is connected with a grid electrode of a transistor M9, a source end of the NMOS tube M9 is connected with a negative end of the operational amplifier OPA _2 to form negative feedback and is connected to the ground through a modulation resistor Rmodset, a drain end of the NMOS tube M9 is connected to a power supply voltage Vdd1 through the current source I4, one end of the mirror current source I3 is connected to the power supply voltage simultaneously with the current source I4, the other end of the mirror current source I3 is connected to the ground through the resistor R5 in a mirror relationship with the current source I4 to generate a. Due to the negative feedback effect, the voltage on the modulation resistor (Rmodset) is equal to the voltage VB, and the current I4 on the modulation resistor Rmodset is equal to Imodset.
The working principle of the circuit is as follows:
the negative feedback clamp circuit 3 generates a current I4 with the magnitude Imodset by setting a modulation resistor Rmodset, and the current I3 is generated by mirror copying the current I4. The common mode feedback circuit 4 compares the voltage V1 generated by the output current on the resistor R4 with the voltage V2 of the current I3 on the resistor R5 to adjust the current of the current driving tube M10, thereby adjusting the drain voltage of the current driving tube M10, and then adjusting the gate control voltage of the output driving tubes M5 and M6 through the differential input tubes M1 and M2 and the follower to achieve the required current.
When the voltage V1 across the resistor R4 is greater than the voltage V2 across the resistor R5, the output voltage of the operational amplifier OPA _1 increases, so that the gate-source voltage | Vgs | of the current driving tube M10 decreases, the drain-source voltage | Vds | increases, the voltage at the point C in the common mode feedback circuit 4 decreases, the voltage at the gate terminal of the output driving tube M5, M6 decreases through the input differential tube M1, M2, the load resistor R7, R8 and the buffer driving stage control, the output current decreases, so that the voltage V1 across the resistor R4 decreases, and the voltage at the point C in the common mode feedback circuit 4 does not change until the voltage V1 and the voltage V2 are equal. When the voltage V1 across the resistor R4 is smaller than the voltage V2 across the resistor R5, the output voltage of the operational amplifier OPA _1 decreases, so that the gate-source voltage | Vgs | of the current driving tube M10 increases, the drain-source voltage | Vds | decreases, the voltage at point C in the common mode feedback circuit 4 increases, the voltage at the gate of the output driving tubes M5 and M6 is controlled to increase through the input differential tubes M1 and M2, the load resistors R7 and R8 and the buffer driving stages M3, M4, I1 and I2, the output current is increased, so that the voltage V1 across the resistor R4 increases until the voltage V1 and the voltage V2 are equal.
For example: the positive input terminal of the operational amplifier OPA _1 is connected to the NMOSThe modulation current generated by the resistor R4 and R4 actually generated by the transistors M5 and M6 with the source electrodes connected is ImodIf the voltage V1 generated on the resistor R4 is Imod×R4The negative input terminal of the operational amplifier is connected to the resistor R5, the other terminal of the resistor R5 is connected to ground, and the connected terminal of the resistor R5 is injected with a voltage of K × I through the current source I3modsetVoltage V2 ═ K × Imodset×R5. The voltages V1 and V2 across the operational amplifier OPA _1 are compared by the negative feedback formed by the operational amplifier OPA _1 and the current driving tube M10. When the differential input voltage V1 of the operational amplifier OPA _1 is not equal to V2, the operational amplifier OPA _1 will adjust the gate (point a) control voltage of the NMOS transistor M10, so that the current of the NMOS transistor M10 changes, thereby affecting the common mode level change of the drain (point C) of the NMOS transistor M10. The change of the drain (point C) potential of the current driving transistor M10 controls the gate voltage of the NMOS transistors M5, M6 through the buffer driving stage NMOS transistors M3, M4 to adjust the output modulation current ImodUntil the voltage V1 of the resistor R4 connected with the NMOS transistors M5 and M6 is equal to the voltage V2 of the resistor R5, the voltage of the drain terminal (point C) of the NMOS transistor M10 does not change any more, and the output driving current I generated by the NMOS transistors M5 and M6modWill no longer change and will have a size of Imod＝K×Imodset×R5/R4。
As shown in fig. 2, which is a result of ac simulation in the common mode feedback circuit (4) in the CMOS process laser driving circuit of the present invention, the power supply voltage is 3.3V. It can be seen from the simulation waveform 2 that when the loop gain is reduced to 0dB, the phase margin of the common mode feedback loop is 80.81 degrees, which can meet the stability requirement of the system. In the common mode feedback circuit (4), in order to meet the output current capacity of dozens of mA, a transistor of a current driving tube (M10) has a large parasitic capacitance Cgd which can be equivalent to the effect of a Miller capacitance, and a first main pole and a second main pole are separated, so that the system is stable.
Fig. 3 shows a transient simulation result of the CMOS process laser driving circuit of the present invention. The transmission rate of the input signal is 1.25Gbps and the speed of the burst control signal is 50 MHz. From the simulation results in the figure, it can be seen that when the signal is input at 1.25Gbps, 50mA of current can be output, and the turn-off current can be guaranteed to be 0mA, and the circuit is guaranteed not to leak electricity. Because parasitic inductance to a power supply and a ground is added in the simulation process, and a package parasitic parameter model (RCL) is added in an output driving port, the output current has certain overshoot and undershoot.
As shown in fig. 4, as a result of the dc simulation of the CMOS process laser driving circuit of the present invention, the value of the voltage (V1) across the resistor (R4) in the common mode feedback circuit is changed by adjusting the magnitude of the modulation resistor Rmodset, the dc operating point of the C point in the common mode feedback circuit 4 is adjusted, and the gate voltages of the output driving transistors M5 and M6 are adjusted to change the magnitude of the output current after passing through the input differential amplifiers (M1, M2, R7, R8) and the buffer driving stages (M3, M4, I1, I2). From the simulation result of fig. 4, it can be seen that when the modulation resistance Rmodset is adjusted from 0K to 100K and the current flowing through the diode d0 is 157.73uA, the output current of the diode d1 is 50.33 mA. When the maximum current output by the diode d1 reaches 50mA, the diode d0 can be well turned off.
The invention has a point to pay attention to:
as shown in fig. 4, in the common mode feedback circuit 4, when the output current exceeds 50mA, the gate terminal (point C) voltage of the current driving tube M10 in the common mode feedback circuit 4 is raised, after passing through the differential input and follower, the gate terminal differential voltage of the control output driving tubes M5 and M6 is also raised, and when the gate terminal voltage of the control output driving tubes M5 and M6 exceeds the threshold voltage of the output driving tubes M5 and M6, the leakage of the output driving tubes M5 and M6 is caused. However, when the output driving current is controlled within 50mA, the maximum leakage current is only 157.73uA, which can be ignored.
Those skilled in the art will appreciate that those matters not described in detail in this specification are well known in the art.
Claims (9)
1. A CMOS process laser driving circuit is characterized in that: the laser diode level adjusting circuit comprises a common mode feedback circuit (4), wherein the common mode feedback circuit (4) converts a differential digital voltage signal into a switching current signal for driving a laser diode, receives an externally arranged reference current signal, adjusts the level of the externally input differential digital voltage signal by adopting a negative feedback principle, and further adjusts the magnitude of the switching current signal to be in direct proportion to the reference current signal;
the common-mode feedback circuit (4) comprises a voltage regulation stage, a buffer driving stage, a current output stage and a voltage feedback stage;
the voltage regulating stage is used for receiving the differential digital voltage signal, comparing the reference voltage with the feedback voltage output by the voltage feedback stage, and regulating the level of the differential digital voltage signal according to the comparison result, namely, when the feedback voltage is greater than the reference voltage, increasing the level of the differential digital signal; otherwise, reducing the level of the differential digital signal, and sending the regulated differential digital voltage signal to a buffer driving stage;
buffering the driving stage, reducing the common-mode level of the adjusted differential digital voltage signal to obtain a driving differential voltage signal, wherein the low level of the driving differential voltage signal is less than the starting threshold voltage of the current output stage;
the current output stage is used for respectively converting the positive and negative signals of the driving differential voltage signal into switching current signals, and the amplitude of the switching current signals is in direct proportion to the magnitude of the differential digital voltage signal;
and the voltage feedback stage converts the switch current signal into feedback voltage and feeds the feedback voltage back to the voltage regulation stage.
2. The CMOS process laser driver circuit of claim 1, wherein: the voltage regulation stage comprises an operational amplifier OPA _1, a current driving tube M10, an NMOS tube M1, an NMOS tube M2, a resistor R7, a resistor R8 and a resistor R3;
the positive input end of the operational amplifier OPA _1 is connected with a reference voltage, the negative input end is connected with a feedback voltage, and the output end is connected with the grid electrode of the current driving tube M10; the source electrode of the current driving tube M10 is connected to the core voltage, and the drain electrode of the current driving tube M10 is connected in parallel with one end of the resistors R7 and R8; the gates of the NMOS transistors M1 and M2 are respectively connected with the positive terminal and the negative terminal of the differential digital voltage signal, the sources of the NMOS transistors M1 and M2 are grounded through a resistor R3, and the drains of the NMOS transistors M1 and M2 are respectively connected with the other ends of the resistors R7 and R8; the voltage signals of the drains of the NMOS transistors M1 and M2 are adjusted differential digital voltage signals.
3. The CMOS process laser driver circuit of claim 1, wherein: the buffer driving stage comprises two followers formed by NMOS tubes and current sources; the method specifically comprises the following steps: the buffer driving stage comprises NMOS transistors M3 and M4 and current sources I1 and I2; the NMOS tube M3 and the current source I1 form a first follower, the drain electrode of the NMOS tube M3 is connected with the core voltage, the grid electrode of the NMOS tube M3 is connected with the positive end of an output signal of the voltage regulating stage, the source electrode of the NMOS tube M is the positive end of a driving differential voltage signal, and the source electrode of the NMOS tube M is grounded through the current source I1; the NMOS transistor M4 and the current source I2 form a second follower, the drain electrode of the NMOS transistor M4 is connected with the kernel voltage, the grid electrode of the NMOS transistor M4 is connected with the negative end of an output signal of the voltage regulating stage, the source electrode of the NMOS transistor M is the negative end of a driving differential voltage signal, and the source electrode of the NMOS transistor M is grounded through the current source I2.
4. The CMOS process laser driver circuit of claim 1, wherein: the current output stage comprises NMOS tubes M5 and M6;
the gates of the NMOS tubes M5 and M6 are respectively connected with the positive end and the negative end of the driving differential voltage signal, and the drain of the NMOS tube M5 is the positive end output of the switching current signal; the drain of the NMOS transistor M6 is the negative terminal output of the switch current signal, and the sources of the NMOS transistors M5 and M6 are connected in parallel to the voltage feedback stage.
5. The CMOS process laser driver circuit of claim 4, wherein: the current output stage further comprises NMOS tubes M7 and M8, the grid electrode and the source electrode of the NMOS tube M7 are connected to the grid electrode of the NMOS tube M5 in common, and the drain electrode of the NMOS tube M7 is connected to the drain electrode of the NMOS tube M6; the gate and the source of the NMOS transistor M8 are commonly connected to the gate of the NMOS transistor M6, and the drain of the NMOS transistor M8 is connected to the drain of the NMOS transistor M5.
6. The CMOS process laser driver circuit of claim 1, wherein: the voltage feedback stage comprises a resistor R4, one end of the resistor R4 is grounded, the other end of the resistor R4 is connected with the source electrodes of the NMOS tubes M5 and M6, and the switch current signals are converted into feedback voltage to be output.
7. The CMOS process laser driver circuit of claim 1, wherein: the negative feedback clamping circuit (3) comprises an operational amplifier OPA _2, an NMOS tube M9, resistors Rmodset, R5, a current source I4 and a mirror current source I3, wherein a forward input port of the operational amplifier OPA _2 is connected with a reference level VB, an output port of the operational amplifier OPA _2 is connected with a grid electrode of a transistor M9, a source end of an NMOS tube M9 is connected with a negative end of the operational amplifier OPA _2 to form negative feedback and is connected to the ground through a modulation resistor Rmodset, a drain end of an NMOS tube M9 is connected with an IO power supply Vdd1 through a current source I4, one end of a mirror current source I3 and the current source I4 are connected to an IO power supply Vdd1 at the same time, the other end of the mirror current source I3 is connected to the ground through the resistor R5 in a mirror relationship with the current source I4 to generate a mirror current, the mirror current flows through a resistor R5 to generate a reference voltage, and the voltage on, the current I4 through the modulation resistor Rmodset is of magnitude Imodset.
8. The CMOS process laser driver circuit of claim 7, wherein: the modulation resistor Rmodset is an adjustable resistor.
9. The CMOS process laser driver circuit of claim 1, wherein: the power voltage V3 of the common mode feedback circuit (4) is provided by the embedded low-voltage difference linear regulator LDO (2).
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| CN110677151A (en) * | 2019-09-25 | 2020-01-10 | 芯创智（北京）微电子有限公司 | High-speed LVDS drive circuit without common-mode feedback loop |
| CN112688161B (en) * | 2020-12-23 | 2021-10-22 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Driving current source of narrow-linewidth semiconductor laser for cold atom gyroscope |
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| WO1997005696A1 (en) * | 1995-08-01 | 1997-02-13 | Information Storage Devices, Inc. | Fully differential output cmos power amplifier |
| CN101595635A (en) * | 2006-03-10 | 2009-12-02 | 爱萨有限公司 | Utilization input common-mode feedback is removed the dummy detector in the optical detector |
| CN204481788U (en) * | 2015-04-07 | 2015-07-15 | 电子科技大学 | A kind of LVDS drive circuit suppressing output common mode to fluctuate |
| CN204517766U (en) * | 2015-04-03 | 2015-07-29 | 成都振芯科技股份有限公司 | A kind of high-gain common mode feedback loop being applied to high impedance current source load differential mode amplification circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7906994B2 (en) * | 2009-02-24 | 2011-03-15 | Standard Microsystems Corporation | Fast common mode feedback control for differential driver |
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| WO1997005696A1 (en) * | 1995-08-01 | 1997-02-13 | Information Storage Devices, Inc. | Fully differential output cmos power amplifier |
| CN101595635A (en) * | 2006-03-10 | 2009-12-02 | 爱萨有限公司 | Utilization input common-mode feedback is removed the dummy detector in the optical detector |
| CN204517766U (en) * | 2015-04-03 | 2015-07-29 | 成都振芯科技股份有限公司 | A kind of high-gain common mode feedback loop being applied to high impedance current source load differential mode amplification circuit |
| CN204481788U (en) * | 2015-04-07 | 2015-07-15 | 电子科技大学 | A kind of LVDS drive circuit suppressing output common mode to fluctuate |
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