CN110676224A - Amplifier chip packaging structure and manufacturing method - Google Patents
Amplifier chip packaging structure and manufacturing method Download PDFInfo
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- CN110676224A CN110676224A CN201911101359.7A CN201911101359A CN110676224A CN 110676224 A CN110676224 A CN 110676224A CN 201911101359 A CN201911101359 A CN 201911101359A CN 110676224 A CN110676224 A CN 110676224A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 119
- 239000002184 metal Substances 0.000 claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000007789 sealing Methods 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 194
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 27
- 229910052802 copper Inorganic materials 0.000 claims description 27
- 239000010949 copper Substances 0.000 claims description 27
- 238000010438 heat treatment Methods 0.000 claims description 10
- 238000007747 plating Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 239000012790 adhesive layer Substances 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 22
- 239000004033 plastic Substances 0.000 abstract description 13
- 229920003023 plastic Polymers 0.000 abstract description 13
- 239000005022 packaging material Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 12
- 230000017525 heat dissipation Effects 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 238000001746 injection moulding Methods 0.000 description 5
- 238000012858 packaging process Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000000465 moulding Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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Abstract
The invention provides an amplifier chip packaging structure and a manufacturing method thereof, relating to the technical field of chip packaging, wherein the amplifier chip packaging structure comprises a chip, a packaging substrate and a sealing cover; the packaging substrate is provided with at least two layers of dielectric layers, a groove is formed in the top layer of the dielectric layer, a top metal layer, a middle metal layer and a bottom metal layer are arranged on the packaging substrate, and the sealing cover is arranged on the packaging substrate. The amplifier chip packaging structure provided by the invention realizes multilayer wiring, the chip is arranged in the groove, the connection length between the chip and the top metal layer of the packaging substrate is effectively shortened, the transmission capability between the chip and the top metal layer is improved, the loss of radio frequency transmission is reduced, the sealing cover with the inner cavity enables an air layer with low dielectric loss to be arranged above the chip, the dielectric loss caused by the fact that the traditional packaging chip needs to be in direct contact with a plastic packaging material is avoided, and the performance loss of a millimeter wave band caused by the packaging structure is effectively reduced.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to an amplifier chip packaging structure and a method for manufacturing the same.
Background
With the utilization and development of spectrum resources in the radio frequency band, the operating frequencies of various communication systems have been expanded from lower frequency bands to the millimeter wave band. The millimeter wave frequency band has the advantages of short wavelength, wide frequency band, large information capacity and the like, and the millimeter wave communication technology is widely applied to the fields of mobile communication, radar detection, electronic countermeasure, accurate guidance and the like. The millimeter wave amplifier can amplify microwave signals in a millimeter wave frequency band, and is a key device of a 5G communication receiving and transmitting system. The amplifier chip in the millimeter wave frequency band is generally designed by adopting a monolithic microwave integrated circuit, and has the advantages of good microwave performance and high integration level.
At present, the microwave radio frequency chip mostly adopts a plastic package packaging process. However, the conventional plastic package chip adopts a solid injection molding packaging process, which comprises the steps of firstly manufacturing a metal packaging carrier frame, then bonding a chip on the frame, bonding the chip to a packaging pin, completing chip injection molding through an injection molding machine, and finally forming a final packaging product through a cutting process. The packaging structure is only suitable for packaging chips with frequency bands lower than 10GHz, and for 5G millimeter wave frequency band amplifiers with frequency bands higher than 20GHz, the problems of overlarge parasitic loss and poor use performance exist, and normal use of the chips cannot be guaranteed.
The packaging process for the millimeter wave chip also adopts a ceramic tube shell packaging process for partial productsWith inorganic AL2O3The chip packaging process is that a chip is loaded into the tube shell and then sealed by gold-tin solder or high temperature resistant glue. Its advantages are less loss, high heat dissipation, high resistance to high temp and air tightness, high cost and large size. The method is mainly applied to military industry and is difficult to be used commercially.
Disclosure of Invention
The invention aims to provide an amplifier chip packaging structure and a method for manufacturing the same, and aims to solve the technical problems that a plastic packaging structure in the prior art easily causes overlarge loss and poor use performance of a millimeter wave amplifier.
In order to achieve the purpose, the invention adopts the technical scheme that: an amplifier chip packaging structure is provided, which comprises a chip, a packaging substrate and a sealing cover; the outer periphery of the upper surface of the chip is provided with a plurality of metal pressure points, wherein at least two metal pressure points are chip radio frequency ports; the packaging substrate is provided with at least two layers of medium layers which are stacked from bottom to top, the medium layer positioned on the top layer is provided with a groove with an upward opening and used for accommodating a chip, the bottom surface of the groove is provided with a conducting layer, the top surface of the medium layer is provided with a plurality of top metal layers which are positioned on the periphery of the chip and respectively correspond to a plurality of metal pressure points one by one, a middle metal layer which corresponds to the top metal layers one by one is arranged between every two adjacent layers of medium layers, the bottom surface of the medium layer positioned on the bottom layer is provided with a bottom metal layer which corresponds to the middle metal layers one by one and corresponds to the conducting layer one by one, a sealing cover.
As another embodiment of the present application, the top metal layers corresponding to the chip rf ports are respectively first rf ports, the chip rf ports are connected to the first rf ports in a one-to-one correspondence manner, and the bottom metal layers corresponding to the first rf ports are respectively provided with second rf ports.
As another embodiment of the present application, the package substrate is provided with a plurality of copper bars located below the conductive layer, the copper bars extend to the bottom metal layer located below the groove, and the top of the copper bars is communicated with the conductive layer.
As another embodiment of the present application, the groove penetrates through the top dielectric layer, and the conductive layer is flush with the middle metal layer.
As another embodiment of the present application, the chip rf port is connected to the first rf port through a bonding wire; and a plating layer used for bonding with the bonding wire is arranged on the first radio frequency port.
As another embodiment of the present application, two bonding wires are provided, and the bonding wires are connected to the chip and the first rf port by wedge bonding or ball bonding, respectively.
As another embodiment of the application, the edge of the bottom surface of the sealing cover is provided with an adhesive layer used for being bonded with the periphery of the packaging substrate, and the chip and the groove are bonded by adopting conductive adhesive.
As another embodiment of the present application, the top surface of the chip is flush with the top surface of the package substrate, and a distance between two side surfaces of the chip adjacent to the first RF port and the side surface of the groove has a value of 50-200 μm.
As another embodiment of the present application, a second rf port is disposed on the bottom metal layer corresponding to the first rf port up and down, and the second rf port is connected to the first rf port through a metalized through hole.
A method of making an amplifier chip package structure, comprising the steps of:
manufacturing a packaging substrate, laminating a top metal layer, a dielectric layer, a middle metal layer, a dielectric layer and a bottom metal layer, forming a groove on the dielectric layer positioned at the top, and forming a conductive layer in the groove;
bonding the chip to the packaging substrate, placing the packaging substrate on a bonding table, bonding the chip to the groove, and drying the chip and the packaging substrate until the bonding glue is cured;
bonding the chip radio frequency ports to the corresponding first radio frequency ports respectively, placing the chip and the packaging substrate on a bonding table, heating the chip and the packaging substrate, and connecting the chip radio frequency ports to the corresponding first radio frequency ports respectively;
mounting a sealing cover, and heating the packaging substrate to 125 ℃; and fixing the sealing cover on the packaging substrate, heating and keeping the sealing cover, and then naturally cooling.
The amplifier chip packaging structure provided by the invention has the beneficial effects that: compared with the prior art, the amplifier chip packaging structure provided by the invention adopts a form that the top metal layer, the bottom metal layer, the middle metal layer and the plurality of medium layers are combined, multilayer wiring can be realized, the chip is arranged in the groove, the connection length between the chip and the top metal layer of the packaging substrate is effectively shortened, the parasitic inductance of the bonding wire is reduced, the transmission capability of radio frequency signals between the chip and the packaging substrate is improved, the radio frequency performance of the chip is ensured to the maximum extent, the sealing cover with the inner cavity enables an air layer with low dielectric loss to be arranged above the chip, and the dielectric loss factor of air is far smaller than that of common plastic packaging materials, so that the dielectric loss caused by the fact that the traditional packaging chip needs to be directly contacted with the plastic packaging materials is avoided, and the performance loss of millimeter wave bands caused by the packaging.
According to the method for manufacturing the amplifier chip packaging structure, the molding mode that the top metal layer, the bottom metal layer, the middle metal layer and the plurality of medium layers are combined is adopted, the packaging structure manufactured by the mode can effectively improve the manufacturing efficiency, and the packaging cost of the chip can be effectively reduced. In addition, the sealing cover with the inner cavity is structurally sealed by bonding with the packaging substrate, and compared with the traditional injection molding type plastic package, the sealing cover is simple and convenient to bond and effectively reduces the loss of a high-frequency wave band. The packaging substrate is provided with the groove for mounting the chip, so that the length of the bonding wire is convenient to shorten, the distance between the chip and the bottom surface of the packaging substrate is effectively shortened, the heat dissipation path of the chip is shortened, the heat dissipation efficiency is increased, and the stable work of the chip is facilitated.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic front cross-sectional view illustrating an amplifier chip package structure according to a first embodiment of the present invention;
FIG. 2 is a schematic top view of the package substrate of FIG. 1;
FIG. 3 is a schematic cross-sectional view of A-A in FIG. 2;
fig. 4 is a schematic cross-sectional front view illustrating a second amplifier chip package structure according to an embodiment of the present invention;
fig. 5 is a schematic sectional structure view of B-B in fig. 4.
Wherein, in the figures, the respective reference numerals:
100. a chip; 110. pressing points of metal; 111. a chip radio frequency port; 112. a chip DC port; 120. bonding wires; 200. a package substrate; 210. a dielectric layer; 220. a bottom metal layer; 221. a second radio frequency port; 222. a second DC port; 230. an intermediate metal layer; 240. a top metal layer; 241. a first radio frequency port; 242. a first DC port; 250. a groove; 251. a conductive layer; 260. a copper bar; 270. metallizing the through-hole; 300. sealing the cover; 310. an inner cavity.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 to 5, the amplifier chip package and the method for fabricating the same according to the present invention will be described. The amplifier chip packaging structure comprises a chip 100, a packaging substrate 200 and a sealing cover 300; a plurality of metal pressure points 110 are arranged on the outer periphery of the upper surface of the chip 100, wherein at least two metal pressure points 110 are chip radio frequency ports 111; the package substrate 200 is provided with at least two layers of dielectric layers 210 stacked from bottom to top, a groove 250 with an upward opening and used for accommodating the chip 100 is arranged on the dielectric layer 210 on the top layer, a conductive layer 251 is arranged on the bottom surface of the groove 250, top metal layers 240 which are arranged on the periphery of the chip 100 and respectively correspond to the plurality of metal pressure points 110 one by one are arranged on the top surface of the dielectric layer 210, middle metal layers 230 which correspond to the top metal layers 240 one by one are arranged between the two adjacent layers of dielectric layers 210, bottom metal layers 220 which correspond to the middle metal layers 230 one by one up and down and correspond to the conductive layer 251 up and down are arranged on the bottom surface of the dielectric layer 210 on the bottom layer, a sealing cover 300 is arranged on the package substrate 200 and used.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or be indirectly on the other element. It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "top," "bottom," "inner," "outer," and the like are used in the orientations and positional relationships indicated in the drawings and are used merely for convenience in describing and simplifying the present invention, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and thus are not to be considered limiting of the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
Compared with the prior art, the amplifier chip packaging structure provided by the invention adopts a form of combining the top metal layer 240, the bottom metal layer 220, the middle metal layer 230 and at least two dielectric layers 210, can realize multilayer wiring, effectively meets the requirements of radio frequency wiring and power supply wiring, arranges the chip 100 in the groove 250 of the packaging substrate 200, effectively shortens the connection length between the chip 100 and the top metal layer 240, improves the transmission capability between the chip 100 and the top metal layer 240, reduces the loss of radio frequency transmission, and furthest ensures the self performance of the chip 100. The manner of mounting the chip 100 by providing the groove 250 on the package substrate 200 also effectively shortens the distance between the chip 100 and the bottom surface of the package substrate 200, shortens the heat dissipation path of the chip 100, increases the heat dissipation efficiency, and contributes to stable operation of the chip 100. The sealing cover 300 with the inner cavity 310 is connected with the top surface of the packaging substrate 200 through the bottom surface of the periphery, so that a gap is formed between the chip 100 which is flush with the top surface of the packaging substrate 200 and the inner cavity 310 of the sealing cover 300, the chip 100 is isolated from the sealing cover 300 through air with a certain thickness above the chip 100, and the metal pressure point 110 is in direct contact with air, the loss caused by the fact that the traditional packaging needs to be in contact with electrolyte is avoided, and the loss of a high-frequency wave band is effectively reduced.
In this embodiment, the dielectric layer 210 is made of a resin material with a low dielectric loss factor, so that the loss can be effectively reduced, and the millimeter wave amplifier chip is suitable for a high-frequency millimeter wave amplifier chip. The mounting mode that the chip 100 is bonded in the groove 250 is simple and convenient to operate, the connection length between the chip 100 and the top metal layer 240 is effectively shortened, and the loss of radio frequency transmission is reduced conveniently. The sealing cover 300 is made of high-temperature-resistant plastic, the lower portion of the sealing cover is provided with the inner cavity 310 with the downward opening, dielectric loss of millimeter wave frequency wave bands is effectively reduced, structural sealing is achieved through bonding with the packaging substrate 200, and compared with a traditional injection molding type plastic package, bonding operation is very simple and convenient. The structure is suitable for GaN millimeter wave amplifier chips or GaAs millimeter wave amplifier chips.
According to the processing requirements and practical application, the thicknesses of the top metal layer 240, the bottom metal layer 220 and the middle metal layer 230 are 18um to 30um, and the thickness of the dielectric layer 210 is 60um to 100 um.
The top metal layer 240 serves as a radio frequency trace and a power feed layer, the middle metal layer 230 serves as a ground layer and a trace layer, and the bottom metal layer 220 serves as a pad layer and is welded to a PCB pad. The combination of two dielectric layers 210 and one intermediate metal layer 230 can meet the requirements of radio frequency wiring and power supply wiring.
By adopting the packaging structure, two layers of dielectric layers 210 or three layers of dielectric layers 210 can be selected according to the number of radio frequency wiring and power supply wiring of the chip 100 and the wiring crossing condition, a top metal layer 240, a bottom metal layer 220 and a middle metal layer 230 need to be arranged corresponding to the two layers of dielectric layers 210, a top metal layer 240, a bottom metal layer 220 and two middle metal layers 230 need to be arranged corresponding to the three layers of dielectric layers 210, the arrangement of the middle metal layer 230 is more convenient for the radio frequency wiring and the power supply wiring of the chip 100, and the applicability of the packaging structure is improved. The top metal layer 240, the dielectric layer 210, the middle metal layer 230, the bottom metal layer 220 and the dielectric layer 210 are arranged in a stacked manner, so that a complicated process of customizing a special plastic package frame in a plastic package process is omitted, meanwhile, the mounting precision of the chip 100 is ensured more easily by arranging the groove 250 in the dielectric layer 210, and meanwhile, multilayer wiring and reduction of loss of a high-frequency waveband are facilitated.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to fig. 5, the top metal layer 240 corresponding to the chip rf port 111 is a first rf port 241, the chip rf port 111 is connected to the first rf port 241, and two bottom metal layers 220 are respectively provided with second rf ports 221 corresponding to the first rf port 241. In this embodiment, the metal pressure points 110 except the chip rf port 111 are the chip dc ports 112, the top metal layers 240 corresponding to the chip dc ports 112 are the first dc ports 242, the bottom metal layers 220 corresponding to the chip dc ports 112 are the second dc ports 222, the chip dc ports 112 are connected to the first dc ports 242, and the first dc ports 242 and the second dc ports 222 may be connected through the metalized through holes 270 or other methods.
Further, the chip rf ports 111 may be provided in two, three or four forms, which are provided in at least two forms, and the corresponding first rf ports 241 and second rf ports 221 are also provided in the form of the same number as the chip rf ports 111.
As an embodiment of the invention, referring to fig. 4 to 5, a plurality of copper bars 260 are disposed on the package substrate 200 below the groove 250 and extending to the bottom surface of the package substrate 200, and the top of the copper bars 260 are connected to the conductive layer 251. Because the copper material is the material that the heat conductivility is good, the setting of copper bar 260 can realize thermal quick derivation, and copper bar 260 can also set up the copper post that is located recess 250 below, and the main shaft of copper post sets up along upper and lower direction, and the top and the conducting layer 251 intercommunication of copper post, bottom extend to bottom metal level 220 on, can realize same heat conduction function. The length direction of the copper bar 260 is perpendicular to the up-down direction, and may be set in a form parallel to the transmission direction of the radio frequency signal, may also be set in a form perpendicular to the transmission direction of the radio frequency signal, and may also be set at a certain angle with the radio frequency signal. The rf signal transmission direction refers to a direction in which the two first rf ports 241 on the top surface of the package substrate 200 are wired.
Further, the width of the copper bar 260 is 100-300 um, the ratio of the width of the copper bar 260 to the distance between two adjacent copper bars 260 is 5: 1-2: 1, and the parameter range can ensure good heat transfer performance.
Referring to fig. 1 and 4, as a specific implementation manner of the embodiment of the present invention, the recess 250 penetrates through the top dielectric layer 210, and the conductive layer 251 is flush with the middle metal layer 230. In the embodiment, the thickness of the top dielectric layer 210 is set according to the thickness of the chip 100, and the top dielectric layer 210 is arranged in a penetrating manner, so that the bottom of the groove 250 is just flush with the middle metal layer 230 and is located between the two dielectric layers 210.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 2 to fig. 3, the chip rf port 111 is connected to the first rf port 241 through the bonding wire 120. The first rf port 241 is provided with a plating layer for bonding with the bonding wire 120, and the plating layer is made of ni-pd-au. Two bonding wires 120 are provided, and the bonding wires 120 are connected to the chip 100 and the first rf port 241 by wedge bonding or ball bonding, respectively. The bonding wire 120 is used to connect the metal pad 110 of the chip 100 and the first rf port 241 on the top metal layer 240 of the first package substrate, and the bonding wire 120 is formed by using two 25 μm gold wires and is connected by means of wedge bonding or ball bonding. The arrangement of the plating layer on the package substrate 200 can improve the bonding strength with the bonding wire 120, and improve the reliability of the package. The bonding wire 120 may adopt a double-wire or multi-wire form, which can realize a smaller integrated inductance and improve the packaging performance.
In this embodiment, the first rf port 241 is surface-treated by a electroless nickel-palladium plating and gold immersion technique, so as to enhance the bonding tension of the bonding wire 120 and improve the packaging reliability.
Further, the first rf port 241 and the second rf port 221 on the package substrate 200 are directly connected in the form of a microstrip line or a coplanar waveguide, the width of the top metal layer 240 as the first rf port 241 is determined by the thickness and the dielectric constant of the dielectric layer 210, and the metalized via 270 is connected with the second rf port 221 at the bottom of the package substrate 200, so as to implement the feedthrough of the rf signals inside and outside the whole package structure. The major axis of the metalized through-hole 270 is arranged in the up-down direction, i.e., in a form perpendicular to the plate surface of the package substrate 200. The microstrip line is a microwave transmission line formed by a single conductor strip supported on the top dielectric layer 210, and is suitable for manufacturing a planar transmission line of a microwave integrated circuit. Compared with other guided wave systems, the microwave single-chip microwave guided wave system has the advantages of small size, light weight, wide frequency band, suitability for packaging and integration of microwave single chips and the like.
Coplanar waveguide, also called coplanar microstrip transmission line, is to make a central conductor on one surface of a dielectric substrate and to make reference ground conductors on two sides adjacent to the central conductor. In the coplanar waveguide transmission, because the central conductor and the reference ground conductor are positioned in the same plane, the change of an electromagnetic wave transmission mode can be effectively reduced and the radio frequency transmission loss of the chip radio frequency port 111 can be reduced by adopting a coplanar waveguide form in the packaging substrate.
As a specific implementation manner of the embodiment of the present invention, an adhesive layer for adhering to the periphery of the package substrate 200 is disposed at the edge of the bottom surface of the cover 300, and the chip 100 and the groove 250 are adhered by a conductive adhesive. The sealing cover 300 is effectively bonded with the packaging substrate 200 through the adhesive layer on the periphery of the bottom surface, and the adhesive layer is melted through heating during bonding, so that the effect that the sealing cover 300 and the packaging substrate 200 are effectively bonded into a whole is achieved.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to 5, a top surface of the chip 100 is flush with a top surface of the package substrate 200, and a distance between two side surfaces of the chip 100 adjacent to the first rf port 241 and a side surface of the groove 250 is 50 to 200 μm. The arrangement of the groove 250 on the package substrate 200 not only effectively shortens the distance between the chip 100 and the bottom surface of the package substrate 200, and improves the heat dissipation efficiency, but also makes the top surface of the chip 100 and the top surface of the package substrate 200 closer to each other, and when the metal pressure point 110 on the top surface of the chip 100 is connected with the first rf port 241 on the package substrate 200, the connection length can be effectively shortened, and the transmission loss is reduced. In this embodiment, the depth of the groove 250 is consistent with the thickness of the chip 100, so that the top surface of the chip 100 is flush with the top surface of the package substrate 200 after the chip 100 is mounted, the size between the metal pressure point 110 and the first radio frequency port 241 is minimized, the bending radian of the bonding wire 120 is effectively reduced, the metal pressure point 110 is connected with the first radio frequency port 241 through the bonding wire 120, the bonding wire 120 is in a form of two gold wires, the high-frequency transmission capability of the package structure is improved by reducing the parasitic parameters of the bonding wire 120, and the self performance of the millimeter wave amplifier chip is exerted to the maximum.
Further, the distance between the two adjacent side surfaces of the chip 100 and the first rf port 241 and the side surface of the groove 250 should be set to be smaller, in this embodiment, a distance range of 50-200 μm is adopted, the length of the bonding wire 120 can be effectively shortened, and the distance between the other two side edges of the chip 100 and the other two side walls of the groove 250 is not limited, and a larger distance can be adopted to achieve the effect of facilitating processing.
As a specific implementation manner of the embodiment of the present invention, referring to fig. 1 to fig. 5, the bottom metal layer 220 corresponding to the upper and lower portions of the first rf port 241 is provided with a second rf port 221, and the second rf port 221 is connected to the first rf port 241 through a metalized through hole 270. The second rf port 221 and the first rf port 241 on the bottom surface of the package substrate 200 are connected by a metalized through hole 270, and a plurality of grounded solid copper pillars may be formed around the metalized through hole 270 to form a coaxial transmission effect, thereby reducing discontinuity of microwave signal transmission and reducing transmission loss of the metalized through hole 270.
In this embodiment, a form of providing a middle metal layer 230 is adopted, the bottom surface of the groove 250 provided on the dielectric layer 210 located at the top extends to the top surface of the middle metal layer 230, the middle metal layer 230 serves as a conductive layer 251 provided at the bottom of the groove 250, a plurality of copper bars 260 arranged in parallel are provided below the middle metal layer 230, the top surface of the copper bars 260 is communicated with the middle metal layer 230, and the copper bars 260 extend downward to the bottom surface of the dielectric layer 210 located at the lower layer, so as to achieve communication with an external space. Because the copper material has good heat-conducting property, the heat emitted by the chip 100 can be quickly conducted to the outside of the package substrate 200, so that the outward quick transmission of the internal heat is realized, and the over-high temperature of the chip 100 is avoided.
Further, the copper bar 260 may be in the form of a column with a spindle disposed in the vertical direction, and may also achieve the effect of conducting the heat at the intermediate metal layer 230 to the outside of the package substrate 200.
The invention also provides a method for manufacturing the amplifier chip packaging structure, which comprises the following steps:
1. manufacturing a package substrate 200: two dielectric layers 210 are stacked, an intermediate metal layer 230 corresponding to the metal pressure point 110 of the chip 100 is arranged between the two dielectric layers 210, a top metal layer 240 corresponding to the metal pressure point 110 of the chip 100 is arranged on the top dielectric layer 210, a bottom metal layer 220 corresponding to the metal pressure point 110 of the chip 100 is arranged on the bottom dielectric layer 210, the dielectric layer 210 is a high-frequency plate with the thickness of 60um, and the intermediate metal layer 230, the top metal layer 240 and the bottom metal layer 220 are respectively made of copper layers with the thickness of 30 um. A groove 250 is formed in the top dielectric layer 210, the groove depth is 60um, the middle metal layer 230 is exposed at the bottom of the groove 250, and the distance from the edge of the chip 100, which is not adjacent to the first radio frequency port 241 and the second radio frequency port 221, to the edge of the groove 250 is 60 um; the surface of the upper dielectric layer 210 is plated, the plating layer is made of nickel-palladium-gold, and the nickel, palladium and gold are stacked from bottom to top, so that the bonding wire has a soft texture, the adhesion of the bonding wire 120 on the top metal layer 240 is improved, and the adhesion performance is improved.
2. Bonding the chip 100 to the package substrate 200: placing the package substrate 200 on a bonding stage, and bonding the chip 100 into the groove 250 of the package substrate 200 through a high-thermal-conductivity conductive adhesive; the packaging substrate 200 with the bonded chip 100 is placed in a high-temperature oven, the drying temperature is 150 ℃, and the drying time is 4 hours, so that the bonding glue between the chip 100 and the packaging substrate 200 is fully cured, and the requirements of fixing and heat conduction of the chip 100 are met.
3. Bonding the chip radio frequency port 111 and the first radio frequency port 241, placing the packaging substrate 200 bonded with the chip 100 on a bonding table, and heating to 120 ℃ of temperature required by bonding; and bonding the chip radio frequency port 111 and the first radio frequency port 241 by using a 25um gold wire, and bonding the chip direct current port 112 and the first direct current port 242 at the same time.
4. Mounting the cover 300: heating the packaging substrate 200 bonded with the chip 100 to 125 ℃; fixing the sealing cover 300 right above the packaging substrate 200, keeping the temperature of the packaging substrate 200 and the sealing cover 300 unchanged at 125 ℃, applying certain pressure, keeping for 10-30 min to fully melt the adhesive of the sealing cover 300, and continuously heating to 160 ℃ for 1 hour; the packaged chip 100 is naturally cooled to room temperature.
And finally, carrying out appearance and X-ray inspection on the packaged product, judging whether the packaged product is scratched or has the phenomena of bonding wire 120 breaking and the like, and marking the front side of the packaged product by adopting laser.
Further, after the package substrate 200 is manufactured, the package substrate 200 may be bonded to a dicing film, and the package substrate 200 may be diced, which is suitable for small-lot processing tests; the whole packaging structure can be diced after being manufactured, and the method is suitable for being used in large-batch processing production.
According to the method for manufacturing the amplifier chip packaging structure, the molding mode of combining the top metal layer 240, the bottom metal layer 220, the middle metal layer 230 and the plurality of dielectric layers 210 is adopted, the packaging structure manufactured by the mode can effectively improve the manufacturing efficiency, and the packaging cost of the chip 100 can be effectively reduced. This structure is convenient for realize the requirement of multilayer wiring still, utilize the mode of bonding glue adhesion in the recess 250 of packaging substrate 200 with chip 100, not only easy and simple to handle, still effectual length of the bonding wire 120 who has shortened between chip 100 and the top metal level 240, the transmission ability between chip 100 and the packaging substrate 200 has been improved, the loss of radio frequency transmission has been reduced, be applicable to the effective transmission of high frequency wave band, the closing cap 300 that has inner chamber 310 in addition, through the bonding realization structure's with packaging substrate 200 sealed, compare traditional formula of moulding plastics plastic envelope, not only the bonding is simple and convenient still effectual the loss that reduces high frequency wave band. The mounting of the chip 100 is performed by providing the groove 250 in the package substrate 200, which not only facilitates shortening the length of the bonding wire 120, but also effectively shortens the distance between the chip 100 and the bottom surface of the package substrate 200, shortens the heat dissipation path of the chip 100, increases the heat dissipation efficiency, and facilitates stable operation of the chip 100.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. An amplifier chip package, comprising:
the chip comprises a chip, wherein a plurality of metal pressure points are arranged on the outer periphery of the upper surface of the chip, and at least two metal pressure points are chip radio frequency ports;
the packaging substrate is provided with at least two layers of medium layers which are stacked from bottom to top, a groove which is provided with an upward opening and is used for accommodating the chip is arranged on the medium layer positioned on the top layer, a conducting layer is arranged on the bottom surface of the groove, a plurality of top metal layers which are positioned on the periphery of the chip and are respectively in one-to-one correspondence with the metal pressure points are arranged on the top surface of the medium layer, middle metal layers which are in one-to-one correspondence with the top metal layers are arranged between every two adjacent layers of medium layers, and bottom metal layers which are in one-to-one correspondence with the middle metal layers and in one-to-one correspondence; and
and the sealing cover is arranged on the packaging substrate and is used for sealing the packaging substrate, and the sealing cover is provided with an inner cavity with a downward opening.
2. The amplifier chip package of claim 1, wherein the top metal layers corresponding to the chip rf ports are first rf ports, respectively, the chip rf ports are connected to the first rf ports in a one-to-one correspondence, and the bottom metal layers corresponding to the first rf ports are provided with second rf ports, respectively.
3. The amplifier chip package of claim 2, wherein the package substrate has a plurality of copper bars disposed under the conductive layer, the copper bars extending to the bottom metal layer under the grooves, and the tops of the copper bars are connected to the conductive layer.
4. The amplifier chip package of claim 3, wherein the recess extends through a face of the dielectric layer at the top layer, and the conductive layer is flush with the intermediate metal layer.
5. The amplifier chip package of claim 2, wherein the chip rf port is connected to the first rf port by a bond wire; and a plating layer used for bonding with the bonding wire is arranged on the first radio frequency port.
6. The amplifier chip package of claim 5, wherein there are two bonding wires, and the bonding wires are connected to the chip and the first RF port by a wedge bond or a ball bond, respectively.
7. The amplifier chip package according to any one of claims 2 to 6, wherein an adhesive layer is disposed at an edge of a bottom surface of the cover for adhering to an outer periphery of the package substrate, and the chip and the groove are adhered by a conductive adhesive.
8. The amplifier chip package of any one of claims 2-6, wherein a top surface of the chip is flush with a top surface of the package substrate, and wherein a spacing value between two side surfaces of the chip adjacent to the first RF port and a side surface of the recess is 50-200 μm.
9. The amplifier chip package of any one of claims 2-6, wherein the first radio frequency port and the second radio frequency port are connected by a metalized via.
10. A method of making an amplifier chip package according to any of claims 2-9, comprising the steps of:
manufacturing a packaging substrate, stacking the top metal layer, the dielectric layer, the middle metal layer, the dielectric layer and the bottom metal layer, forming a groove on the dielectric layer at the top, and forming a conductive layer in the groove;
bonding the chip to the packaging substrate, placing the packaging substrate on a bonding table, bonding the chip to the groove, and drying the chip and the packaging substrate until bonding glue is cured;
bonding two radio frequency ports to two first radio frequency ports respectively, placing the chip and the packaging substrate on a bonding table, heating the chip and the packaging substrate, and connecting the radio frequency ports of the chip to the corresponding first radio frequency ports respectively;
mounting the cover, and heating the packaging substrate to 125 ℃; and fixing the sealing cover on the packaging substrate, heating and keeping the sealing cover, and then naturally cooling.
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| CN201911101359.7A CN110676224A (en) | 2019-11-12 | 2019-11-12 | Amplifier chip packaging structure and manufacturing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112838366A (en) * | 2020-12-31 | 2021-05-25 | 中国电子科技集团公司第四十三研究所 | Multi-channel surface-mounted T/R assembly |
| CN113281853A (en) * | 2020-02-19 | 2021-08-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN113359248A (en) * | 2021-06-02 | 2021-09-07 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN117936464A (en) * | 2024-03-22 | 2024-04-26 | 成都万应微电子有限公司 | Packaging cavity structure of chip device and method for reducing resonance of packaging cavity |
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2019
- 2019-11-12 CN CN201911101359.7A patent/CN110676224A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113281853A (en) * | 2020-02-19 | 2021-08-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN113281853B (en) * | 2020-02-19 | 2023-01-20 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN112838366A (en) * | 2020-12-31 | 2021-05-25 | 中国电子科技集团公司第四十三研究所 | Multi-channel surface-mounted T/R assembly |
| CN112838366B (en) * | 2020-12-31 | 2024-02-20 | 中国电子科技集团公司第四十三研究所 | Multichannel surface-mounted T/R assembly |
| CN113359248A (en) * | 2021-06-02 | 2021-09-07 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN113359248B (en) * | 2021-06-02 | 2022-11-15 | 青岛海信宽带多媒体技术有限公司 | Optical module |
| CN117936464A (en) * | 2024-03-22 | 2024-04-26 | 成都万应微电子有限公司 | Packaging cavity structure of chip device and method for reducing resonance of packaging cavity |
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