CN110676157A - Optimization of self-aligned quad technology process design using oxide and TiN - Google Patents
Optimization of self-aligned quad technology process design using oxide and TiN Download PDFInfo
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- CN110676157A CN110676157A CN201910883214.0A CN201910883214A CN110676157A CN 110676157 A CN110676157 A CN 110676157A CN 201910883214 A CN201910883214 A CN 201910883214A CN 110676157 A CN110676157 A CN 110676157A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
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Abstract
The invention discloses an optimization of self-aligned quadruple graphic technology process design by utilizing oxide and TiN, wherein SiON and SoC jointly form a mandrel material, and a layer of ploy material is deposited between the mandrel material and a dielectric layer material; the two layers of interval materials respectively adopt oxide and TiN, the oxide is firstly deposited on a mandrel formed by etching on a mandrel material to form a first layer of interval, the mandrel is removed, the first layer of interval is reserved, then TiN is deposited on the first layer of interval formed by the oxide to form a second layer of interval, then the first layer of interval is removed, and the second layer of interval is reserved; transferring the pattern formed by the second layer interval to the ploy material layer, and transferring the pattern formed by the ploy material layer after the ploy material layer is etched to the dielectric material layer for etching, thereby finally completing the etching. The invention adopts oxide and TiN as spacing materials to realize the optimization of the self-aligned quadruple pattern technology process.
Description
Technical Field
The invention relates to the technical field of integrated circuit manufacturing processes, in particular to optimization of self-aligned quad technology (SAQP) process design by utilizing oxide and TiN.
Background
As integrated circuits are rapidly moving toward ultra large scale hybrid integrated circuits (ULSI), the requirements for the feature size of the integrated circuits are becoming smaller and smaller. Many flash memory manufacturers have sought sub-16 nm patterning techniques that can be extended to sub-16 nm half-pitches using immersion ArF lithography using patterning techniques such as self-aligned quad-patterning (120 to 128 nm pitch) or triple-patterning (90 nm pitch).
Two kinds of composite structures for realizing the self-aligned quadruple patterning technology are available, as shown in fig. 1, two layers of mandrel material (carbon) are deposited on a wafer, Oxide is deposited between the two layers of material to be used as an etching barrier layer, the first layer of carbon etching is used for completing the mandrel, a deposition spacing material covers the mandrel, and the spacing side wall of the first deposition transfers the pattern to the second layer of material (carbon) to be used as the mandrel, so as to form a second mandrel. And depositing the second-time interval covering mandrel again, wherein the pattern is finally transferred to the dielectric layer by the side wall of the interval to form a final quadruple pattern.
The second method is shown in fig. 2: in contrast to method one, where the mandrel (carbon) is deposited once, two deposition materials (materials a and b) are selected. And photoetching to finish mandrel etching, depositing a spacing material (material a) on the mandrel, removing the mandrel, keeping the side wall as the mandrel, depositing a layer of spacing (material b) on the left side wall again, removing the first layer of side wall (material a), partially leaving the second layer of side wall (material b), and transferring the pattern to the dielectric layer. Compared with the method (b), the method (a) has the advantages that the deposition of one layer of mandrel material is reduced, the etching of the mandrel in one step is reduced, the influence of the etching process on the characteristic size is reduced, two layers of the method (b) are deposited at intervals in succession, and therefore two completely different materials are required to provide the selective etching ratio.
Experiments have shown that the first method is easier to obtain smaller line widths with better uniformity. The combination of the process flows of the second method is that the key to obtain a line width with better uniformity lies in the selection of two spacing materials, and the selection etching ratio must be higher. The general flow design is to select two non-metal oxides to complete the deposition of two intervals, the non-metal oxide with superior properties can well complete the full coverage of the mandrel, but is not outstanding enough in the selection of etching ratio, for example, the interval material is silicon nitride SIN, amorphous silicon, can complete the self-aligned quadruple pattern, but has poor performance in the overall appearance.
Disclosure of Invention
The invention aims to provide optimization of self-aligned quadruple patterning technology (SAQP) process design by using oxide and TiN aiming at technical defects in the prior art.
The technical scheme adopted for realizing the purpose of the invention is as follows:
the optimization of self-aligned quadruple patterning technology (SAQP) process design by utilizing oxide and TiN comprises the following steps:
forming a mandrel material by SiON and SoC together, and depositing a layer of ploy material between the mandrel material and the dielectric layer material;
the two layers of interval materials respectively adopt oxide and TiN, the oxide is firstly deposited on a mandrel formed by etching on a mandrel material to form a first layer of interval, the mandrel is removed, the first layer of interval is reserved, then TiN is deposited on the first layer of interval formed by the oxide to form a second layer of interval, then the first layer of interval is removed, and the second layer of interval is reserved;
transferring the pattern formed by the second layer interval to the ploy material layer, and transferring the pattern formed by the ploy material layer after the ploy material layer is etched to the dielectric material layer for etching, thereby finally completing the etching.
The invention adopts TiN as the spacing material and the poly layer to modify the pattern appearance, which can obviously improve the uniformity of the characteristic dimension of the final pattern, and can obtain smaller characteristic dimension by controlling the spacing thickness.
The dielectric layer material comprises a metal dielectric layer (IMD layer), and a silicon nitride SiN layer (silicon nitride) and a silicon substrate are sequentially arranged below the metal dielectric layer.
Preferably, the photoresist is spin-coated on SiON, and the photoresist acts as an anti-reflection coating during the exposure and development process of the photoresist, so that the standing wave effect generated during photoetching is inhibited.
The invention adopts oxide and TiN as spacing materials to realize the optimization of the self-aligned quadruple pattern technology process.
Drawings
FIGS. 1-2 are process flow diagrams of two methods for implementing the self-aligned quad technique in the prior art
FIG. 3 is a flow chart of a process for implementing the self-aligned quad scheme technique of the present invention.
In the figure, 1 is a SiON layer, 2 is a SoC layer, and 3 is a SiN (silicon nitride) layer.
Detailed Description
The invention is described in further detail below with reference to the figures and specific examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 3, the present invention utilizes oxide and TiN to realize a self-aligned quadruple patterning technology (SAQP) process, comprising the steps of:
SiON (SiOxNy silicon oxynitride) and SoC (spin-on carbon) jointly form a mandrel, a photoresist is spin-coated on the SiON, and the photoresist serves as an anti-reflection coating in the photoresist exposure and development process, so that a standing wave effect generated in the photoetching process is inhibited, and the verticality of an etched pattern is influenced by the standing wave effect. SiON has good repeatability and uniformity, controls film thickness well during chemical vapor deposition, and is easy to etch, which is necessary for mandrel etching. Meanwhile, in the process of removing the mandrel, the difficulty of the process can be well reduced due to the characteristic that SiON is easy to etch. The spin-coated carbon is only oxidized when being removed, so that the influence of etching on a lower poly layer is reduced, and the overall pattern appearance is more uniform.
A layer of ploy material is deposited between the mandrel material and the dielectric layer material IMD, and the poly material is widely used for preparing large-scale integrated circuits due to the advantage that the self-alignment process is easy to realize. The etched pattern has better vertical characteristic and is used for modifying the pattern transmitted by the second layer interval to improve the uniformity of the final pattern.
The two layers of spacer material are respectively oxide, TiN (titanium nitride), the oxide is first deposited on the mandrel (carbon) as the first layer of spacer, and TiN is subsequently deposited on the oxide to form the second layer of spacer. Oxides andTiN has good step coverage, the thickness of the film is easy to control, and a side wall with good verticality can be formed. Unlike the easy removal of oxide, TiN may remain during etching, which places high demands on the etching gas, with Cl2/CHF3As an etching gas, and CHF is appropriately increased3The gas is better able to remove metal residues, using CHF before etching of the poly layer3/N2The pretreatment of the/Ar can better remove the metal residues, and the generation of the metal residues can be inhibited in the high polymer environment.
Specifically, SiON (SiOxNy silicon oxynitride) and SoC (spin-on carbon), ploy (polysilicon) materials, oxides, TiN (titanium nitride) are used to achieve process optimization. The oxide and TiN have good step coverage, the thickness of the film is easy to control, and a side wall with good verticality can be formed. After the etching of the second layer sidewall is completed, the pattern is transferred to the poly layer, and the pattern with uniform size is obtained by utilizing the better vertical characteristic in the poly etching process. The residual problem of the metal compound during etching is solved by controlling etching gas and pretreating the poly layer and the dielectric layer before etching.
The invention realizes the optimization of the process flow design of the self-aligned quadruple pattern, well reduces the edge roughness of the pattern, improves the integration level, saves the cost and improves the yield of equipment.
The invention adopts TiN as the spacing material and the poly layer to modify the pattern appearance, which can obviously improve the uniformity of the characteristic dimension of the final pattern, and can obtain smaller characteristic dimension by controlling the spacing thickness.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (3)
1. The optimization of self-aligned quadruple patterning technology (SAQP) process design by utilizing oxide and TiN is characterized by comprising the following steps of:
forming a mandrel material by SiON and SoC together, and depositing a layer of ploy material between the mandrel material and the dielectric layer material;
the two layers of interval materials respectively adopt oxide and TiN, the oxide is firstly deposited on a mandrel formed by etching on a mandrel material to form a first layer of interval, the mandrel is removed, the first layer of interval is reserved, then TiN is deposited on the first layer of interval formed by the oxide to form a second layer of interval, then the first layer of interval is removed, and the second layer of interval is reserved;
transferring the pattern formed by the second layer interval to the ploy material layer, and transferring the pattern formed by the ploy material layer after the ploy material layer is etched to the dielectric material layer for etching, thereby finally completing the etching.
The invention adopts TiN as the spacing material and the poly layer to modify the pattern appearance, which can obviously improve the uniformity of the characteristic dimension of the final pattern, and can obtain smaller characteristic dimension by controlling the spacing thickness.
2. Optimization of self-aligned quad technology (SAQP) process design using oxides and TiN according to claim 1, wherein the dielectric layer material comprises a metal dielectric layer, and a silicon nitride layer and a silicon substrate are sequentially arranged under the metal dielectric layer.
3. Optimization of self-aligned quad technology (SAQP) process design using oxide and TiN according to claim 1, wherein the photoresist is spin coated over SiON, acting as an anti-reflective coating during the photoresist exposure development, suppressing standing wave effect during photolithography.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111584430A (en) * | 2020-05-19 | 2020-08-25 | 上海集成电路研发中心有限公司 | Self-aligned quadruple pattern forming method |
| CN111584431A (en) * | 2020-05-19 | 2020-08-25 | 上海集成电路研发中心有限公司 | Self-aligned quadruple pattern forming method |
| CN112670175A (en) * | 2020-12-24 | 2021-04-16 | 长江先进存储产业创新中心有限责任公司 | Method for manufacturing semiconductor structure |
| WO2023279538A1 (en) * | 2021-07-05 | 2023-01-12 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure, and semiconductor structure |
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| CN109119330A (en) * | 2017-06-23 | 2019-01-01 | 中芯国际集成电路制造（天津）有限公司 | A kind of forming method of semiconductor devices |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111584430A (en) * | 2020-05-19 | 2020-08-25 | 上海集成电路研发中心有限公司 | Self-aligned quadruple pattern forming method |
| CN111584431A (en) * | 2020-05-19 | 2020-08-25 | 上海集成电路研发中心有限公司 | Self-aligned quadruple pattern forming method |
| CN111584431B (en) * | 2020-05-19 | 2023-06-02 | 上海集成电路研发中心有限公司 | Self-aligned quadruple pattern forming method |
| CN112670175A (en) * | 2020-12-24 | 2021-04-16 | 长江先进存储产业创新中心有限责任公司 | Method for manufacturing semiconductor structure |
| CN112670175B (en) * | 2020-12-24 | 2024-05-03 | 长江先进存储产业创新中心有限责任公司 | Method for manufacturing semiconductor structure |
| WO2023279538A1 (en) * | 2021-07-05 | 2023-01-12 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure, and semiconductor structure |
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