CN111584430A - Self-aligned quadruple pattern forming method - Google Patents
Self-aligned quadruple pattern forming method Download PDFInfo
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- CN111584430A CN111584430A CN202010425164.4A CN202010425164A CN111584430A CN 111584430 A CN111584430 A CN 111584430A CN 202010425164 A CN202010425164 A CN 202010425164A CN 111584430 A CN111584430 A CN 111584430A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
The invention discloses a method for forming a self-aligned quadruple pattern, which comprises the following steps: forming and patterning a first mandrel layer on a substrate to form a first mandrel pattern; uniformly forming a first sidewall layer on the surface of the first mandrel pattern; removing the first side wall layer material on the top of the first mandrel graph, and forming a first side wall graph on the side wall of the first mandrel graph; filling and flattening the sacrificial layer to expose the tops of the first mandrel graph and the first side wall graph and eliminate the fillet morphology of the top of the first side wall graph; removing the sacrificial layer and the first mandrel pattern, and forming a second mandrel pattern formed by the first side wall pattern on the substrate; uniformly forming a second side wall layer on the surface of the second mandrel graph; and forming a second side wall on the side wall of the second mandrel graph by adopting a side wall etching process, removing the second mandrel graph, and forming a second side wall graph on the substrate. The invention has simple process and accurate pattern size, and can obviously reduce the process control difficulty.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for forming a self-aligned quadruple pattern.
Background
With the continuous shrinking of chip size, after entering the era of three-dimensional Fin field effect transistor (FinFET) technology, especially from the 7nm node, since the pattern period (e.g., 7nm in Fin size and 30nm in pitch) has exceeded the exposure limit of 193nm immersion lithography machine, Self-aligned quad imaging (salp) technology has been introduced to define the pattern, such as the pattern for defining the Fin or the pattern for defining the back-end metal layer.
Referring to fig. 1-10, fig. 1-10 are schematic process flow structures of a conventional self-aligned quad-patterning technique. As shown in fig. 1-10, the process flow of the conventional self-aligned quadruple patterning technology includes:
as shown in fig. 1, a first silicon oxide layer 10, a first amorphous silicon layer 11, a second silicon oxide layer 12, a second amorphous silicon layer 13, and an organic composite barrier layer (including SOC (carbon coating) 14, SiARC (Si-containing anti-reflection coating) 15, and a photoresist layer 16) are formed in this order from bottom to top, and photoresist development is performed by a 193nm immersion lithography process;
as shown in fig. 2, a second amorphous silicon mandrel pattern 13' is formed by etching;
as shown in fig. 3, a first silicon nitride sidewall layer 17 is formed on the second amorphous silicon mandrel pattern 13';
as shown in fig. 4, a first silicon nitride sidewall pattern 17 'is formed by etching, and the second amorphous silicon core axis pattern 13' is removed;
as shown in fig. 5, a second silicon oxide pattern 12 'and a first amorphous silicon mandrel pattern 11' are formed by etching;
as shown in fig. 6, a carbon coating 18 deposition is performed;
as shown in fig. 7, the carbon coating 18 is back etched to expose the second silicon oxide pattern 12';
as shown in fig. 8, the first silicon nitride sidewall patterns 17 'and the second silicon oxide patterns 12' are removed, and the carbon coating 18 is removed;
as shown in fig. 9, a second silicon nitride sidewall layer 19 is formed on the first amorphous silicon core axis pattern 11';
as shown in fig. 10, a second silicon nitride sidewall pattern 19 ' is formed by etching, and the first amorphous silicon mandrel pattern 11 ' is removed, and a regular pattern having the original photoresist pattern pitch 1/4 and using the second silicon nitride sidewall pattern 19 ' as a hard mask is formed on the first silicon oxide layer 10.
However, when the first silicon nitride sidewall pattern is formed by the conventional SAQP technique, a dry etching method is generally adopted, and when anisotropic etching (anisotropic etching) is performed, a sidewall chamfering problem at the top of the first silicon nitride sidewall pattern 17 'may be caused, so that a fillet 171 is formed at a single side of the top of the first silicon nitride sidewall pattern 17'. Due to the rounded corner 171, the first silicon nitride sidewall patterns 17 'are formed into irregular shapes, and thus the second silicon nitride sidewall layer 19 cannot be directly deposited on the first silicon nitride sidewall patterns 17'. Otherwise, the subsequent process cannot be controlled, and pattern transfer must be performed again through dry etching to form the first amorphous silicon mandrel pattern 11' with a flat top, and then deposition and etching of the second silicon nitride sidewall layer 19 are performed. However, this has the disadvantage that the pattern level and the process are complicated, and the etching load effect during the transfer of the first amorphous silicon mandrel pattern 11' is significantly increased, which easily causes the dimensional deviation (i.e., the lateral shift (pitch) of the pattern) during the pattern transfer, thereby increasing the process control difficulty.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art and to provide a method for forming a self-aligned quadruple pattern.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a self-aligned quadruple pattern forming method comprises the following steps:
step S01: providing a substrate, and forming a first mandrel layer on the substrate;
step S02: patterning the first mandrel layer to form a plurality of first mandrel patterns having a first pitch;
step S03: uniformly forming a first side wall layer on the surface of the first mandrel graph;
step S04: removing the first side wall layer material on the top of the first mandrel graph, and forming a first side wall graph with rounded corner appearance on the top of the first mandrel graph side wall;
step S05: filling and flattening a sacrificial layer to expose the tops of the first mandrel graph and the first side wall graph, and further flattening to eliminate the fillet morphology of the top of the first side wall graph to form the first side wall graph with a flat top;
step S06: removing the sacrificial layer and the first mandrel graph, and forming a second mandrel graph formed by the first side wall graph on the substrate;
step S07: uniformly forming a second side wall layer on the surface of the second mandrel graph;
step S08: forming a second side wall on the side wall of the second mandrel graph by adopting a side wall etching process;
step S09: and removing the second mandrel pattern to form the second side wall pattern with a second pitch on the substrate.
Further, step S02 specifically includes: forming a barrier layer and a photoresist layer on the first mandrel layer, developing photoresist, patterning the first mandrel layer by sequentially etching the barrier layer and the first mandrel layer, exposing the substrate, and removing the residual barrier layer material to form the first mandrel pattern.
Further, the barrier layer is an organic composite etching barrier layer, the organic composite etching barrier layer contains a carbon coating and an anti-reflection coating, and the carbon coating comprises an amorphous carbon coating or a carbon-containing organic spin-coating.
Further, an ashing process and a wet cleaning process are adopted to remove the residual carbon coating material.
Further, step S02, step S08 and step S09 are performed in the same reaction chamber.
Further, the reaction cavity is an inductively coupled plasma reaction cavity.
Further, in steps S03 and S07, the first sidewall layer and the second sidewall layer are formed by using an atomic layer deposition process.
Further, in step S05, a flow chemical vapor deposition process is used to fill the sacrificial layer.
Further, in step S05, a chemical mechanical polishing process is used to planarize the first sidewall pattern, and an over-polishing process is used to remove the rounded corner profile at the top of the first sidewall pattern.
Further, in step S06, a wet etching process is used to remove the sacrificial layer and the first mandrel pattern.
The invention can effectively solve the problems of complex process and great process control difficulty in the prior art, and has the following technical advantages:
(1) the structure of the graph is simple, the deposition layers of the film layers are fewer, and the process steps are obviously simplified.
(2) The method reduces the pattern transfer step from the original first silicon nitride side wall pattern (first side wall pattern) to the first amorphous silicon mandrel pattern (second mandrel pattern) in the prior art, thereby reducing the size deviation caused by etching and obviously reducing the process control difficulty.
Drawings
Fig. 1-10 are schematic process flow diagrams of a conventional self-aligned quad-patterning technique.
FIG. 11 is a flowchart illustrating a method for forming a self-aligned quadruple pattern according to a preferred embodiment of the present invention.
Fig. 12-20 are schematic process flow structures of a method for forming a self-aligned quadruple pattern according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 11 in combination with fig. 12 to 20, in which fig. 11 is a flowchart of a self-aligned quadruple pattern forming method according to a preferred embodiment of the present invention, and fig. 12 to 20 are process flow structure diagrams of a self-aligned quadruple pattern forming method according to a preferred embodiment of the present invention. As shown in fig. 11, a method for forming a self-aligned quadruple pattern according to the present invention comprises the steps of:
step S01: a first mandrel layer is formed on a substrate.
Please refer to fig. 12. First, an amorphous silicon substrate 20 may be used, a first mandrel layer 21 formed on the substrate 20, and barrier layers 22, 23 and a photoresist layer 24 formed on the first mandrel layer 21.
As a specific embodiment, a first mandrel layer 21 of silicon oxide, an organic composite etch stop layer 22-24 comprising a carbon coating (SOC)22, a Si-containing anti-reflective coating (SiARC)23 and a photoresist layer 24 (for example, a 193nm immersion lithography process; wherein SOC22 and SiARC23 are used as the stop layers 22, 23) may be deposited sequentially on an amorphous silicon substrate 20. The carbon coating may comprise an amorphous carbon coating or a carbon-containing organic spin-on coating. Wherein, the thickness range of each film layer includes but is not limited to:
silicon oxide first core layer 21:
SOC22：
SiARC23：
photoresist layer 24:
then, resist development is performed to form a resist pattern (24).
Step S02: a plurality of first mandrel patterns having a first pitch are formed.
Please refer to fig. 13. In an inductively coupled plasma reaction chamber (ICP), a first etching of the first mandrel layer 21 of silicon oxide is performed to pattern the first mandrel layer 21. And taking the organic composite barrier layers 22-24 as etching barrier layers, and sequentially etching the SiARC23, the SOC22 and the silicon oxide first mandrel layer 21 to expose the amorphous silicon substrate 20 at the bottom.
After a subsequent ashing (ash) process and a wet cleaning process, the remaining SOC22 material is removed to form a plurality of first core patterns 21' of silicon oxide. The silicon oxide first mandrel pattern 21' has a first pitch a.
Step S03: forming a first sidewall layer.
Please refer to fig. 14. A deposition of a silicon nitride first sidewall layer 25 is performed. In order to improve the Deposition uniformity, an Atomic Layer Deposition (ALD) process may be used to deposit the silicon nitride first sidewall Layer 25 with a thickness of 11-14 nm, and a first sidewall Layer 25 is uniformly formed on the surface of the silicon oxide first mandrel pattern 21'.
Step S04: and forming a first side wall pattern with rounded corner topography at the top.
Please refer to fig. 15. And etching the silicon nitride first side wall layer 25 to form a side wall structure on the side wall of the first mandrel pattern 21'. When the silicon nitride etching is performed, the material of the silicon nitride first sidewall layer 25 at the top of the silicon oxide first mandrel pattern 21 'is etched and removed, and the silicon nitride on the sidewall of the silicon oxide first mandrel pattern 21' is etched to have a sidewall profile (Spacer), so that the silicon nitride first sidewall pattern 25 'with a rounded corner 251 profile at the top is formed on the sidewall of the silicon oxide first mandrel pattern 21'.
Step S05: forming a first sidewall pattern having a flat top.
Please refer to fig. 16. And filling and depositing the sacrificial silicon oxide layer 26 to completely fill the gaps between the silicon nitride first sidewall patterns 25 ', completely cover the first mandrel silicon oxide pattern 21', and keep the top of the sacrificial silicon oxide layer 26 in a smooth shape as much as possible.
The filling of the silicon oxide sacrificial layer 26 may be performed using a Flow Chemical Vapor Deposition (FCVD) process.
The filling thickness can be
Please refer to fig. 17. Next, a Chemical Mechanical Polishing (CMP) process may be used as a planarization process to polish and remove the top of the sacrificial silicon oxide layer 26, exposing the tops of the first mandrel pattern 21 ' and the first sidewall pattern 25 ', and an over-polishing (over-polish) process may be used to flatten the top rounded corners 251 of the first sidewall pattern 25 ' and eliminate the rounded corners 251 of the top of the first sidewall pattern 25 ', thereby forming a first sidewall pattern 25 ' of silicon nitride having a flattened top (e.g., approximately right-angled) 252.
Step S06: forming a second mandrel pattern comprised of the first sidewall pattern.
Please refer to fig. 18. A wet etching process may be used, and the filled sacrificial layer 26 of silicon oxide and the first mandrel pattern 21 ' of silicon oxide are removed by using a high etching selection ratio of silicon oxide to amorphous silicon and silicon nitride (the etching selection ratio of silicon oxide to silicon nitride and silicon may be maintained at > 200:1) to ensure that the shapes of the first sidewall pattern 25 ' of silicon nitride and the silicon substrate 20 are not affected, thereby forming a second mandrel pattern 25 ″ of silicon nitride on the amorphous silicon substrate 20, the second mandrel pattern 25 ″ of silicon nitride being formed by the first sidewall pattern 25 ' of silicon nitride.
Step S07: and forming a second side wall layer.
Please refer to fig. 19. A deposition of a second sidewall layer 27 of silicon oxide is performed. In order to improve the deposition uniformity, an atomic layer deposition process can be used to deposit the silicon oxide second sidewall layer 27 with the thickness of 11-14 nm, and a layer of silicon oxide second sidewall layer 27 is uniformly formed on the surface of the silicon nitride second mandrel pattern 25 ″.
Step S08: and forming a second side wall pattern with a second pitch.
Please refer to fig. 20. And etching the silicon oxide second side wall layer 27 and the silicon nitride second mandrel pattern 25' for the second time in the same inductively coupled plasma reaction chamber (ICP).
By performing the silicon oxide sidewall etching, a silicon oxide second sidewall pattern 27' is formed. This etch requires a high etch selectivity of silicon oxide to amorphous silicon.
Then, the silicon nitride second mandrel pattern 25 "is removed and etched, so that the silicon nitride second mandrel pattern 25" is completely etched, and a silicon oxide second sidewall pattern 27' having a second pitch b is formed. This etch requires a high etch selectivity of silicon nitride to silicon oxide and amorphous silicon. Theoretically the second pitch b is 1/4 of the first pitch a.
And then carrying out wet cleaning. Finally, 1/4 regular patterns with the silicon oxide second sidewall patterns 27' as hard masks and the pitch b as the pitch a of the original pattern are formed, and then the required pattern is finally formed by pattern transfer.
The materials of the film layers such as the substrate 20, the first mandrel layer 21, the barrier layers 22 and 23, the first sidewall layer 25, the sacrificial layer 26, and the second sidewall layer 27 are optional and are not limited to the illustrated materials.
The above description is only a preferred embodiment of the present invention, and the embodiments are not intended to limit the scope of the present invention, so that all equivalent structural changes made by using the contents of the specification and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A self-aligned quadruple pattern forming method is characterized by comprising the following steps:
step S01: providing a substrate, and forming a first mandrel layer on the substrate;
step S02: patterning the first mandrel layer to form a plurality of first mandrel patterns having a first pitch;
step S03: uniformly forming a first side wall layer on the surface of the first mandrel graph;
step S04: removing the first side wall layer material on the top of the first mandrel graph, and forming a first side wall graph with rounded corner appearance on the top of the first mandrel graph side wall;
step S05: filling and flattening a sacrificial layer to expose the tops of the first mandrel graph and the first side wall graph, and further flattening to eliminate the fillet morphology of the top of the first side wall graph to form the first side wall graph with a flat top;
step S06: removing the sacrificial layer and the first mandrel graph, and forming a second mandrel graph formed by the first side wall graph on the substrate;
step S07: uniformly forming a second side wall layer on the surface of the second mandrel graph;
step S08: forming a second side wall on the side wall of the second mandrel graph by adopting a side wall etching process;
step S09: and removing the second mandrel pattern to form the second side wall pattern with a second pitch on the substrate.
2. The method of claim 1, wherein step S02 specifically includes: forming a barrier layer and a photoresist layer on the first mandrel layer, developing photoresist, patterning the first mandrel layer by sequentially etching the barrier layer and the first mandrel layer, exposing the substrate, and removing the residual barrier layer material to form the first mandrel pattern.
3. The method of claim 2, wherein the barrier layer is an organic composite etch barrier layer comprising a carbon coating and an anti-reflective coating, the carbon coating comprising an amorphous carbon coating or a carbon-containing organic spin-on coating.
4. The self-aligned quadruple pattern forming method according to claim 3, wherein the carbon coating material remaining is removed by using an ashing process and a wet cleaning process.
5. The method of claim 1, wherein the steps S02, S08 and S09 are performed in the same reaction chamber.
6. The method of claim 5, wherein the reaction chamber is an inductively coupled plasma reaction chamber.
7. The method of claim 1, wherein the first and second sidewall layers are formed by an atomic layer deposition process in steps S03 and S07.
8. The method of claim 1, wherein the step S05 is performed by a flow chemical vapor deposition process to fill the sacrificial layer.
9. The method of claim 1, wherein in step S05, planarization is performed by using a chemical mechanical polishing process, and the fillet profile at the top of the first sidewall pattern is eliminated by over-polishing.
10. The method as claimed in claim 1, wherein in step S06, the sacrificial layer and the first mandrel pattern are removed by wet etching.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160233104A1 (en) * | 2015-02-09 | 2016-08-11 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices using self-aligned spacers to provide fine patterns |
| CN109119330A (en) * | 2017-06-23 | 2019-01-01 | 中芯国际集成电路制造（天津）有限公司 | A kind of forming method of semiconductor devices |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160233104A1 (en) * | 2015-02-09 | 2016-08-11 | Samsung Electronics Co., Ltd. | Methods of fabricating semiconductor devices using self-aligned spacers to provide fine patterns |
| CN109119330A (en) * | 2017-06-23 | 2019-01-01 | 中芯国际集成电路制造（天津）有限公司 | A kind of forming method of semiconductor devices |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
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Application publication date: 20200825 |