CN111584431A - Self-aligned quadruple pattern forming method - Google Patents
Self-aligned quadruple pattern forming method Download PDFInfo
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- CN111584431A CN111584431A CN202010426156.1A CN202010426156A CN111584431A CN 111584431 A CN111584431 A CN 111584431A CN 202010426156 A CN202010426156 A CN 202010426156A CN 111584431 A CN111584431 A CN 111584431A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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Abstract
The invention discloses a method for forming a self-aligned quadruple pattern, which comprises the following steps: sequentially forming a second mandrel layer and a first mandrel layer on the substrate; forming a first mandrel pattern; forming a first side wall graph on the side wall of the first mandrel graph, and removing the material of a second mandrel layer below the first side wall graph to form a middle graph of a second mandrel; removing the material of the first mandrel graph and the material of the middle graph of the second mandrel below the first mandrel graph to form a second mandrel graph with vertical side wall appearance; removing the first side wall graph; forming a second sidewall pattern on the second mandrel pattern; and removing the second mandrel pattern to form a second side wall pattern on the substrate. The invention can effectively avoid the problem of transferring the asymmetric morphology of the graph and reduce the process difficulty.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for forming a self-aligned quadruple pattern.
Background
With the continuous shrinking of chip size, after entering the era of three-dimensional Fin field effect transistor (FinFET) technology, especially from the 7nm node, since the pattern period (e.g., 7nm in Fin size and 30nm in pitch) has exceeded the exposure limit of 193nm immersion lithography machine, Self-aligned quad imaging (salp) technology has been introduced to define the pattern, such as the pattern for defining the Fin or the pattern for defining the back-end metal layer.
Referring to fig. 1-10, fig. 1-10 are schematic process flow structures of a conventional self-aligned quad-patterning technique. As shown in fig. 1-10, the process flow of the conventional self-aligned quadruple patterning technology includes:
as shown in fig. 1, a first silicon oxide layer 10, a first amorphous silicon layer 11, a second silicon oxide layer 12, a second amorphous silicon layer 13, and an organic composite barrier layer (including SOC (carbon coating) 14, SiARC (Si-containing anti-reflection coating) 15, and a photoresist layer 16) are formed in this order from bottom to top, and photoresist development is performed by a 193nm immersion lithography process;
as shown in fig. 2, a second amorphous silicon mandrel pattern 13' is formed by etching;
as shown in fig. 3, a first silicon nitride sidewall layer 17 is formed on the second amorphous silicon mandrel pattern 13';
as shown in fig. 4, a first silicon nitride sidewall pattern 17 'is formed by etching, and the second amorphous silicon core axis pattern 13' is removed;
as shown in fig. 5, a second silicon oxide pattern 12 'and a first amorphous silicon mandrel pattern 11' are formed by etching;
as shown in fig. 6, a carbon coating 18 deposition is performed;
as shown in fig. 7, the carbon coating 18 is back etched to expose the second silicon oxide pattern 12';
as shown in fig. 8, the first silicon nitride sidewall patterns 17 'and the second silicon oxide patterns 12' are removed, and the carbon coating 18 is removed;
as shown in fig. 9, a second silicon nitride sidewall layer 19 is formed on the first amorphous silicon core axis pattern 11';
as shown in fig. 10, a second silicon nitride sidewall pattern 19 ' is formed by etching, and the first amorphous silicon mandrel pattern 11 ' is removed, and a regular pattern having the original photoresist pattern pitch 1/4 and using the second silicon nitride sidewall pattern 19 ' as a hard mask is formed on the first silicon oxide layer 10.
However, the above conventional sapp technology has the following technical difficulties:
(1) when the first silicon nitride sidewall pattern 17' is formed, a dry etching method is generally adopted, and the shape of the bottom sidewall 171 of the first silicon nitride sidewall layer 17 is required to be kept vertical after etching while anisotropic etching (anisotropic etching); meanwhile, when the first silicon nitride side wall layer 17 is etched, the etching loss on the surface 121 of the substrate layer (the second silicon oxide layer 12) is small, so that the difference of pattern transmission between the inside (the part occupied by the second amorphous silicon core axis pattern 13 ') and the outside (the gap part between the first silicon nitride side wall pattern 17') of the side wall is avoided. However, the difficulty in this method is that these two requirements are contradictory to each other, and it is difficult to achieve a process at the same time, which makes the process adjustment extremely difficult.
(2) After the first silicon nitride sidewall pattern 17 ' is formed, a pattern transfer using the first silicon nitride sidewall pattern 17 ' as a hard mask is required to form a first amorphous silicon mandrel pattern 11 '. The pattern transfer is completed by a one-time dry etching process, and since the two sides of the first silicon nitride side wall pattern 17' have different shapes, the different side wall shapes are transferred downwards at the same time, so that the shapes of the two sides are difficult to adjust in a one-step etching process, the finally formed bottom shape is affected by the shape difference of the side wall, and the symmetry of the finally obtained pattern is lost.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks of the prior art and to provide a method for forming a self-aligned quadruple pattern.
In order to achieve the purpose, the technical scheme of the invention is as follows:
a self-aligned quadruple pattern forming method comprises the following steps:
step S01: providing a substrate, and sequentially forming a second mandrel layer and a first mandrel layer on the substrate;
step S02: patterning the first mandrel layer to form a plurality of first mandrel patterns having a first pitch;
step S03: uniformly forming a first side wall layer on the surface of the first mandrel graph;
step S04: removing the first side wall layer material on the top of the first mandrel graph to form a first side wall graph on the side wall of the first mandrel graph; meanwhile, the first side wall graph and the first mandrel graph are used as masks, the material of the second mandrel layer below the first side wall graph and the first mandrel graph are removed, the second mandrel layer stops on the substrate, and a second mandrel middle graph with a vertical side wall appearance is formed;
step S05: filling a sacrificial layer, removing the sacrificial layer material on the top, exposing the tops of the first mandrel graph and the first side wall graph, and covering the middle graph of the second mandrel;
step S06: removing the first mandrel pattern;
step S07: removing the middle pattern material of the second mandrel below the first side wall pattern and the sacrificial layer by taking the first side wall pattern and the sacrificial layer as masks, stopping on the substrate, and removing the sacrificial layer to form a second mandrel pattern with a vertical side wall appearance;
step S08: removing the first side wall graph;
step S09: uniformly forming a second side wall layer on the surface of the second mandrel graph;
step S10: forming a second side wall pattern on the side wall of the second mandrel pattern by using a side wall etching process;
step S11: and removing the second mandrel pattern to form the second side wall pattern with a second pitch on the substrate.
Further, step S02 specifically includes: forming a barrier layer and a photoresist layer on the first mandrel layer, developing photoresist, patterning the first mandrel layer by sequentially etching the barrier layer and the first mandrel layer, exposing the second mandrel layer, and removing the residual barrier layer material to form the first mandrel pattern.
Further, the barrier layer is an organic composite etching barrier layer, the organic composite etching barrier layer contains a carbon coating and an anti-reflection coating, and the carbon coating comprises an amorphous carbon coating or a carbon-containing organic spin-coating.
Further, an ashing process and a wet cleaning process are adopted to remove the residual carbon coating material.
Further, step S02, step S10 and step S11 are performed in the same reaction chamber.
Further, the reaction cavity is an inductively coupled plasma reaction cavity.
Further, in steps S03 and S09, the first sidewall layer and the second sidewall layer are formed by using an atomic layer deposition process.
Further, in the step S04 and the step S07, the included angle between the vertical side wall and the horizontal plane is 86-89 degrees.
Further, in step S05, a dry etching process is used to back-etch the sacrificial layer and remove the top sacrificial layer material.
Further, in steps S06 and S08, a wet etching process is used to remove the first mandrel pattern and the first sidewall pattern.
The invention can effectively solve the problems of high difficulty of the etching process of the first side wall (the first silicon nitride side wall graph 17') and asymmetric graph transmission in the prior art, and has the following technical advantages:
(1) the process difficulty of the first side wall etching is reduced, the vertical appearance of the side wall and the etching loss of the substrate are respectively realized on the first side wall layer and the second mandrel layer at the bottom, and when the amorphous silicon is adopted as the second mandrel layer at the bottom, the etching selection ratio of the amorphous silicon to the silicon oxide or the silicon nitride easily reaches a very high level, and the requirements of the vertical appearance of the side wall and the less etching loss of the substrate can be easily realized.
(2) The first side wall is in a pattern transfer form of a hard mask and is respectively finished by two independent etching processes, and debugging can be respectively carried out according to different characteristics of the appearances of the two sides of the side wall so as to form a second mandrel pattern with the same appearance of the side wall when the patterns are transferred, thereby avoiding the transfer of asymmetric appearances.
Drawings
Fig. 1-10 are schematic process flow diagrams of a conventional self-aligned quad-patterning technique.
FIG. 11 is a flowchart illustrating a method for forming a self-aligned quadruple pattern according to a preferred embodiment of the present invention.
Fig. 12-22 are schematic process flow structures of a method for forming a self-aligned quadruple pattern according to a preferred embodiment of the invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
In the following detailed description of the embodiments of the present invention, in order to clearly illustrate the structure of the present invention and to facilitate explanation, the structure shown in the drawings is not drawn to a general scale and is partially enlarged, deformed and simplified, so that the present invention should not be construed as limited thereto.
In the following description of the present invention, please refer to fig. 11 in combination with fig. 12 to 22, in which fig. 11 is a flowchart of a self-aligned quadruple pattern forming method according to a preferred embodiment of the present invention, and fig. 12 to 22 are process flow structure diagrams of a self-aligned quadruple pattern forming method according to a preferred embodiment of the present invention. As shown in fig. 11, a method for forming a self-aligned quadruple pattern according to the present invention comprises the steps of:
step S01: a second mandrel layer and a first mandrel layer are sequentially formed on a substrate.
Please refer to fig. 12. First, a substrate 20 may be used, a second mandrel layer 21 and a first mandrel layer 22 may be sequentially formed on the substrate 20, and barrier layers 23, 24 and a photoresist layer 25 may be sequentially formed on the first mandrel layer 22.
As a specific example, amorphous silicon second mandrel layer 21, silicon nitride first mandrel layer 22, and organic composite etch stop layers 23-25 comprising carbon coating (SOC)23, Si-containing anti-reflective coating (SiARC)24, and photoresist layer 25 (for example 193nm immersion lithography; SOC23 and SiARC24 as stop layers 23, 24) may be deposited in sequence on a silicon nitride substrate 20. The carbon coating may comprise an amorphous carbon coating or a carbon-containing organic spin-on coating. Wherein, the thickness range of each film layer includes but is not limited to:
amorphous silicon second mandrel layer 21:
silicon oxide first mandrel layer 22:
SOC23：
SiARC24：
photoresist layer 25:
then, photoresist development is performed to form a photoresist pattern (25).
Step S02: a plurality of first mandrel patterns having a first pitch are formed.
Please refer to fig. 13. The first mandrel layer 22 may be patterned by first etching the first mandrel layer 22 of silicon nitride in an inductively coupled plasma reaction chamber (ICP). And taking the organic composite barrier layers 23-25 as etching barrier layers, and sequentially etching the SiARC24, the SOC23 and the silicon nitride first mandrel layer 22 to expose the amorphous silicon second mandrel layer 21 at the bottom.
After the subsequent ashing process and wet cleaning process, the remaining SOC23 material is removed, and a plurality of silicon nitride first mandrel patterns 22' are formed. The silicon nitride first mandrel pattern 22' has a first pitch a.
Step S03: forming a first sidewall layer.
Please refer to fig. 14. A deposition of a silicon oxide first sidewall layer 26 is performed. In order to improve the Deposition uniformity, an Atomic Layer Deposition (ALD) process may be used to deposit the first sidewall Layer 26 of silicon oxide with a thickness of 11-14 nm, and a Layer of the first sidewall Layer 26 of silicon oxide is uniformly formed on the surface of the first mandrel pattern 22' of silicon nitride.
Step S04: forming a first sidewall pattern and a second mandrel intermediate pattern.
Please refer to fig. 15. And etching the silicon oxide first side wall layer 26 to form a side wall structure on the side wall of the silicon nitride first mandrel pattern 22' by using the silicon oxide. When the silicon oxide etching is performed, the material of the silicon oxide first sidewall layer 26 on the top of the silicon nitride first mandrel pattern 22 'is etched and removed, and the silicon oxide on the sidewall of the silicon nitride first mandrel pattern 22' is etched to form a sidewall profile (Spacer), so that a silicon oxide first sidewall pattern 26 'is formed on the sidewall of the silicon nitride first mandrel pattern 22'.
Meanwhile, taking the first silicon oxide side wall pattern 26 ' and the first silicon nitride core axis pattern 22 ' as masks, continuously etching the amorphous silicon at the bottom, removing the amorphous silicon second core axis layer 21 material below the two adjacent first silicon oxide side wall patterns 26 ', stopping on the silicon nitride substrate 20 at the bottom, completing the pattern transfer of the side wall gap part, forming an amorphous silicon second core axis middle pattern 21 ' with a vertical side wall morphology 211 ', enabling the side wall morphology 211 ' of the bottom amorphous silicon second core axis middle pattern 21 ' to be vertical (the included angle between the side wall and the horizontal plane is 86-89 degrees), and the bottom silicon nitride substrate 20 has less etching loss
Step S05: and filling and back etching the sacrificial layer.
Please refer to fig. 16. Coating the SOC sacrificial layer 27 material to completely fill the gaps between the silicon oxide first sidewall patterns 26 ', completely cover the silicon nitride first mandrel patterns 22', and keep the top of the SOC sacrificial layer 27 in a flat shape as much as possible. The filling thickness of the SOC sacrificial layer 27 may be
Please refer to fig. 17. Next, a dry etching process may be used to perform a back etching process on the top of the SOC sacrificial layer 27 to remove the top of the SOC sacrificial layer 27, so that the first silicon nitride mandrel pattern 22 'is exposed, and the space between the sidewalls is still filled and protected by the SOC sacrificial layer 27, so that the amorphous silicon second mandrel middle pattern 21' is still covered by the SOC sacrificial layer 27. The height difference of the SOC sacrificial layer 27 from the top of the silicon nitride first mandrel pattern 22' may be
Step S06: the first mandrel pattern is removed.
Please refer to fig. 18. The removal of the silicon nitride first mandrel pattern 22' may be performed using a wet etching method using a high etching selectivity of silicon nitride to amorphous silicon and silicon oxide (e.g., hot phosphoric acid).
Step S07: a second mandrel pattern is formed.
Please refer to fig. 19. Etching the amorphous silicon second mandrel middle pattern 21 ' below the removed original silicon nitride first mandrel pattern 22 ' between two opposite silicon oxide first side wall patterns 26 ' by using the silicon oxide first side wall patterns 26 ' and the SOC sacrificial layer 27 as masks, stopping on the silicon nitride substrate 20 to form a second mandrel pattern 21 ', and enabling the side wall features 211 ' on two sides of the bottom amorphous silicon second mandrel pattern 21 ' to be vertical (the included angle between the side wall and the horizontal plane is 86-89 degrees), and the loss of the bottom silicon nitride substrate 20 is less
Please refer to fig. 20. And removing the residual SOC sacrificial layer 27 material through subsequent ashing and wet cleaning processes to complete the pattern transfer from the first side wall to the second mandrel.
Step S08: and removing the first side wall graph.
Please refer to fig. 20. Then, the removal of the remaining silicon oxide first sidewall pattern 26' may be completed by using a wet etching process, leaving only the amorphous silicon second mandrel pattern 21 ″ on the silicon nitride substrate 20.
Step S09: and forming a second side wall layer.
Please refer to fig. 21. A deposition of a silicon oxide second sidewall layer 28 material is performed. In order to improve the deposition uniformity, an atomic layer deposition process can be adopted to deposit the silicon oxide second side wall layer 28 with the thickness of 11-14 nm, and a layer of silicon oxide second side wall layer 28 is uniformly formed on the surface of the amorphous silicon second mandrel pattern 21'.
Step S10: and forming the second side wall pattern with a second pitch.
Please refer to fig. 22. And in the same inductively coupled plasma reaction cavity (ICP), removing and etching the silicon oxide second side wall layer 28 and the amorphous silicon second mandrel pattern 21' for the second time.
A silicon oxide second sidewall pattern 28' is formed by performing a silicon oxide sidewall etch. This etch requires a high etch selectivity of silicon oxide to the underlying silicon nitride substrate 20.
Then, the amorphous silicon second mandrel pattern 21 "is removed and etched, so that the amorphous silicon second mandrel pattern 21" is etched clean, and a silicon oxide second sidewall pattern 28' with a second pitch b is formed. Theoretically the second pitch b is 1/4 of the first pitch a.
And then carrying out wet cleaning. Finally, 1/4 regular patterns with the silicon oxide second sidewall patterns 28' as hard masks and the pitch b as the pitch a of the original pattern are formed, and then the required pattern is finally formed by pattern transfer.
The materials of the film layers such as the substrate 20, the second mandrel layer 21, the first mandrel layer 22, the barrier layers 23 and 24, the first sidewall layer 26, the sacrificial layer 27, and the second sidewall layer 28 are optional and not limited to the illustrated materials.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (10)
1. A self-aligned quadruple pattern forming method is characterized by comprising the following steps:
step S01: providing a substrate, and sequentially forming a second mandrel layer and a first mandrel layer on the substrate;
step S02: patterning the first mandrel layer to form a plurality of first mandrel patterns having a first pitch;
step S03: uniformly forming a first side wall layer on the surface of the first mandrel graph;
step S04: removing the first side wall layer material on the top of the first mandrel graph to form a first side wall graph on the side wall of the first mandrel graph; meanwhile, the first side wall graph and the first mandrel graph are used as masks, the material of the second mandrel layer below the first side wall graph and the first mandrel graph are removed, the second mandrel layer stops on the substrate, and a second mandrel middle graph with a vertical side wall appearance is formed;
step S05: filling a sacrificial layer, removing the sacrificial layer material on the top, exposing the tops of the first mandrel graph and the first side wall graph, and covering the middle graph of the second mandrel;
step S06: removing the first mandrel pattern;
step S07: removing the middle pattern material of the second mandrel below the first side wall pattern and the sacrificial layer by taking the first side wall pattern and the sacrificial layer as masks, stopping on the substrate, and removing the sacrificial layer to form a second mandrel pattern with a vertical side wall appearance;
step S08: removing the first side wall graph;
step S09: uniformly forming a second side wall layer on the surface of the second mandrel graph;
step S10: forming a second side wall pattern on the side wall of the second mandrel pattern by using a side wall etching process;
step S11: and removing the second mandrel pattern to form the second side wall pattern with a second pitch on the substrate.
2. The method of claim 1, wherein step S02 specifically includes: forming a barrier layer and a photoresist layer on the first mandrel layer, developing photoresist, patterning the first mandrel layer by sequentially etching the barrier layer and the first mandrel layer, exposing the second mandrel layer, and removing the residual barrier layer material to form the first mandrel pattern.
3. The method of claim 2, wherein the barrier layer is an organic composite etch barrier layer comprising a carbon coating and an anti-reflective coating, the carbon coating comprising an amorphous carbon coating or a carbon-containing organic spin-on coating.
4. The self-aligned quadruple pattern forming method according to claim 3, wherein the carbon coating material remaining is removed by using an ashing process and a wet cleaning process.
5. The method of claim 1, wherein the steps S02, S10 and S11 are performed in the same reaction chamber.
6. The method of claim 5, wherein the reaction chamber is an inductively coupled plasma reaction chamber.
7. The method of claim 1, wherein the first and second sidewall layers are formed by an atomic layer deposition process in steps S03 and S09.
8. The method of claim 1, wherein the vertical sidewall has an angle of 86-89 degrees with respect to a horizontal plane in steps S04 and S07.
9. The method of claim 1, wherein in step S05, the sacrificial layer is etched back by a dry etching process to remove the top sacrificial layer material.
10. The method of claim 1, wherein the first mandrel pattern and the first sidewall pattern are removed by a wet etching process in steps S06 and S08.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103794475A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Self aligned triple patterning method |
| US9620380B1 (en) * | 2015-12-17 | 2017-04-11 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits using self-aligned quadruple patterning |
| US9773680B1 (en) * | 2016-12-13 | 2017-09-26 | Globalfoundries Inc. | Advanced method for scaled SRAM with flexible active pitch |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
| CN110867369A (en) * | 2019-11-25 | 2020-03-06 | 长江存储科技有限责任公司 | Self-aligned quadruple pattern and method for manufacturing semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794475A (en) * | 2012-10-30 | 2014-05-14 | 中芯国际集成电路制造(上海)有限公司 | Self aligned triple patterning method |
| US9620380B1 (en) * | 2015-12-17 | 2017-04-11 | GlobalFoundries, Inc. | Methods for fabricating integrated circuits using self-aligned quadruple patterning |
| US9773680B1 (en) * | 2016-12-13 | 2017-09-26 | Globalfoundries Inc. | Advanced method for scaled SRAM with flexible active pitch |
| CN110676157A (en) * | 2019-09-18 | 2020-01-10 | 天津大学 | Optimization of self-aligned quad technology process design using oxide and TiN |
| CN110867369A (en) * | 2019-11-25 | 2020-03-06 | 长江存储科技有限责任公司 | Self-aligned quadruple pattern and method for manufacturing semiconductor device |
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