CN110660435A - MRAM memory cell, array and memory - Google Patents
MRAM memory cell, array and memory Download PDFInfo
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- CN110660435A CN110660435A CN201810687747.7A CN201810687747A CN110660435A CN 110660435 A CN110660435 A CN 110660435A CN 201810687747 A CN201810687747 A CN 201810687747A CN 110660435 A CN110660435 A CN 110660435A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
Abstract
The invention provides an MRAM memory unit, an array and a memory, wherein the memory unit comprises: the magnetic tunnel junction device comprises two vertically stacked magnetic tunnel junctions, a selector element and a transistor, wherein an isolation layer is arranged between the two magnetic tunnel junctions, a reference layer of each magnetic tunnel junction is arranged close to the isolation layer, a spin orbit torque providing line is arranged on the outer side of a free layer of each magnetic tunnel junction, two ends of the selector element are connected to the two spin orbit torque providing lines through metal connecting layers, and a drain of the transistor is connected with one end, close to the selector element, of any one spin orbit torque providing line; one end of each of the two spin orbit torque supply lines, which is close to the magnetic tunnel junction, is led out to form an end point for connecting a bit line, one end point for connecting a word line is led out from a grid electrode of the transistor, and one end point for connecting a source line is led out from a source electrode of the transistor. The invention can improve the storage density of the memory.
Description
Technical Field
The present invention relates to the field of magnetic memory technology, and in particular, to an MRAM memory cell, array, and memory.
Background
The core of a Memory cell of a conventional Magnetic Memory (MRAM) is a Magnetic tunnel junction MTJ (MTJ), which is a two-port structure device composed of a multilayer film, the core is mainly composed of three films, two ferromagnetic layers are separated by a tunneling barrier layer, the magnetization direction of one of the ferromagnetic layers is fixed and is called a fixed layer or a reference layer, the magnetization direction of the other ferromagnetic layer can be changed and is called a free layer, and the magnetization direction of the free layer can be Parallel to the magnetization direction of the reference layer (Parallel, P for short) or Anti-Parallel to the magnetization direction of the reference layer (Anti-Parallel, AP for short). When the magnetization directions of the two ferromagnetic layers are parallel, the MTJ assumes a low resistance state, whereas when the magnetization directions of the two ferromagnetic layers are anti-parallel, the MTJ assumes a high resistance state. These two distinct resistance states can be used to characterize binary data "0" and "1" respectively at the time of information storage.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the existing MRAM memory can only store two states of '0' and '1', and the storage density is low.
Disclosure of Invention
To solve the above problems, the present invention provides an MRAM memory cell, an array and a memory, which can improve the storage density of the memory.
In a first aspect, the present invention provides an MRAM memory cell comprising two vertically stacked magnetic tunnel junctions, a selector element and a transistor, wherein,
an isolation layer is arranged between the two magnetic tunnel junctions, a reference layer of each magnetic tunnel junction is arranged close to the isolation layer, a spin orbit torque providing line is arranged on the outer side of a free layer of each magnetic tunnel junction, two ends of the selector element are connected to the two spin orbit torque providing lines through metal connecting layers, and a drain of the transistor is connected with one end, close to the selector element, of any one spin orbit torque providing line;
one end of each of the two spin orbit torque supply lines, which is close to the magnetic tunnel junction, is led out to form an end point for connecting a bit line;
the grid of the transistor leads out a terminal point which is used for connecting a word line;
and the source electrode of the transistor leads out a terminal point which is used for connecting a source line.
Optionally, both of the magnetic tunnel junctions are in-plane magnetized MTJs or out-of-plane perpendicular magnetized MTJs.
Optionally, when the two magnetic tunnel junctions are in-plane magnetization MTJs, the isolation layer between the two magnetic tunnel junctions comprises a non-magnetic isolation layer; when the two magnetic tunnel junctions are out-of-plane perpendicular magnetization MTJs, the isolation layer between the two magnetic tunnel junctions comprises two non-magnetic isolation layers and reference layers respectively close to the two magnetic tunnel junctions, an in-plane magnetized magnetic layer is further arranged between the two non-magnetic isolation layers, and the magnetization direction of the in-plane magnetized magnetic layer is parallel or antiparallel to the current direction.
Optionally, the spin orbit torque provides a length of the line greater than a characteristic length of the magnetic tunnel junction being approached.
Optionally, the material of the spin orbit torque providing wire is a heavy metal, a topological insulator BiSe alloy, or an antiferromagnetic alloy.
Optionally, the selector element has a bidirectional conduction function, the conduction threshold voltage being lower than the MTJ write voltage while being higher than the MTJ read voltage.
Optionally, the selector element is a silicon material based diode or a combination of diodes.
In a second aspect, the present invention provides an MRAM memory array, including a plurality of pairs of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of the MRAM memory cells, wherein four terminals of each MRAM memory cell are respectively connected to a set of bit lines, a word line, and a source line.
In a third aspect, the present invention provides an MRAM memory comprising the MRAM memory array described above.
The MRAM memory unit provided by the invention is a four-terminal device and can store four states, while the existing memory unit can only store two states, so that the storage density of the memory based on the MRAM memory unit can be doubled. Meanwhile, a selector element with small occupied area is added in the memory unit, and only one transistor is needed to realize read-write control, so that the area of the memory is favorably reduced.
Drawings
FIG. 1 is a schematic diagram of an MRAM memory cell according to an embodiment of the invention;
FIG. 2 is a schematic diagram of another embodiment of an MRAM memory cell of the invention;
FIG. 3 is a schematic diagram of the current and magnetization directions in a first step of writing state 1 or 2 into the MRAM memory cell of FIG. 1;
FIG. 4 is a schematic diagram of the current and magnetization directions in a second step of writing state 1 into the MRAM memory cell of FIG. 1;
FIG. 5 is a schematic diagram of the current and magnetization directions in a second step of writing state 2 into the MRAM memory cell of FIG. 1;
FIG. 6 is a schematic diagram of the current and magnetization directions in a first step of writing states 3 or 4 into the MRAM memory cell of FIG. 1;
FIG. 7 is a schematic diagram of the current and magnetization directions in a second step of writing state 3 into the MRAM memory cell of FIG. 1;
FIG. 8 is a schematic diagram of the current and magnetization directions in a second step of writing state 4 into the MRAM memory cell of FIG. 1;
FIG. 9 is a schematic current diagram illustrating a state read of the MRAM memory cell of FIG. 1;
FIG. 10 is a connection diagram of an embodiment of an MRAM memory array of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an MRAM memory cell, as shown in fig. 1, which includes two vertically stacked magnetic tunnel junctions MTJ1 and MTJ2 (hereinafter, the magnetic tunnel junction is abbreviated as MTJ for simplicity), a selector element S1, and a transistor M1, wherein,
MTJ1 and MTJ2 are in-plane magnetized MTJs, a nonmagnetic spacer layer is disposed between the two MTJs, a reference layer of each MTJ is close to the nonmagnetic spacer layer, a free layer is away from the nonmagnetic spacer layer, one spin orbit torque supply line is disposed outside each free layer, a free layer of MTJ1 is close to spin orbit torque supply line 1, a free layer of MTJ2 is close to spin orbit torque supply line 2, both ends of selector element S1 are connected to the two spin orbit torque supply lines through metal connection layers, a drain of transistor M1 is connected to an end of any one spin orbit torque supply line close to selector element S1, a drain of M1 in fig. 1 is connected to an end of spin orbit torque supply line 1 close to selector element S1, an end of spin orbit torque supply line 1 close to the magnetic tunnel junction leads to a first end point, which is connected to first bit line BL 1; one end of the spin orbit torque supply line 2 near the magnetic tunnel junction leads out a second end point, which is connected to a second bit line BL 2; the gate of transistor M1 leads to a third terminal, which is connected to word line WL; the source of the transistor M1 leads to a fourth terminal, which is connected to the source line SL.
Fig. 2 shows another embodiment of an MRAM memory cell in accordance with the present invention. The difference from FIG. 1 is that the two vertically stacked MTJs are out-of-plane perpendicularly magnetized MTJs, and the separation layer between the two MTJs has a different structure for different types of MTJs. In FIG. 2, the spacer layer between MTJ1 and MTJ2 comprises two nonmagnetic spacer layers, a reference layer adjacent to each of the two magnetic tunnel junctions, and a magnetic layer with in-plane magnetization parallel or anti-parallel to the direction of current flow.
Further, in the above embodiments, the vertically stacked MTJ1 and MTJ2 have different structures, have different parallel state resistance Rp and anti-parallel state resistance Rap, have different thicknesses of the barrier layer (e.g., MgO), and have different thicknesses of feature size (diameter).
The spin orbit torque provides a line length greater than the characteristic length of the magnetic tunnel junction in proximity, the spin orbit torque provides a line 1 length greater than the characteristic length of MTJ1, and the spin orbit torque provides a line 2 length greater than the characteristic length of MTJ 2. The material of the spin orbit torque supply wire is a material having a spin orbit torque effect, and a heavy metal such as Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au, Os can be used, a topological insulator BiSe alloy such as Bi2Se3, BiTe alloy, BiSeTe alloy, TlBiSe can be used, and an antiferromagnetic alloy such as PtMn, IrMn or the like can be used.
For the selector element S1, which has a bidirectional conduction function, the conduction threshold voltage Vth is lower than the MTJ write voltage and higher than the MTJ read voltage, typically between 0.1V and 1V, which ensures that the selector element S1 is turned on when the memory cell writes data and the selector element S1 is turned off when the memory cell state is read. The material of the selector element S1 may be one of CuGeSe, HfO, etc., or a diode or combination of diodes based on silicon material.
The MRAM memory unit provided by the embodiment of the invention is a four-terminal element, information is written based on spin orbit torque, four states can be stored, and compared with the existing memory unit, the storage density of a memory can be doubled. Meanwhile, a selector element with small occupied area is added in the memory unit, and only one transistor is needed to realize read-write control, so that the area of the memory is favorably reduced.
The writing process for each state is described below using the MRAM memory cell shown in fig. 1 as an example, and the writing process for each state is performed in two steps.
Let Va be the first write voltage, Vb be the second write voltage, Vth be the turn-on threshold voltage of selector element S1, Vc be the applied voltage that MTJ realized free layer inversion through traditional STT mode (i.e. MTJ passed the write voltage of traditional STT mode), then it needs to satisfy Vth < Va < Vc, Vth < Vb < Vc, and guarantee that selector element S1 is always in the on state during write-in. Once Va or Vb exceeds Vc, the MTJ realizes free layer inversion by a traditional STT mode, and therefore Va or Vb does not exceed Vc. Transistor M1 is always on during the write process.
Writing state 1: first, as shown in FIG. 3, applying voltage-Va to BL1 while BL2 is off, with the current path providing lines 1-BL1 for the transistor-spin orbit torque, MTJ1 flips to the parallel state; in a second step, as shown in FIG. 4, BL1 is turned off and BL2 applies voltage Vb, while the current path is BL 2-spin orbit torque supply line 2-selector element-spin orbit torque supply line 1-transistor, MTJ2 also flips to the parallel state, and the total resistance of both MTJs is Rp1+ Rp 2.
Writing state 2: the first step, like the first step of writing state 1, is to first apply voltage-Va to BL1 while BL2 is off, at which time the current path provides lines 1-BL1 for the transistor-spin orbit torque, MTJ1 flips to the parallel state; in a second step, as shown in FIG. 5, BL1 is turned off and BL2 applies a voltage-Vb, where the current path is transistor-spin orbit torque providing line 1-selector element-spin orbit torque providing line 2-BL2, MTJ2 flips to the anti-parallel state, and the total resistance of both MTJs is Rp1+ Rap 2.
Write state 3: first, as shown in FIG. 6, voltage Va is applied to BL1 while BL2 is turned off, when the current path is BL 1-the spin orbit torque providing line 1-transistor, MTJ1 flips to the anti-parallel state; in a second step, as shown in FIG. 7, BL1 is turned off and BL2 applies voltage Vb, while the current path is BL 2-spin orbit torque supply line 2-selector element-spin orbit torque supply line 1-transistor, MTJ2 flips to the parallel state, and the total resistance of both MTJs is Rap1+ Rp 2.
Write state 4: first, as in the first step of writing state 3, voltage Va is first applied to BL1 while BL2 is turned off, at which time the current path is BL 1-the spin orbit torque providing line 1-transistor, MTJ1 flips to the anti-parallel state; in a second step, as shown in fig. 8, BL1 is turned off, BL2 applies a voltage-Vb, when the current path is transistor-spin orbit torque supply line 1-selector element-spin orbit torque supply line 2-BL2,
the MTJ2 flips to the anti-parallel state and the total resistance of the two MTJs is Rap1+ Rap 2.
The circuit state during the above-described writing process can be represented by the following table:
in the MRAM memory cell according to the embodiment of the present invention, when the state is read, one of the bit lines connected to the spin orbit torque supply line connected to the drain of the transistor is disconnected, and the bit line applied voltage Vr, Vr being denoted as the MTJ read voltage, connected to the spin orbit torque supply line not connected to the transistor is satisfied with Vr < Vth, that is, the selector element S1 is ensured to be disconnected.
Also taking the MRAM memory cell shown in fig. 1 as an example, referring to fig. 9, the drain of the transistor M1 is connected to the spin orbit torque supply line 1, so that BL1 is off, BL2 applies a voltage Vr, the transistor is on, the current path is BL2 — spin orbit torque supply line 2-MTJ2-MTJ1 — spin orbit torque supply line 1-transistor M1-source line SL, the total resistance value R ═ Vr/I of MTJ1 and MTJ2 can be calculated by measuring the current I flowing through the bit line BL2 to which the voltage Vr is applied, and since the total resistances of the four states are different, the four states can be read, wherein the total resistance of state 1 is Rp1+ Rp2, the total resistance of state 2 is Rp1+ Rap2, the total resistance of state 3 is Rap1+ Rp2, and the total resistance of state 4 is Rap1+ Rap 2.
As can be seen from the above description, the selector element is on when the MRAM memory cell is writing and off when the memory cell is reading the state. When reading the state, the MTJ reading voltage Vr applied by the bit line is less than the conduction threshold voltage Vth of the selector element, so as to ensure that the selector element is disconnected; the bit line applies a write voltage Va or Vb greater than Vth during writing, which ensures that the selector element is turned on, but at the same time Va or Vb cannot exceed Vc, which ensures that the free layer inversion is based on spin-orbit torque.
For the MRAM memory cell shown in fig. 2, the writing process and the state reading process are similar to those of the MRAM memory cell shown in fig. 1, and are not described again here.
The embodiment of the invention also provides an MRAM memory array, which comprises a plurality of groups of paired bit lines, a plurality of word lines, a plurality of source lines and a plurality of MRAM memory cells provided in the embodiments, wherein four end points of each memory cell are respectively connected with one group of bit lines, one word line and one source line. Referring to fig. 10, a specific embodiment of an MRAM memory array, which includes 3 pairs of bit lines, 3 word lines, 3 source lines, and 9 memory cells, is shown in fig. 10.
The embodiment of the invention also provides an MRAM memory, which comprises the MRAM memory array.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. An MRAM memory cell, comprising two vertically stacked magnetic tunnel junctions, a selector element and a transistor, wherein,
an isolation layer is arranged between the two magnetic tunnel junctions, a reference layer of each magnetic tunnel junction is arranged close to the isolation layer, a spin orbit torque providing line is arranged on the outer side of a free layer of each magnetic tunnel junction, two ends of the selector element are connected to the two spin orbit torque providing lines through metal connecting layers, and a drain of the transistor is connected with one end, close to the selector element, of any one spin orbit torque providing line;
one end of each of the two spin orbit torque supply lines, which is close to the magnetic tunnel junction, is led out to form an end point for connecting a bit line;
the grid of the transistor leads out a terminal point which is used for connecting a word line;
and the source electrode of the transistor leads out a terminal point which is used for connecting a source line.
2. The MRAM memory cell of claim 1, wherein both of the magnetic tunnel junctions are in-plane magnetization MTJs or out-of-plane perpendicular magnetization MTJs.
3. The MRAM memory cell of claim 2, wherein when both of the magnetic tunnel junctions are in-plane magnetization MTJs, the isolation layer between the two magnetic tunnel junctions comprises a layer of non-magnetic isolation layer; when the two magnetic tunnel junctions are out-of-plane perpendicular magnetization MTJs, the isolation layer between the two magnetic tunnel junctions comprises two non-magnetic isolation layers and reference layers respectively close to the two magnetic tunnel junctions, an in-plane magnetized magnetic layer is further arranged between the two non-magnetic isolation layers, and the magnetization direction of the in-plane magnetized magnetic layer is parallel or antiparallel to the current direction.
4. The MRAM memory cell of claim 1, wherein the spin orbit torque providing line has a length greater than a characteristic length of the magnetic tunnel junction being approached.
5. The MRAM memory cell of claim 1, wherein the material of the spin orbit torque providing line is a heavy metal, a topological insulator BiSe alloy, or an antiferromagnetic alloy.
6. The MRAM memory cell of claim 1, wherein the selector element has a bidirectional conduction function, a conduction threshold voltage being lower than an MTJ write voltage while being higher than an MTJ read voltage.
7. The MRAM memory cell of claim 1, wherein the selector element is a diode or a combination of diodes based on a silicon material.
8. An MRAM memory array comprising a plurality of pairs of bit lines, a plurality of word lines, a plurality of source lines, and a plurality of MRAM memory cells according to any one of claims 1 to 7, wherein four terminals of each of the MRAM memory cells are connected to a respective one of the bit lines, one of the word lines, and one of the source lines.
9. An MRAM memory, comprising the MRAM memory array of claim 8.
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| CN116723704B (en) * | 2023-08-09 | 2023-10-17 | 苏州凌存科技有限公司 | Magnetic random access memory and preparation method thereof |
| CN116723704A (en) * | 2023-08-09 | 2023-09-08 | 苏州凌存科技有限公司 | Magnetic random access memory and preparation method thereof |
| CN117500282A (en) * | 2024-01-02 | 2024-02-02 | 致真存储(北京)科技有限公司 | Magnetic memory, preparation method thereof and electronic equipment |
| CN117500282B (en) * | 2024-01-02 | 2024-04-02 | 致真存储(北京)科技有限公司 | Magnetic memory, preparation method thereof and electronic equipment |
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